SystemVerilog.hs

{- sv2v
 - Author: Tom Hawkins <tomahawkins@gmail.com>
 -
 - A parser for SystemVerilog.
 -}
module Language.SystemVerilog
    ( module Language.SystemVerilog.AST
    , module Language.SystemVerilog.Parser
    ) where

import Language.SystemVerilog.AST
import Language.SystemVerilog.Parser