fp-armv8 is currently defined as a double precision FPv5 with 32 D
registers *and* a special FP_ARMv8 bit. However FP for ARMv8 should only
bring 32 D registers on top of FPv5-D16 so this FP_ARMv8 bit is
spurious. As a consequence, many instruction patterns which are guarded
by TARGET_FPU_ARMV8 are unavailable to FPv5-D16 and FPv5-SP-D16.

This commit gets rid of TARGET_FPU_ARMV8 and rewire all uses to
expressions based on TARGET_VFP5, TARGET_VFPD32 and TARGET_VFP_DOUBLE.
It also redefine ISA_FP_ARMv8 to include the D32 capability to
distinguish it from FPv5-D16. At last, it sets the +fp.sp for ARMv8-R to
enable FPv5-SP-D16 (ie FP for ARMv8 with single precision only and 16 D
registers).

2017-07-14  Thomas Preud'homme  <thomas.preudhomme@arm.com>

    gcc/
    * config/arm/arm-isa.h (isa_bit_FP_ARMv8): Delete enumerator.
    (ISA_FP_ARMv8): Define as ISA_FPv5 and ISA_FP_D32.
    * config/arm/arm-cpus.in (armv8-r): Define fp.sp as enabling FPv5.
    (fp-armv8): Define it as FP_ARMv8 only.
    config/arm/arm.h (TARGET_FPU_ARMV8): Delete.
    (TARGET_VFP_FP16INST): Define using TARGET_VFP5 rather than
    TARGET_FPU_ARMV8.
    config/arm/arm.c (arm_rtx_costs_internal): Replace checks against
    TARGET_FPU_ARMV8 by checks against TARGET_VFP5.
    * config/arm/arm-builtins.c (arm_builtin_vectorized_function): Define
    first ARM_CHECK_BUILTIN_MODE definition using TARGET_VFP5 rather
    than TARGET_FPU_ARMV8.
    * config/arm/arm-c.c (arm_cpu_builtins): Likewise for
    __ARM_FEATURE_NUMERIC_MAXMIN macro definition.
    * config/arm/arm.md (cmov<mode>): Condition on TARGET_VFP5 rather than
    TARGET_FPU_ARMV8.
    * config/arm/neon.md (neon_vrint): Likewise.
    (neon_vcvt): Likewise.
    (neon_<fmaxmin_op><mode>): Likewise.
    (<fmaxmin><mode>3): Likewise.
    * config/arm/vfp.md (l<vrint_pattern><su_optab><mode>si2): Likewise.
    * config/arm/predicates.md (arm_cond_move_operator): Check against
    TARGET_VFP5 rather than TARGET_FPU_ARMV8 and fix spacing.

From-SVN: r250204