Atomics use DMB instruction to enforce ordering of loads/stores.
Currently gcc generates DMB w/o any arg which is a no-op. Fix that by
generating DMB 3 which enforces R+W ordering. It is stricter than what
acq/rel expect, but there's no other way.

gcc/

2019-xx-xx  Vineet Gupta <vgupta@synopsys.com>

       * config/arc/atomic.md: Add operand to DMB instruction

From-SVN: r268181