[ARC] atomics: Add operand to DMB instruction

Atomics use DMB instruction to enforce ordering of loads/stores.
Currently gcc generates DMB w/o any arg which is a no-op. Fix that by
generating DMB 3 which enforces R+W ordering. It is stricter than what
acq/rel expect, but there's no other way.

gcc/

2019-xx-xx  Vineet Gupta <vgupta@synopsys.com>

       * config/arc/atomic.md: Add operand to DMB instruction

From-SVN: r268181

gcc/ChangeLog

+2019-01-23  Vineet Gupta  <vgupta@synopsys.com>
+
+	* config/arc/atomic.md: Add operand to DMB instruction.
+
 2019-01-23  Jakub Jelinek  <jakub@redhat.com>
 
 	PR tree-optimization/88964

gcc/config/arc/atomic.md

@@ -44,7 +44,7 @@
   {
    if (TARGET_HS)
       {
-       return "dmb";
+       return "dmb\\t3";
       }
     else
       {