Following MVE ACLE intrinsics have an issue with writeback to the base address.

vldrdq_gather_base_wb_s64, vldrdq_gather_base_wb_u64, vldrdq_gather_base_wb_z_s64, vldrdq_gather_base_wb_z_u64, vldrwq_gather_base_wb_s32, vldrwq_gather_base_wb_u32, vldrwq_gather_base_wb_z_s32, vldrwq_gather_base_wb_z_u32, vldrwq_gather_base_wb_f32, vldrwq_gather_base_wb_z_f32.

This patch fixes the bug reported in PR94317 by adding separate builtin calls to update the result and writeback to base address for the above intrinsics.

2020-04-02  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>

	PR target/94317
	* config/arm/arm-builtins.c (LDRGBWBXU_QUALIFIERS): Define.
	(LDRGBWBXU_Z_QUALIFIERS): Likewise.
	* config/arm/arm_mve.h (__arm_vldrdq_gather_base_wb_s64): Modify
	intrinsic defintion by adding a new builtin call to writeback into base
	address.
	(__arm_vldrdq_gather_base_wb_u64): Likewise.
	(__arm_vldrdq_gather_base_wb_z_s64): Likewise.
	(__arm_vldrdq_gather_base_wb_z_u64): Likewise.
	(__arm_vldrwq_gather_base_wb_s32): Likewise.
	(__arm_vldrwq_gather_base_wb_u32): Likewise.
	(__arm_vldrwq_gather_base_wb_z_s32): Likewise.
	(__arm_vldrwq_gather_base_wb_z_u32): Likewise.
	(__arm_vldrwq_gather_base_wb_f32): Likewise.
	(__arm_vldrwq_gather_base_wb_z_f32): Likewise.
	* config/arm/arm_mve_builtins.def (vldrwq_gather_base_wb_z_u): Modify
	builtin's qualifier.
	(vldrdq_gather_base_wb_z_u): Likewise.
	(vldrwq_gather_base_wb_u): Likewise.
	(vldrdq_gather_base_wb_u): Likewise.
	(vldrwq_gather_base_wb_z_s): Likewise.
	(vldrwq_gather_base_wb_z_f): Likewise.
	(vldrdq_gather_base_wb_z_s): Likewise.
	(vldrwq_gather_base_wb_s): Likewise.
	(vldrwq_gather_base_wb_f): Likewise.
	(vldrdq_gather_base_wb_s): Likewise.
	(vldrwq_gather_base_nowb_z_u): Define builtin.
	(vldrdq_gather_base_nowb_z_u): Likewise.
	(vldrwq_gather_base_nowb_u): Likewise.
	(vldrdq_gather_base_nowb_u): Likewise.
	(vldrwq_gather_base_nowb_z_s): Likewise.
	(vldrwq_gather_base_nowb_z_f): Likewise.
	(vldrdq_gather_base_nowb_z_s): Likewise.
	(vldrwq_gather_base_nowb_s): Likewise.
	(vldrwq_gather_base_nowb_f): Likewise.
	(vldrdq_gather_base_nowb_s): Likewise.
	* config/arm/mve.md (mve_vldrwq_gather_base_nowb_<supf>v4si): Define RTL
	pattern.
	(mve_vldrwq_gather_base_wb_<supf>v4si): Modify RTL pattern.
	(mve_vldrwq_gather_base_nowb_z_<supf>v4si): Define RTL pattern.
	(mve_vldrwq_gather_base_wb_z_<supf>v4si): Modify RTL pattern.
	(mve_vldrwq_gather_base_wb_fv4sf): Modify RTL pattern.
	(mve_vldrwq_gather_base_nowb_fv4sf): Define RTL pattern.
	(mve_vldrwq_gather_base_wb_z_fv4sf): Modify RTL pattern.
	(mve_vldrwq_gather_base_nowb_z_fv4sf): Define RTL pattern.
	(mve_vldrdq_gather_base_nowb_<supf>v4di): Define RTL pattern.
	(mve_vldrdq_gather_base_wb_<supf>v4di):  Modify RTL pattern.
	(mve_vldrdq_gather_base_nowb_z_<supf>v4di): Define RTL pattern.
	(mve_vldrdq_gather_base_wb_z_<supf>v4di):  Modify RTL pattern.

gcc/testsuite/ChangeLog:

2020-04-02  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>

	PR target/94317
	* gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_s64.c: Modify.
	* gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_u64.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_z_s64.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_z_u64.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_u32.c: Likewise.

2020-04-01  Andrea Corallo  <andrea.corallo@arm.com>

	* testsuite/experimental/net/execution_context/use_service.cc:
	Require pthread and gthreads.

	PR fortran/93522
	* match.c (gfc_match_select_rank): Fix error cleanup.

	PR fortran/93522
	* gfortran.dg/select_rank_4.f90: New.

For operands with an identical set of alternatives there is no point
in marking them commutative.  This patch removes the superfluous
constraint modifiers in vector.md and vx-builtins.md since it might
slow down reload without buying us anything.

There were even two patterns where the constraint modifier was plain
wrong: "sub<VF_HW>3" and "ior_not<VT>3". Fortunately it never had any effect.

gcc/ChangeLog:

2020-04-02  Andreas Krebbel  <krebbel@linux.ibm.com>

	* config/s390/vector.md ("<ti*>add<mode>3", "mul<mode>3")
	("and<mode>3", "notand<mode>3", "ior<mode>3", "ior_not<mode>3")
	("xor<mode>3", "notxor<mode>3", "smin<mode>3", "smax<mode>3")
	("umin<mode>3", "umax<mode>3", "vec_widen_smult_even_<mode>")
	("vec_widen_umult_even_<mode>", "vec_widen_smult_odd_<mode>")
	("vec_widen_umult_odd_<mode>", "add<mode>3", "sub<mode>3")
	("mul<mode>3", "fma<mode>4", "fms<mode>4", "neg_fma<mode>4")
	("neg_fms<mode>4", "*smax<mode>3_vxe", "*smaxv2df3_vx")
	("*smin<mode>3_vxe", "*sminv2df3_vx"): Remove % constraint
	modifier.
	("vec_widen_umult_lo_<mode>", "vec_widen_umult_hi_<mode>")
	("vec_widen_smult_lo_<mode>", "vec_widen_smult_hi_<mode>"):
	Remove constraints from expander.
	* config/s390/vx-builtins.md ("vacc<bhfgq>_<mode>", "vacq")
	("vacccq", "vec_avg<mode>", "vec_avgu<mode>", "vec_vmal<mode>")
	("vec_vmah<mode>", "vec_vmalh<mode>", "vec_vmae<mode>")
	("vec_vmale<mode>", "vec_vmao<mode>", "vec_vmalo<mode>")
	("vec_smulh<mode>", "vec_umulh<mode>", "vec_nor<mode>3")
	("vfmin<mode>", "vfmax<mode>"): Remove % constraint modifier.

ICE occurs when findloc is used with character arguments of different
kinds.  If the character kinds are different reject the code.

Original patch provided by Steven G. Kargl  <kargl@gcc.gnu.org>.

gcc/fortran/ChangeLog:

	PR fortran/93498
	* check.c (gfc_check_findloc):  If the kinds of the arguments
	differ goto label "incompat".

gcc/testsuite/ChangeLog:

	PR fortran/93498
	* gfortran.dg/pr93498_1.f90:  New test.
	* gfortran.dg/pr93498_2.f90:  New test.

Deferred size arrays can not be used in equivalance statements.

gcc/fortran/ChangeLog:

	PR fortran/94030
	* resolve.c (resolve_equivalence): Correct formatting
	around the label "identical_types".  Instead of using
	gfc_resolve_array_spec use is_non_constants_shape_array
	to determine whether the array can be used in a in an
	equivalence statement.

gcc/testsuite/ChangeLog:

	PR fortran/94030
	* gfortran.dg/pr94030_1.f90
	* gfortran.dg/pr94030_2.f90

The scan-file match is likely too strict to always succeed, so instead
have split it up into a set of smaller matches.

gcc/testsuite/ChangeLog:

	PR d/94315
	* gdc.dg/pr93038.d: Split dg-final into multiple tests.
	* gdc.dg/pr93038b.d: Likewise.

The symbol being scanned for only matched on 64-bit targets.

gcc/testsuite/ChangeLog:

	PR d/94321
	* gdc.dg/pr92216.d: Update to work on targets with 16 or 32-bit
	pointers.

	* doc/xml/manual/appendix_free.xml: Move "free books" list from
	fsf.org to gnu.org.
	* doc/html/manual/appendix_free.html: Regenerate.

PR analyzer/94378 reports a false -Wanalyzer-malloc-leak
when returning a struct containing a malloc-ed pointer.

The issue is that the assignment code was not handling
compound copies, only copying top-level values from region to region,
and not copying child values.

This patch introduces a region_model::copy_region function, using
it for assignments and when analyzing function return values.
It recursively copies nested values within structs, unions, and
arrays, fixing the bug.

gcc/analyzer/ChangeLog:
	PR analyzer/94378
	* checker-path.cc: Include "bitmap.h".
	* constraint-manager.cc: Likewise.
	* diagnostic-manager.cc: Likewise.
	* engine.cc: Likewise.
	(exploded_node::detect_leaks): Pass null region_id to pop_frame.
	* program-point.cc: Include "bitmap.h".
	* program-state.cc: Likewise.
	* region-model.cc (id_set<region_id>::id_set): Convert to...
	(region_id_set::region_id_set): ...this.
	(svalue_id_set::svalue_id_set): New ctor.
	(region_model::copy_region): New function.
	(region_model::copy_struct_region): New function.
	(region_model::copy_union_region): New function.
	(region_model::copy_array_region): New function.
	(stack_region::pop_frame): Drop return value.  Add
	"result_dst_rid" param; if it is non-null, use copy_region to copy
	the result to it.  Rather than capture and pass a single "known
	used" return value to be used by purge_unused_values, instead
	gather and pass a set of known used return values.
	(root_region::pop_frame): Drop return value.  Add "result_dst_rid"
	param.
	(region_model::on_assignment): Use copy_region.
	(region_model::on_return): Likewise for the result.
	(region_model::on_longjmp): Pass null for pop_frame's
	result_dst_rid.
	(region_model::update_for_return_superedge): Pass the region for the
	return value of the call, if any, to pop_frame, rather than setting
	the lvalue for the lhs of the result.
	(region_model::pop_frame): Drop return value.  Add
	"result_dst_rid" param.
	(region_model::purge_unused_svalues): Convert third param from an
	svalue_id * to an svalue_id_set *, updating the initial populating
	of the "used" bitmap accordingly.  Don't remap it when done.
	(struct selftest::coord_test): New selftest fixture, extracted from...
	(selftest::test_dump_2): ...here.
	(selftest::test_compound_assignment): New selftest.
	(selftest::test_stack_frames): Pass null to new param of pop_frame.
	(selftest::analyzer_region_model_cc_tests): Call the new selftest.
	* region-model.h (class id_set): Delete template.
	(class region_id_set): Reimplement, using old id_set implementation.
	(class svalue_id_set): Likewise.  Convert from auto_sbitmap to
	auto_bitmap.
	(region::get_active_view): New accessor.
	(stack_region::pop_frame): Drop return value.  Add
	"result_dst_rid" param.
	(root_region::pop_frame): Likewise.
	(region_model::pop_frame): Likewise.
	(region_model::copy_region): New decl.
	(region_model::purge_unused_svalues): Convert third param from an
	svalue_id * to an svalue_id_set *.
	(region_model::copy_struct_region): New decl.
	(region_model::copy_union_region): New decl.
	(region_model::copy_array_region): New decl.

gcc/testsuite/ChangeLog:
	PR analyzer/94378
	* gcc.dg/analyzer/compound-assignment-1.c: New test.
	* gcc.dg/analyzer/compound-assignment-2.c: New test.
	* gcc.dg/analyzer/compound-assignment-3.c: New test.

Segher's patch that added -fsplit-wide-types-early and enabled by default
for rs6000, caused pr87507.c to FAIL because when running lower-subreg
earlier, we don't see any pseudo-to-pseudo copies of our wide type,
which are created by combine, therefore, we skip decomposing our TImode
accesses.  The fix here is just to always run the third pass of lower-subreg
instead of disabling it if we ran the second pass.

2020-04-01  Peter Bergner  <bergner@linux.ibm.com>

	PR rtl-optimization/94123
	* lower-subreg.c (pass_lower_subreg3::gate): Remove test for
	flag_split_wide_types_early.

2020-04-01  Joerg Sonnenberger  <joerg@bec.de>

	* doc/extend.texi (Common Function Attributes): Fix typo.

2020-04-01  Zackery Spytz  <zspytz@gmail.com>

gcc/
	* doc/extend.texi: Fix a typo in the documentation of the
	copy function attribute.

The example code in the PR uses r2 (the TOC register) directly.  In the
RTL generated for that, r2 is copied to some pseudo, and then cprop
propagates that into a "*tocref<mode>" insn, because nothing is
preventing it from doing that.

So, put the same condition in the insn condition for this as we will
later encounter in the constraint anyway, fixing this.

2020-04-01  Segher Boessenkool  <segher@kernel.crashing.org>

	PR target/94420
	* config/rs6000/rs6000.md (*tocref<mode> for P): Add insn condition
	on operands[1].

2020-04-01  Jakub Jelinek  <jakub@redhat.com>

	PR middle-end/94436
	* gcc.dg/pr94436.c: New test.

Failures of pr93365.f90,  pr93600_1.f90 and pr93600_2.f90.
Changes made by PR94246 delete and changed code from expr.c
introduced by PR93600, the deleted code.  This broke the PR93600
test cases.  Restoring the deleted code and leaving the changed
code alone allows the cases for PR93600 and PR94246 to pass.

gcc/fortran/ChangeLog:

	PR fortran/94386
	expr.c (simplify_parameter_variable): Restore code deleted
	in PR94246.

The following testcase ICEs because the objsz pass calls replace_uses_by
on SSA_NAME_OCCURS_IN_ABNORMAL_PHI SSA_NAME.  The following patch instead
of that calls replace_call_with_value, which will turn it into
  xyz_123(ab) = 234;

2020-04-01  Jakub Jelinek  <jakub@redhat.com>

	PR middle-end/94423
	* tree-object-size.c (pass_object_sizes::execute): Don't call
	replace_uses_by for SSA_NAME_OCCURS_IN_ABNORMAL_PHI lhs, instead
	call replace_call_with_value.

	* gcc.dg/ubsan/pr94423.c: New test.

	PR lto/94249
	* plugin-api.h: Fix a typo.

As PR94043 shows, my commit r10-4524 exposed one issue in
vectorizable_live_operation, which inserts one extra BB
before the single exit, leading unexpected operand expansion
and unexpected loop depth assertion.  As Richi suggested,
this patch is to teach vectorizable_live_operation to
generate loop closed phi for vec_lhs, it looks like:
     loop;
     # lhs' = PHI <lhs>
=>
     loop;
     # vec_lhs' = PHI <vec_lhs>
     new_tree = BIT_FIELD_REF <vec_lhs', ...>;
     lhs' = new_tree;

I noticed that there are some SLP cases that have same lhs
and vec_lhs but different offsets, which can make us have
more PHIs for the same vec_lhs there.  But I think it would
be fine since only one of them is actually live, the others
should be eliminated by the following dce.  So the patch
doesn't check whether there is one phi for vec_lhs, just
create one directly instead.

Bootstrapped/regtested on powerpc64le-linux-gnu (LE) P8.

2020-04-01  Kewen Lin  <linkw@gcc.gnu.org>

gcc/ChangeLog

    PR tree-optimization/94043
    * tree-vect-loop.c (vectorizable_live_operation): Generate loop-closed
    phi for vec_lhs and use it for lane extraction.

gcc/testsuite/ChangeLog

    PR tree-optimization/94043
    * gfortran.dg/graphite/vect-pr94043.f90: New test.

We represent 'this' in a default member initializer with a PLACEHOLDER_EXPR.
Normally in constexpr evaluation when we encounter one it refers to
ctx->ctor, but when we're creating a temporary of class type, that replaces
ctx->ctor, so a PLACEHOLDER_EXPR that refers to the type of the member being
initialized needs to be replaced before that happens.

gcc/cp/ChangeLog
2020-03-31  Jason Merrill  <jason@redhat.com>

	PR c++/94205
	* constexpr.c (cxx_eval_constant_expression) [TARGET_EXPR]: Call
	replace_placeholders.
	* typeck2.c (store_init_value): Fix arguments to
	fold_non_dependent_expr.

This patch has no semantic effect; committing it separately makes the change
for 94205 easier to read.

gcc/cp/ChangeLog
2020-03-31  Jason Merrill  <jason@redhat.com>

	* constexpr.c (cxx_eval_constant_expression) [TARGET_EXPR]: Use
	local variables.

This change fixes the symbol merging in get_symbol_decl to also consider
prototypes.  This allows the ability to set user defined attributes on
the prototype of a function, which then get applied to the definition,
if found later in the compilation.

The lowering of UDAs to GCC attributes has been commonized into a single
function called apply_user_attributes.

gcc/d/ChangeLog:

	PR d/90136
	* d-attribs.cc: Include dmd/attrib.h.
	(build_attributes): Redeclare as static.
	(apply_user_attributes): New function.
	* d-tree.h (class UserAttributeDeclaration): Remove.
	(build_attributes): Remove.
	(apply_user_attributes): Declare.
	(finish_aggregate_type): Remove attrs argument.
	* decl.cc (get_symbol_decl): Merge declaration prototypes with
	definitions.  Use apply_user_attributes.
	* modules.cc (layout_moduleinfo_fields): Remove last argument to
	finish_aggregate_type.
	* typeinfo.cc (layout_classinfo_interfaces): Likewise.
	* types.cc (layout_aggregate_members): Likewise.
	(finish_aggregate_type): Remove attrs argument.
	(TypeVisitor::visit (TypeEnum *)): Use apply_user_attributes.
	(TypeVisitor::visit (TypeStruct *)): Remove last argument to
	finish_aggregate_type.  Use apply_user_attributes.
	(TypeVisitor::visit (TypeClass *)): Likewise.

gcc/testsuite/ChangeLog:

	PR d/90136
	* gdc.dg/pr90136a.d: New test.
	* gdc.dg/pr90136b.d: New test.
	* gdc.dg/pr90136c.d: New test.

This attribute is not directly accessible from user code, rather it is
indirectly added from the @forceinline attribute.  Even so, a handler
should be present for it to prevent false positive warnings.

Said warnings are not something that could happen currently, but will
become a problem from fixing PR90136 later.

gcc/d/ChangeLog:

	* d-attribs.cc (d_langhook_common_attribute_table): Add always_inline.
	(handle_always_inline_attribute): New function.

gcc/jit/ChangeLog
2020-03-31  Andrea Corallo  <andrea.corallo@arm.com>
	    David Malcolm  <dmalcolm@redhat.com>

	* docs/topics/compatibility.rst (LIBGCCJIT_ABI_13): New ABI tag
	plus add version paragraph.
	* libgccjit++.h (namespace gccjit::version): Add new namespace.
	* libgccjit.c (gcc_jit_version_major, gcc_jit_version_minor)
	(gcc_jit_version_patchlevel): New functions.
	* libgccjit.h (LIBGCCJIT_HAVE_gcc_jit_version): New macro.
	(gcc_jit_version_major, gcc_jit_version_minor)
	(gcc_jit_version_patchlevel): New functions.
	* libgccjit.map (LIBGCCJIT_ABI_13) New ABI tag.

gcc/testsuite/ChangeLog
2020-03-31  Andrea Corallo  <andrea.corallo@arm.com>

	* jit.dg/test-version.c: New testcase.
	* jit.dg/all-non-failing-tests.h: Add test-version.c.

	* target.c (GOMP_target_enter_exit_data): Handle PSET/MAP_POINTER.
	* testsuite/libgomp.fortran/target-enter-data-1.f90: New.

This patch removes the manual insertion of padding for fields in
constructed struct literals, and instead uses memset() on the
declaration being initialized.

When compiling optimized builds, the intent is usually missed, and
alignment holes end up with non-zero values in them anyway.

gcc/d/ChangeLog:

	PR d/94424
	* d-codegen.cc (build_alignment_field): Remove.
	(build_struct_literal): Don't insert alignment padding.
	* expr.cc (ExprVisitor::visit (AssignExp *)): Call memset before
	assigning struct literals.

gcc/testsuite/ChangeLog:

	PR d/94424
	* gdc.dg/pr94424.d: New test.

In the testcase for PR94398, we're trying to compute:

  alignment_support_scheme
    = vect_supportable_dr_alignment (first_dr_info, false);
  gcc_assert (alignment_support_scheme);

even for VMAT_GATHER_SCATTER, which always accesses individual elements.
Here we should set alignment_support_scheme to dr_unaligned_supported
the gather/scatter case instead of calling vect_supportable_dr_alignment.

2020-03-31  Felix Yang  <felix.yang@huawei.com>

gcc/
	PR tree-optimization/94398
	* tree-vect-stmts.c (vectorizable_store): Instead of calling
	vect_supportable_dr_alignment, set alignment_support_scheme to
	dr_unaligned_supported for gather-scatter accesses.
	(vectorizable_load): Likewise.

gcc/testsuite/
	PR tree-optimization/94398
	* gcc.target/aarch64/pr94398.c: New test.

PR c++/92878
PR c++/92947

* testsuite/20_util/allocator_traits/members/92878_92947.cc: New.
* testsuite/20_util/any/assign/92878_92947.cc: Likewise.
* testsuite/20_util/any/cons/92878_92947.cc: Likewise.
* testsuite/20_util/is_constructible/92878_92947.cc: Likewise.
* testsuite/20_util/optional/assignment/92878_92947.cc: Likewise.
* testsuite/20_util/optional/cons/92878_92947.cc: Likewise.
* testsuite/20_util/pair/cons/92878_92947.cc: Likewise.
* testsuite/20_util/shared_ptr/creation/92878_92947.cc: Likewise.
* testsuite/20_util/specialized_algorithms/construct_at/92878_92947.cc:
Likewise.
* testsuite/20_util/unique_ptr/creation/92878_92947.cc: Likewise.
* testsuite/20_util/uses_allocator/92878_92947.cc: Likewise.
* testsuite/20_util/variant/92878_92947.cc: Likewise.
* testsuite/23_containers/deque/modifiers/emplace/92878_92947.cc:
Likewise.
* testsuite/23_containers/forward_list/modifiers/92878_92947.cc:
Likewise.
* testsuite/23_containers/list/modifiers/emplace/92878_92947.cc:
Likewise.
* testsuite/23_containers/map/modifiers/emplace/92878_92947.cc:
Likewise.
* testsuite/23_containers/multimap/modifiers/emplace/92878_92947.cc:
Likewise.
* testsuite/23_containers/multiset/modifiers/emplace/92878_92947.cc:
Likewise.
* testsuite/23_containers/priority_queue/92878_92947.cc: Likewise.
* testsuite/23_containers/queue/92878_92947.cc: Likewise.
* testsuite/23_containers/set/modifiers/emplace/92878_92947.cc:
Likewise.
* testsuite/23_containers/stack/92878_92947.cc: Likewise.
* testsuite/23_containers/unordered_map/modifiers/92878_92947.cc:
Likewise.
* testsuite/23_containers/unordered_multimap/modifiers/92878_92947.cc:
Likewise.
* testsuite/23_containers/unordered_multiset/modifiers/92878_92947.cc:
Likewise.
* testsuite/23_containers/unordered_set/modifiers/92878_92947.cc:
Likewise.
* testsuite/23_containers/vector/modifiers/emplace/92878_92947.cc:
Likewise.

This adds weak linkage to internal TypeInfo data on top of the existing
DECL_COMDAT, which helps in the unlikely event that two of the same
TypeInfo data ends up in multiple places.

gcc/d/ChangeLog:

	* typeinfo.cc (TypeInfoVisitor::internal_reference): Call
	d_comdat_linkage on generated decl.

Replace all relevant explicit uses of V64 vectors with an iterator (albeit
with only one entry).  This is prerequisite to adding extra vector lengths.

The changes are purely mechanical: comparing the mddump files from before
and after shows only white-space differences and the use of GET_MODE_NUNITS.

2020-03-31  Andrew Stubbs  <ams@codesourcery.com>

	gcc/
	* config/gcn/gcn-valu.md (V_QI, V_HI, V_HF, V_SI, V_SF, V_DI, V_DF):
	New mode iterators.
	(vnsi, VnSI, vndi, VnDI): New mode attributes.
	(mov<mode>): Use <VnDI> in place of V64DI.
	(mov<mode>_exec): Likewise.
	(mov<mode>_sgprbase): Likewise.
	(reload_out<mode>): Likewise.
	(*vec_set<mode>_1): Use GET_MODE_NUNITS instead of constant 64.
	(gather_load<mode>v64si): Rename to ...
	(gather_load<mode><vnsi>): ... this, and use <VnSI> in place of V64SI,
	and <VnDI> in place of V64DI.
	(gather<mode>_insn_1offset<exec>): Use <VnDI> in place of V64DI.
	(gather<mode>_insn_1offset_ds<exec>): Use <VnSI> in place of V64SI.
	(gather<mode>_insn_2offsets<exec>): Use <VnSI> and <VnDI>.
	(scatter_store<mode>v64si): Rename to ...
	(scatter_store<mode><vnsi>): ... this, and use <VnSI> and <VnDI>.
	(scatter<mode>_expr<exec_scatter>): Use <VnSI> and <VnDI>.
	(scatter<mode>_insn_1offset<exec_scatter>): Likewise.
	(scatter<mode>_insn_1offset_ds<exec_scatter>): Likewise.
	(scatter<mode>_insn_2offsets<exec_scatter>): Likewise.
	(ds_bpermute<mode>): Use <VnSI>.
	(addv64si3_vcc<exec_vcc>): Rename to ...
	(add<mode>3_vcc<exec_vcc>): ... this, and use V_SI.
	(addv64si3_vcc_dup<exec_vcc>): Rename to ...
	(add<mode>3_vcc_dup<exec_vcc>): ... this, and use V_SI.
	(addcv64si3<exec_vcc>): Rename to ...
	(addc<mode>3<exec_vcc>): ... this, and use V_SI.
	(subv64si3_vcc<exec_vcc>): Rename to ...
	(sub<mode>3_vcc<exec_vcc>): ... this, and use V_SI.
	(subcv64si3<exec_vcc>): Rename to ...
	(subc<mode>3<exec_vcc>): ... this, and use V_SI.
	(addv64di3): Rename to ...
	(add<mode>3): ... this, and use V_DI.
	(addv64di3_exec): Rename to ...
	(add<mode>3_exec): ... this, and use V_DI.
	(subv64di3): Rename to ...
	(sub<mode>3): ... this, and use V_DI.
	(subv64di3_exec): Rename to ...
	(sub<mode>3_exec): ... this, and use V_DI.
	(addv64di3_zext): Rename to ...
	(add<mode>3_zext): ... this, and use V_DI and <VnSI>.
	(addv64di3_zext_exec): Rename to ...
	(add<mode>3_zext_exec): ... this, and use V_DI and <VnSI>.
	(addv64di3_zext_dup): Rename to ...
	(add<mode>3_zext_dup): ... this, and use V_DI and <VnSI>.
	(addv64di3_zext_dup_exec): Rename to ...
	(add<mode>3_zext_dup_exec): ... this, and use V_DI and <VnSI>.
	(addv64di3_zext_dup2): Rename to ...
	(add<mode>3_zext_dup2): ... this, and use V_DI and <VnSI>.
	(addv64di3_zext_dup2_exec): Rename to ...
	(add<mode>3_zext_dup2_exec): ... this, and use V_DI and <VnSI>.
	(addv64di3_sext_dup2): Rename to ...
	(add<mode>3_sext_dup2): ... this, and use V_DI and <VnSI>.
	(addv64di3_sext_dup2_exec): Rename to ...
	(add<mode>3_sext_dup2_exec): ... this, and use V_DI and <VnSI>.
	(<su>mulv64si3_highpart<exec>): Rename to ...
	(<su>mul<mode>3_highpart<exec>): ... this and use V_SI and <VnDI>.
	(mulv64di3): Rename to ...
	(mul<mode>3): ... this, and use V_DI and <VnSI>.
	(mulv64di3_exec): Rename to ...
	(mul<mode>3_exec): ... this, and use V_DI and <VnSI>.
	(mulv64di3_zext): Rename to ...
	(mul<mode>3_zext): ... this, and use V_DI and <VnSI>.
	(mulv64di3_zext_exec): Rename to ...
	(mul<mode>3_zext_exec): ... this, and use V_DI and <VnSI>.
	(mulv64di3_zext_dup2): Rename to ...
	(mul<mode>3_zext_dup2): ... this, and use V_DI and <VnSI>.
	(mulv64di3_zext_dup2_exec): Rename to ...
	(mul<mode>3_zext_dup2_exec): ... this, and use V_DI and <VnSI>.
	(<expander>v64di3): Rename to ...
	(<expander><mode>3): ... this, and use V_DI and <VnSI>.
	(<expander>v64di3_exec): Rename to ...
	(<expander><mode>3_exec): ... this, and use V_DI and <VnSI>.
	(<expander>v64si3<exec>): Rename to ...
	(<expander><mode>3<exec>): ... this, and use V_SI and <VnSI>.
	(v<expander>v64si3<exec>): Rename to ...
	(v<expander><mode>3<exec>): ... this, and use V_SI and <VnSI>.
	(<expander>v64si3<exec>): Rename to ...
	(<expander><vnsi>3<exec>): ... this, and use V_SI.
	(subv64df3<exec>): Rename to ...
	(sub<mode>3<exec>): ... this, and use V_DF.
	(truncv64di<mode>2): Rename to ...
	(trunc<vndi><mode>2): ... this, and use <VnDI>.
	(truncv64di<mode>2_exec): Rename to ...
	(trunc<vndi><mode>2_exec): ... this, and use <VnDI>.
	(<convop><mode>v64di2): Rename to ...
	(<convop><mode><vndi>2): ... this, and use <VnDI>.
	(<convop><mode>v64di2_exec): Rename to ...
	(<convop><mode><vndi>2_exec): ... this, and use <VnDI>.
	(vec_cmp<u>v64qidi): Rename to ...
	(vec_cmp<u><mode>di): ... this, and use <VnSI>.
	(vec_cmp<u>v64qidi_exec): Rename to ...
	(vec_cmp<u><mode>di_exec): ... this, and use <VnSI>.
	(vcond_mask_<mode>di): Use <VnDI>.
	(maskload<mode>di): Likewise.
	(maskstore<mode>di): Likewise.
	(mask_gather_load<mode>v64si): Rename to ...
	(mask_gather_load<mode><vnsi>): ... this, and use <VnSI> and <VnDI>.
	(mask_scatter_store<mode>v64si): Rename to ...
	(mask_scatter_store<mode><vnsi>): ... this, and use <VnSI> and <VnDI>.
	(*<reduc_op>_dpp_shr_v64di): Rename to ...
	(*<reduc_op>_dpp_shr_<mode>): ... this, and use V_DI and <VnSI>.
	(*plus_carry_in_dpp_shr_v64si): Rename to ...
	(*plus_carry_in_dpp_shr_<mode>): ... this, and use V_SI.
	(*plus_carry_dpp_shr_v64di): Rename to ...
	(*plus_carry_dpp_shr_<mode>): ... this, and use V_DI and <VnSI>.
	(vec_seriesv64si): Rename to ...
	(vec_series<mode>): ... this, and use V_SI.
	(vec_seriesv64di): Rename to ...
	(vec_series<mode>): ... this, and use V_DI.

Use HOST_WIDE_INT_PRINT_DEC macro instead of %ld for format printing.

gcc/
xxxx-xx-xx  Claudiu Zissulescu  <claziss@synopsys.com>

	* config/arc/arc.c (arc_print_operand): Use
	HOST_WIDE_INT_PRINT_DEC macro.

gcc/
xxxx-xx-xx  Claudiu Zissulescu  <claziss@synopsys.com>

	* config/arc/arc.h (ASM_FORMAT_PRIVATE_NAME): Fix it.

For the following MVE ACLE intrinsics, polymorphic variant support is missing on the trunk.

vbicq_n_s16, vbicq_n_s32, vbicq_n_u16 and vbicq_n_u32.

This patch add the polymorphic variant support for above intrinsics.

Please refer to M-profile Vector Extension (MVE) intrinsics [1]  for more details.
[1] https://developer.arm.com/architectures/instruction-sets/simd-isas/helium/mve-intrinsics

2020-03-31  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>

	* config/arm/arm_mve.h (vbicq): Define MVE intrinsic polymorphic
	variant.
	(__arm_vbicq): Likewise.

2020-03-31  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>

	* gcc.target/arm/mve/intrinsics/vbicq_n_s16.c: Modify.
	* gcc.target/arm/mve/intrinsics/vbicq_n_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vbicq_n_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vbicq_n_u32.c: Likewise.

Enable big-endian suffixed dynamic linker per glibc multi-abi support.

And to avoid a future churn and version pairingi hassles, also allow
arc700 although glibc for ARC currently doesn't support it.

gcc/
xxxx-xx-xx  Vineet Gupta <vgupta@synopsys.com>

       * config/arc/linux.h: GLIBC_DYNAMIC_LINKER support BE/arc700

For the following MVE ACLE intrinsics, polymorphic variant supports only +mve option, support for +mve.fp is missing.

vabavq_p_s16, vabavq_p_s32, vabavq_p_s8, vabavq_p_u16, vabavq_p_u32, vabavq_p_u8, vabavq_s16, vabavq_s32, vabavq_s8, vabavq_u16, vabavq_u32, vabavq_u8, vaddlvaq_p_s32, vaddlvaq_p_u32, vaddlvaq_s32, vaddlvaq_u32, vaddlvq_p_s32, vaddlvq_p_u32, vaddlvq_u32, vaddvaq_p_s16, vaddvaq_p_s32, vaddvaq_p_s8, vaddvaq_p_u16, vaddvaq_p_u32, vaddvaq_p_u8, vaddvaq_s16, vaddvaq_s32, vaddvaq_s8, vaddvaq_u16, vaddvaq_u32, vaddvaq_u8, vaddvq_p_s16, vaddvq_p_s32, vaddvq_p_s8, vaddvq_p_u16, vaddvq_p_u32, vaddvq_p_u8, vaddvq_s8, vaddvq_u16, vaddvq_u32, vaddvq_u8, vcmpcsq_m_n_u16, vcmpcsq_m_n_u32, vcmpcsq_m_n_u8, vcmpcsq_m_u16, vcmpcsq_m_u32, vcmpcsq_m_u8, vcmpcsq_n_u16, vcmpcsq_n_u32, vcmpcsq_n_u8, vcmpcsq_u16, vcmpcsq_u32, vcmpcsq_u8, vcmpeqq_n_f16, vcmpeqq_n_f32, vcmpgeq_m_n_s16, vcmpgeq_m_n_s32, vcmpgeq_m_n_s8, vcmpgtq_m_n_f16, vcmpgtq_m_n_f32, vcmpgtq_n_f16, vcmpgtq_n_f32, vcmphiq_m_n_u16, vcmphiq_m_n_u32, vcmphiq_m_n_u8, vcmphiq_m_u16, vcmphiq_m_u32, vcmphiq_m_u8, vcmphiq_n_u16, vcmphiq_n_u32, vcmphiq_n_u8, vcmphiq_u16, vcmphiq_u32, vcmphiq_u8, vcmpleq_m_n_f16, vcmpleq_m_n_f32, vcmpleq_n_f16, vcmpleq_n_f32, vcmpltq_m_n_f16, vcmpltq_m_n_f32, vcmpneq_m_n_f16, vcmpneq_m_n_f32, vcmpneq_n_f16, vcmpneq_n_f32, vmaxavq_p_s16, vmaxavq_p_s32, vmaxavq_p_s8, vmaxavq_s16, vmaxavq_s32, vmaxavq_s8, vmaxq_x_s16, vmaxq_x_s32, vmaxq_x_s8, vmaxq_x_u16, vmaxq_x_u32, vmaxq_x_u8, vmaxvq_p_s16, vmaxvq_p_s32, vmaxvq_p_s8, vmaxvq_p_u16, vmaxvq_p_u32, vmaxvq_p_u8, vmaxvq_s16, vmaxvq_s32, vmaxvq_s8, vmaxvq_u16, vmaxvq_u32, vmaxvq_u8, vminavq_p_s16, vminavq_p_s32, vminavq_p_s8, vminavq_s16, vminavq_s32, vminavq_s8, vminq_x_s16, vminq_x_s32, vminq_x_s8, vminq_x_u16, vminq_x_u32, vminq_x_u8, vminvq_p_s16, vminvq_p_s32, vminvq_p_s8, vminvq_p_u16, vminvq_p_u32, vminvq_p_u8, vminvq_s16, vminvq_s32, vminvq_s8, vminvq_u16, vminvq_u32, vminvq_u8, vmladavaq_p_s16, vmladavaq_p_s32, vmladavaq_p_s8, vmladavaq_p_u16, vmladavaq_p_u32, vmladavaq_p_u8, vmladavaq_s16, vmladavaq_s32, vmladavaq_s8, vmladavaq_u16, vmladavaq_u32, vmladavaq_u8, vmladavaxq_s16, vmladavaxq_s32, vmladavaxq_s8, vmladavq_p_s16, vmladavq_p_s32, vmladavq_p_s8, vmladavq_p_u16, vmladavq_p_u32, vmladavq_p_u8, vmladavq_s16, vmladavq_s32, vmladavq_s8, vmladavq_u16, vmladavq_u32, vmladavq_u8, vmladavxq_p_s16, vmladavxq_p_s32, vmladavxq_p_s8, vmladavxq_s16, vmladavxq_s32, vmladavxq_s8, vmlaldavaq_s16, vmlaldavaq_s32, vmlaldavaq_u16, vmlaldavaq_u32, vmlaldavaxq_s16, vmlaldavaxq_s32, vmlaldavq_p_s16, vmlaldavq_p_s32, vmlaldavq_p_u16, vmlaldavq_p_u32, vmlaldavq_s16, vmlaldavq_s32, vmlaldavq_u16, vmlaldavq_u32, vmlaldavxq_p_s16, vmlaldavxq_p_s32, vmlsdavaq_s16, vmlsdavaq_s32, vmlsdavaq_s8, vmlsdavaxq_s16, vmlsdavaxq_s32, vmlsdavaxq_s8, vmlsdavq_p_s16, vmlsdavq_p_s32, vmlsdavq_p_s8, vmlsdavq_s16, vmlsdavq_s32, vmlsdavq_s8, vmlsdavxq_p_s16, vmlsdavxq_p_s32, vmlsdavxq_p_s8, vmlsdavxq_s16, vmlsdavxq_s32, vmlsdavxq_s8, vmlsldavaq_s16, vmlsldavaq_s32, vmlsldavaxq_s16, vmlsldavaxq_s32, vmlsldavq_p_s16, vmlsldavq_p_s32, vmlsldavq_s16, vmlsldavq_s32, vmlsldavxq_p_s16, vmlsldavxq_p_s32, vmlsldavxq_s16, vmlsldavxq_s32, vmovlbq_x_s16, vmovlbq_x_s8, vmovlbq_x_u16, vmovlbq_x_u8, vmovltq_x_s16, vmovltq_x_s8, vmovltq_x_u16, vmovltq_x_u8, vmulhq_x_s16, vmulhq_x_s32, vmulhq_x_s8, vmulhq_x_u16, vmulhq_x_u32, vmulhq_x_u8, vmullbq_int_x_s16, vmullbq_int_x_s32, vmullbq_int_x_s8, vmullbq_int_x_u16, vmullbq_int_x_u32, vmullbq_int_x_u8, vmullbq_poly_x_p16, vmullbq_poly_x_p8, vmulltq_int_x_s16, vmulltq_int_x_s32, vmulltq_int_x_s8, vmulltq_int_x_u16, vmulltq_int_x_u32, vmulltq_int_x_u8, vmulltq_poly_x_p16, vmulltq_poly_x_p8, vrmlaldavhaq_s32, vrmlaldavhaq_u32, vrmlaldavhaxq_s32, vrmlaldavhq_p_s32, vrmlaldavhq_p_u32, vrmlaldavhq_s32, vrmlaldavhq_u32, vrmlaldavhxq_p_s32, vrmlaldavhxq_s32, vrmlsldavhaq_s32, vrmlsldavhaxq_s32, vrmlsldavhq_p_s32, vrmlsldavhq_s32, vrmlsldavhxq_p_s32, vrmlsldavhxq_s32, vstrbq_p_s16, vstrbq_p_s32, vstrbq_p_s8, vstrbq_p_u16, vstrbq_p_u32, vstrbq_p_u8, vstrbq_s16, vstrbq_s32, vstrbq_s8, vstrbq_scatter_offset_p_s16, vstrbq_scatter_offset_p_s32, vstrbq_scatter_offset_p_s8, vstrbq_scatter_offset_p_u16, vstrbq_scatter_offset_p_u32, vstrbq_scatter_offset_p_u8, vstrbq_scatter_offset_s16, vstrbq_scatter_offset_s32, vstrbq_scatter_offset_s8, vstrbq_scatter_offset_u16, vstrbq_scatter_offset_u32, vstrbq_scatter_offset_u8, vstrbq_u16, vstrbq_u32, vstrbq_u8, vstrdq_scatter_base_p_s64, vstrdq_scatter_base_p_u64, vstrdq_scatter_base_s64, vstrdq_scatter_base_u64, vstrdq_scatter_offset_p_s64, vstrdq_scatter_offset_p_u64, vstrdq_scatter_offset_s64, vstrdq_scatter_offset_u64, vstrdq_scatter_shifted_offset_p_s64,
vstrdq_scatter_shifted_offset_p_u64, vstrdq_scatter_shifted_offset_s64,
vstrdq_scatter_shifted_offset_u64.

This patch adds the support for MVE ACLE intrinsics polymorphic variants with +mve.fp option.

Please refer to M-profile Vector Extension (MVE) intrinsics [1]  for more details.
[1] https://developer.arm.com/architectures/instruction-sets/simd-isas/helium/mve-intrinsics

2020-03-31  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>

	* config/arm/arm_mve.h (vaddlvq): Move the polymorphic variant to the
	common section of both MVE Integer and MVE Floating Point.
	(vaddvq): Likewise.
	(vaddlvq_p): Likewise.
	(vaddvaq): Likewise.
	(vaddvq_p): Likewise.
	(vcmpcsq): Likewise.
	(vmlsdavxq): Likewise.
	(vmlsdavq): Likewise.
	(vmladavxq): Likewise.
	(vmladavq): Likewise.
	(vminvq): Likewise.
	(vminavq): Likewise.
	(vmaxvq): Likewise.
	(vmaxavq): Likewise.
	(vmlaldavq): Likewise.
	(vcmphiq): Likewise.
	(vaddlvaq): Likewise.
	(vrmlaldavhq): Likewise.
	(vrmlaldavhxq): Likewise.
	(vrmlsldavhq): Likewise.
	(vrmlsldavhxq): Likewise.
	(vmlsldavxq): Likewise.
	(vmlsldavq): Likewise.
	(vabavq): Likewise.
	(vrmlaldavhaq): Likewise.
	(vcmpgeq_m_n): Likewise.
	(vmlsdavxq_p): Likewise.
	(vmlsdavq_p): Likewise.
	(vmlsdavaxq): Likewise.
	(vmlsdavaq): Likewise.
	(vaddvaq_p): Likewise.
	(vcmpcsq_m_n): Likewise.
	(vcmpcsq_m): Likewise.
	(vmladavxq_p): Likewise.
	(vmladavq_p): Likewise.
	(vmladavaxq): Likewise.
	(vmladavaq): Likewise.
	(vminvq_p): Likewise.
	(vminavq_p): Likewise.
	(vmaxvq_p): Likewise.
	(vmaxavq_p): Likewise.
	(vcmphiq_m): Likewise.
	(vaddlvaq_p): Likewise.
	(vmlaldavaq): Likewise.
	(vmlaldavaxq): Likewise.
	(vmlaldavq_p): Likewise.
	(vmlaldavxq_p): Likewise.
	(vmlsldavaq): Likewise.
	(vmlsldavaxq): Likewise.
	(vmlsldavq_p): Likewise.
	(vmlsldavxq_p): Likewise.
	(vrmlaldavhaxq): Likewise.
	(vrmlaldavhq_p): Likewise.
	(vrmlaldavhxq_p): Likewise.
	(vrmlsldavhaq): Likewise.
	(vrmlsldavhaxq): Likewise.
	(vrmlsldavhq_p): Likewise.
	(vrmlsldavhxq_p): Likewise.
	(vabavq_p): Likewise.
	(vmladavaq_p): Likewise.
	(vstrbq_scatter_offset): Likewise.
	(vstrbq_p): Likewise.
	(vstrbq_scatter_offset_p): Likewise.
	(vstrdq_scatter_base_p): Likewise.
	(vstrdq_scatter_base): Likewise.
	(vstrdq_scatter_offset_p): Likewise.
	(vstrdq_scatter_offset): Likewise.
	(vstrdq_scatter_shifted_offset_p): Likewise.
	(vstrdq_scatter_shifted_offset): Likewise.
	(vmaxq_x): Likewise.
	(vminq_x): Likewise.
	(vmovlbq_x): Likewise.
	(vmovltq_x): Likewise.
	(vmulhq_x): Likewise.
	(vmullbq_int_x): Likewise.
	(vmullbq_poly_x): Likewise.
	(vmulltq_int_x): Likewise.
	(vmulltq_poly_x): Likewise.
	(vstrbq): Likewise.

gcc/testsuite/ChangeLog:

2020-03-31  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>

	* gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u16.c: Modify.
	* gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpleq_n_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpleq_n_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpneq_n_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpneq_n_f32.c: Likewise.