Amongst the inputs to the analyzer state machines that can lead to state
transitions are conditions on CFG edges, such as a test for a pointer
being non-NULL.

These conditionals can be non-trivial to determine in the face of
optimization.  For example, at -O2:

  if (p == NULL || q == NULL)

is optimized on some targets (e.g. x86_64) to a bitwise-or:

  _1 = p_5(D) == 0B;
  _2 = q_6(D) == 0B;
  _3 = _1 | _2;
  if (_3 != 0)
    goto <bb 4>; [51.12%]
  else
    goto <bb 3>; [48.88%]

but on other targets (e.g. powerpc64le) as control flow:

  if (p_2(D) == 0B)
    goto <bb 5>; [18.09%]
  else
    goto <bb 3>; [81.91%]

  <bb 3> [local count: 879501929]:
  if (q_3(D) == 0B)
    goto <bb 5>; [30.95%]
  else
    goto <bb 4>; [69.05%]

region_model::add_any_constraints_from_ssa_def_stmt attempts to walk
SSA def chains to reconstruct the conditions that hold, so that
e.g. in the above case of bitwise-or, the state machine for
"p" can transition to the "known-null" state along the edge leading
to bb 3.

In gcc.dg/analyzer/pattern-test-2.c I attempted to write test coverage
for this, but the test fails on those targets for which the || is
expressed via control flow.

This patch rewrites the test to make explicit use of bitwise-or, and
adds coverage for bitwise-and for good measure.

gcc/testsuite/ChangeLog:
	PR analyzer/93291
	* gcc.dg/analyzer/pattern-test-2.c: Remove include of stdlib.h.
	(test_2): Rewrite to explicitly perform a bitwise-or of two
	boolean conditions.
	(test_3): New function, to test bitwise-and.

This test started failing after the switch to -fno-common because we can
now force the array to be aligned to 16 bytes, which in turn lets us use
SIMD accesses.  Locally restoring -fcommon seems the most faithful to
the original PR.

2020-01-27  Richard Sandiford  <richard.sandiford@arm.com>

gcc/testsuite/
	PR testsuite/71727
	* gcc.target/aarch64/pr71727.c: Add -fcommon.

	PR gcov-profile/93403
	* tree-profile.c (gimple_init_gcov_profiler): Generate
	both __gcov_indirect_call_profiler_v4 and
	__gcov_indirect_call_profiler_v4_atomic.
	PR gcov-profile/93403
	* libgcov-profiler.c (__gcov_indirect_call_profiler_v4):
	Call __gcov_indirect_call_profiler_body.
	(__gcov_indirect_call_profiler_body): New.
	(__gcov_indirect_call_profiler_v4_atomic): New.
	* libgcov.h (__gcov_indirect_call_profiler_v4_atomic):
	New declaration.

region_model.cc's tree_cmp attempted to verify that the ordering
is symmetric by asserting that
  tree_cmp (x, y) == -tree_cmp (y, x)

This condition is too strong: it's only required for a comparator that
  sign (tree_cmp (x, y)) == -sign (tree_cmp (y, x))
and the incorrect form of the assertion doesn't hold e.g. on s390x where
for certain inputs x, y, tree_cmp (x, y) == 1 and tree_cmp (y, x) == -2,
breaking the build in "make selftest" in stage1.

In any case, these checks are redundant, since qsort_chk performs them.

Additionally, there is a potential lack of transitivity in
worklist::key_t::cmp where hashval_t values are compared by subtraction,
which could fail to be transitive if overflows occur.

This patch eliminates the redundant checks and reimplements the hashval_t
comparisons in terms of < and >, fixing these issues.

gcc/analyzer/ChangeLog:
	* call-string.cc (call_string::cmp_1): Delete, moving body to...
	(call_string::cmp): ...here.
	* call-string.h (call_string::cmp_1): Delete decl.
	* engine.cc (worklist::key_t::cmp_1): Delete, moving body to...
	(worklist::key_t::cmp): ...here.  Implement hash comparisons
	via comparison rather than subtraction to avoid overflow issues.
	* exploded-graph.h (worklist::key_t::cmp_1): Delete decl.
	* region-model.cc (tree_cmp): Eliminate buggy checking for
	symmetry.

Part of the problem in this PR is that we don't provide patterns
to extract a 64-bit vector from one half of a 128-bit vector.
Adding them fixes:

FAIL: gcc.target/aarch64/fmul_intrinsic_1.c scan-assembler-times fmul\\td[0-9]+, d[0-9]+, d[0-9]+ 1
FAIL: gcc.target/aarch64/fmul_intrinsic_1.c scan-assembler-times fmul\\tv[0-9]+.2d, v[0-9]+.2d, v[0-9]+.d\\[[0-9]+\\] 3

The 2s failures need target-independent changes, after which they rely
on these patterns too.

2020-01-27  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
	PR target/92822
	* config/aarch64/aarch64-simd.md (aarch64_get_half<mode>): New
	expander.
	(@aarch64_split_simd_mov<mode>): Use it.
	(aarch64_simd_mov_from_<mode>low): Add a GPR alternative.
	Leave the vec_extract patterns to handle 2-element vectors.
	(aarch64_simd_mov_from_<mode>high): Likewise.
	(vec_extract<VQMOV_NO2E:mode><Vhalf>): New expander.
	(vec_extractv2dfv1df): Likewise.

gcc.target/aarch64/cmpimm_branch_1.c started failing after Bernd's
fix to make combine take the costs of jumps into account
(g:391500af).  This is because the rtx costs
of *compare_condjump<GPI:mode> were higher than the costs
of the instructions it combines.

2020-01-27  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
	* config/aarch64/aarch64.c (aarch64_if_then_else_costs): Match
	jump conditions for *compare_condjump<GPI:mode>.

This patch removes the hack in is_setjmp_call_p of looking for
"setjmp" and "_setjmp", replacing it with some logic adapted from
special_function_p in calls.c, ignoring up to 2 leading underscores from
the fndecl's name when checking for a function by name.

It also requires that such functions are "extern" and at file scope
for them to be matched.

The patch also generalizes the setjmp/longjmp handling in the analyzer
to also work with sigsetjmp/siglongjmp.  Doing so requires generalizing
some hardcoded functions in diagnostics (which were hardcoded to avoid
user-facing messages referring to "_setjmp", which is an implementation
detail) - the patch adds a new function, get_user_facing_name for this,
for use on calls that matched is_named_call_p and
is_specical_named_call_p.

gcc/analyzer/ChangeLog:
	* analyzer.cc  (is_named_call_p): Check that fndecl is "extern"
	and at file scope.  Potentially disregard prefix _ or __ in
	fndecl's name.  Bail if the identifier is NULL.
	(is_setjmp_call_p): Expect a gcall rather than plain gimple.
	Remove special-case check for leading prefix, and also check for
	sigsetjmp.
	(is_longjmp_call_p): Also check for siglongjmp.
	(get_user_facing_name): New function.
	* analyzer.h (is_setjmp_call_p): Expect a gcall rather than plain
	gimple.
	(get_user_facing_name): New decl.
	* checker-path.cc (setjmp_event::get_desc): Use
	get_user_facing_name to avoid hardcoding the function name.
	(rewind_event::rewind_event): Add rewind_info param, using it to
	initialize new m_rewind_info field, and strengthen the assertion.
	(rewind_from_longjmp_event::get_desc): Use get_user_facing_name to
	avoid hardcoding the function name.
	(rewind_to_setjmp_event::get_desc): Likewise.
	* checker-path.h (setjmp_event::setjmp_event): Add setjmp_call
	param and use it to initialize...
	(setjmp_event::m_setjmp_call): New field.
	(rewind_event::rewind_event): Add rewind_info param.
	(rewind_event::m_rewind_info): New protected field.
	(rewind_from_longjmp_event::rewind_from_longjmp_event): Add
	rewind_info param.
	(class rewind_to_setjmp_event): Move rewind_info field to parent
	class.
	* diagnostic-manager.cc (diagnostic_manager::add_events_for_eedge):
	Update setjmp-handling for is_setjmp_call_p requiring a gcall;
	pass the call to the new setjmp_event.
	* engine.cc (exploded_node::on_stmt): Update for is_setjmp_call_p
	requiring a gcall.
	(stale_jmp_buf::emit): Use get_user_facing_name to avoid
	hardcoding the function names.
	(exploded_node::on_longjmp): Pass the longjmp_call when
	constructing rewind_info.
	(rewind_info_t::add_events_to_path): Pass the rewind_info_t to the
	rewind_from_longjmp_event's ctor.
	* exploded-graph.h (rewind_info_t::rewind_info_t): Add
	longjmp_call param.
	(rewind_info_t::get_longjmp_call): New.
	(rewind_info_t::m_longjmp_call): New.
	* region-model.cc (region_model::on_setjmp): Update comment to
	indicate this is also for sigsetjmp.
	* region-model.h (struct setjmp_record): Likewise.
	(class setjmp_svalue): Likewise.

gcc/testsuite/ChangeLog:
	* gcc.dg/analyzer/sigsetjmp-5.c: New test.
	* gcc.dg/analyzer/sigsetjmp-6.c: New test.

2020-01-27  Richard Biener  <rguenther@suse.de>

	PR testsuite/91171
	* gcc.dg/graphite/scop-21.c: un-XFAIL.

This patch fixes various build failures seen with gcc 4.4

gcc prior to 4.6 complains about:

  error: #pragma GCC diagnostic not allowed inside functions

for various uses of PUSH_IGNORE_WFORMAT and POP_IGNORE_WFORMAT.
This patch makes them a no-op with such compilers.

The patch also fixes various errors with template base initializers
and redundant uses of "typename" that older g++ implementations
can't cope with.

gcc/analyzer/ChangeLog:
	PR analyzer/93276
	* analyzer.h (PUSH_IGNORE_WFORMAT, POP_IGNORE_WFORMAT): Guard these
	macros with GCC_VERSION >= 4006, making them no-op otherwise.
	* engine.cc (exploded_edge::exploded_edge): Specify template for
	base class initializer.
	(exploded_graph::add_edge): Specify template when chaining up to
	base class add_edge implementation.
	(viz_callgraph_node::dump_dot): Drop redundant "typename".
	(viz_callgraph_edge::viz_callgraph_edge): Specify template for
	base class initializer.
	* program-state.cc (sm_state_map::clone_with_remapping): Drop
	redundant "typename".
	(sm_state_map::print): Likewise.
	(sm_state_map::hash): Likewise.
	(sm_state_map::operator==): Likewise.
	(sm_state_map::remap_svalue_ids): Likewise.
	(sm_state_map::on_svalue_purge): Likewise.
	(sm_state_map::validate): Likewise.
	* program-state.h (sm_state_map::iterator_t): Likewise.
	* supergraph.h (superedge::superedge): Specify template for base
	class initializer.

gcc/ChangeLog:
	PR analyzer/93276
	* digraph.cc (test_edge::test_edge): Specify template for base
	class initializer.

My changes to is_nested_namespace broke is_ancestor's use where a namespace
alias might be passed in.  This changes is_ancestor to look through the alias.

	PR c++/91826
	* name-lookup.c (is_ancestor): Allow CHILD to be a namespace alias.

gcc/
xxxx-xx-xx  Claudiu Zissulescu  <claziss@synopsys.com>

	* config/arc/arc.c (arc_rtx_costs): Update mul64 cost.

ARC600 when configured with mul64 instructions uses mlo and mhi
registers to store the 64 result of the multiplication. In the ARC600
ISA documentation we have the next register configuration when ARC600
is configured only with mul64 extension:

Register | Name | Use
---------+------+------------------------------------
r57      | mlo  | Multiply low 32 bits, read only
r58      | mmid | Multiply middle 32 bits, read only
r59      | mhi  | Multiply high 32 bits, read only
-----------------------------------------------------

When used for Co-existence configurations we have for mul64 the next
registers used:

Register | Name | Use
---------+------+------------------------------------
r58      | mlo  | Multiply low 32 bits, read only
r59      | mhi  | Multiply high 32 bits, read only
-----------------------------------------------------

Note that mlo/mhi assignment doesn't swap when bigendian CPU
configuration is used.

The compiler will always use r58 for mlo, regardless of the
configuration choosen to ensure mlo/mhi correct splitting. Fixing mlo
to the right register number is done at assembly time. The dwarf info
is also notified via DBX_... macro. Both mlo/mhi registers needs to
saved when ISR happens using a custom sequence.

gcc/
xxxx-xx-xx  Claudiu Zissulescu  <claziss@synopsys.com>

	* config/arc/arc-protos.h (gen_mlo): Remove.
	(gen_mhi): Likewise.
	* config/arc/arc.c (AUX_MULHI): Define.
	(arc_must_save_reister): Special handling for r58/59.
	(arc_compute_frame_size): Consider mlo/mhi registers.
	(arc_save_callee_saves): Emit fp/sp move only when emit_move
	paramter is true.
	(arc_conditional_register_usage): Remove TARGET_BIG_ENDIAN from
	mlo/mhi name selection.
	(arc_restore_callee_saves): Don't early restore blink when ISR.
	(arc_expand_prologue): Add mlo/mhi saving.
	(arc_expand_epilogue): Add mlo/mhi restoring.
	(gen_mlo): Remove.
	(gen_mhi): Remove.
	* config/arc/arc.h (DBX_REGISTER_NUMBER): Correct register
	numbering when MUL64 option is used.
	(DWARF2_FRAME_REG_OUT): Define.
	* config/arc/arc.md (arc600_stall): New pattern.
	(VUNSPEC_ARC_ARC600_STALL): Define.
	(mulsi64): Use correct mlo/mhi registers.
	(mulsi_600): Clean it up.
	* config/arc/predicates.md (mlo_operand): Remove any dependency on
	TARGET_BIG_ENDIAN.
	(mhi_operand): Likewise.

testsuite/
xxxx-xx-xx  Claudiu Zissulescu  <claziss@synopsys.com>

	* gcc.target/arc/interrupt-6.c: Update test.

Like `packed` type attribute, the ARC's `uncached` type attribute
needs to be propagated to each member of the struct where it is used,
triggering the .di flag for any access of the struct members. However,
any complex CFG manipulation may drop memory pointer type attributes,
leading to the impossibility to discriminate the direct accesses from
normal ones. To solve this issue, we will treat the direct memory
accessed specially via unspecs.

gcc/
xxxx-xx-xx  Claudiu Zissulescu  <claziss@synopsys.com>
	Petro Karashchenko  <petro.karashchenko@ring.com>

	* config/arc/arc.c (arc_is_uncached_mem_p): Check struct
	attributes if needed.
	(prepare_move_operands): Generate special
	unspec instruction for direct access.
	(arc_isuncached_mem_p): Propagate uncached attribute to each
	structure member.
	* config/arc/arc.md (VUNSPEC_ARC_LDDI): Define.
	(VUNSPEC_ARC_STDI): Likewise.
	(ALLI): New mode iterator.
	(mALLI): New mode attribute.
	(lddi): New instruction pattern.
	(stdi): Likewise.
	(stdidi_split): Split instruction for architectures which are not
	supporting ll64 option.
	(lddidi_split): Likewise.

testsuite/
xxxx-xx-xx  Claudiu Zissulescu  <claziss@synopsys.com>
	Petro Karashchenko  <petro.karashchenko@ring.com>

	* gcc.target/arc/uncached-1.c: Update test.
	* gcc.target/arc/uncached-2.c: Likewise.
	* gcc.target/arc/uncached-3.c: New test.
	* gcc.target/arc/uncached-4.c: Likewise.
	* gcc.target/arc/uncached-5.c: Likewise.
	* gcc.target/arc/uncached-6.c: Likewise.
	* gcc.target/arc/uncached-7.c: Likewise.
	* gcc.target/arc/uncached-8.c: Likewise.
	* gcc.target/arc/arc.exp (ll64): New predicate.

ARC processors can work with a reduced register set (i.e. registers
r4-r9 and r16-r25 are not available). This option can be enabled
passing -mrf16 option to the compiler, or by using -mcpu=em_mini CPU
configuration. Using RF16 config requires all the hand-made assembly
files used in libgcc to have the corresponding RF16 object attribute
set.

This patch qualifies the relevant hand-made assembly files to
RF16 config, and also adds generic c-functions for the one which are
not.

libgcc/
xxxx-xx-xx  Claudiu Zissulescu  <claziss@synopsys.com>

	* config/arc/crti.S: Add RF16 object attribute.
	* config/arc/crtn.S: Likewise.
	* config/arc/crttls.S: Likewise.
	* config/arc/lib1funcs.S: Likewise.
	* config/arc/fp-hack.h (ARC_OPTFPE): Define.
	* config/arc/lib2funcs.c: New file.
	* config/arc/t-arc: Add lib2funcs to LIB2ADD.

The deduction guide from an iterator and sentinel used the wrong alias
template and so didn't work.

	PR libstdc++/93426
	* include/std/span (span): Fix deduction guide.
	* testsuite/23_containers/span/deduction.cc: New test.

lra_assign has an assert to make sure that no pseudo is allocated
to a conflicting hard register.  It used to be restricted to
!flag_ipa_ra, but in g:a1e6ee38 I'd enabled it for
flag_ipa_ra too.  It then tripped while building libstdc++
for mips-mti-linux.

The failure was due to code at the end of process_bb_lives.  For an
abnormal/EH edge, we need to make sure that all pseudos that are live
on entry to the destination conflict with all hard registers that are
clobbered by an abnormal call return.  The usual way to do this would
be to simulate a clobber of the hard registers, by making them live and
them making them dead again.  Making the registers live creates the
conflict; making them dead again restores the correct live set for
whatever follows.

However, process_bb_lives skips the second step (making the registers
dead again) at the start of a BB, presumably on the basis that there's
no further code that needs a correct live set.  The problem for the PR
is that that wasn't quite true in practice.  There was code further
down process_bb_lives that updated the live-in set of the BB for some
registers, and this live set was "contaminated" by registers that
weren't live but that created conflicts.  This information then got
propagated to other blocks, so that registers that were made live
purely to create a conflict at the start of the EH receiver then became
needlessly live throughout preceding blocks.  This in turn created a
fake conflict with pseudos in those blocks, invalidating the choices
made by IRA.

The easiest fix seems to be to update the live-in set *before* adding
the fake live registers.  An alternative would be to simulate the full
clobber, but that seems a bit wasteful.

2020-01-27  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
	PR rtl-optimization/92989
	* lra-lives.c (process_bb_lives): Update the live-in set before
	processing additional clobbers.

g:3bd29185 mishandled the case in which only the
tail end of a multireg hard register is invalidated by the call.
Walking all the entries should be both safer and more precise.

Avoiding cselib_invalidate_regno also means that we no longer
walk the same list multiple times (which is something we did
before g:3bd29185 too).

2020-01-27  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
	PR rtl-optimization/93170
	* cselib.c (cselib_invalidate_regno_val): New function, split out
	from...
	(cselib_invalidate_regno): ...here.
	(cselib_invalidated_by_call_p): New function.
	(cselib_process_insn): Iterate over all the hard-register entries in
	REG_VALUES and invalidate any that cross call-clobbered registers.

gcc/testsuite/
	* gcc.dg/torture/pr93170.c: New test.

PR91323 was fixed for x86 and sparc in target code, but aarch64
instead relies on the target-independent comparison splitters.
Since LTGT is an unordered-signalling operation, we should split
it into unordered-signalling operations for any input that could
be NaN, not just inputs that could be signalling NaNs.

2020-01-27  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
	* dojump.c (split_comparison): Use HONOR_NANS rather than
	HONOR_SNANS when splitting LTGT.

	PR driver/91220
	* opts.c (print_filtered_help): Exclude language-specific
	options from --help=common unless enabled in all FEs.

	* opts.c (print_help): Exclude params from
	all except --help=param.

	PR target/93274
	* config/i386/i386-features.c (make_resolver_func):
	Align the code with ppc64 target implementation.
	Do not generate a unique name for resolver function.
	PR target/93274
	* gcc.target/i386/pr81213.c: Adjust to not expect
	a globally unique name.

The following delays adjusting the SLP graph for converted reduction
chains to a point where the SLP build no longer can fail since we
otherwise fail to undo marking the conversion as a group.

2020-01-27  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/93397
	* tree-vect-slp.c (vect_analyze_slp_instance): Delay
	converted reduction chain SLP graph adjustment.

	* gcc.dg/torture/pr93397.c: New testcase.

        PR fortran/85781
        * trans-expr.c (gfc_conv_substring): Handle non-ARRAY_TYPE strings
        of Bind(C) procedures.

        PR fortran/85781
        * gfortran.dg/bind_c_char_2.f90: New.
        * gfortran.dg/bind_c_char_3.f90: New.
        * gfortran.dg/bind_c_char_4.f90: New.
        * gfortran.dg/bind_c_char_5.f90: New.

It occurred to me that the NotNoexcept class is irrelevant to the issue I
was fixing, so let's remove it.

The immediate issue here was that the second warning didn't depend on the
first one, so if the first location was in a system header, we'd
mysteriously give the second by itself.

It's also the case that the thing we care about being in a system header is
the function that we want to suggest adding 'noexcept' to, not the
noexcept-expression; it's useful to suggest adding noexcept to a user
function to satisfy a noexcept-expression in a system header.

	PR c++/90992
	* except.c (maybe_noexcept_warning): Check DECL_IN_SYSTEM_HEADER and
	temporarily enable -Wsystem-headers.  Change second warning to
	conditional inform.

Here we crash when using -fsanitize=address -fdump-tree-sanopt because
the dumping code uses IDENTIFIER_POINTER on a null DECL_NAME.  Instead,
we can print "<anonymous>" in such a case.  Or we could avoid printing
that diagnostic altogether.

2020-01-26  Marek Polacek  <polacek@redhat.com>

	PR tree-optimization/93436
	* sanopt.c (sanitize_rewrite_addressable_params): Avoid crash on
	null DECL_NAME.

This amends the cases where inline comments in function calls were
followed by a space.  It also fixes some uses of C++ style and wrongly
wrapped comment end markers.

gcc/cp/ChangeLog:

2020-01-26  Iain Sandoe  <iain@sandoe.co.uk>

* coroutines.cc: Amend whitespace after inline comments
throughout.  Ensure use of C-style comment markers.

The new gcc.target/i386/pr91298-?.c testcases FAIL on Solaris/x86 with the
native assembler:

FAIL: gcc.target/i386/pr91298-1.c (test for excess errors)

Excess errors:
Assembler: pr91298-1.c
        "/var/tmp//ccE6r3xb.s", line 5 : Syntax error
        Near line: "    .globl  $quux"
        "/var/tmp//ccE6r3xb.s", line 6 : Syntax error
        Near line: "    .type   $quux, @function"
        "/var/tmp//ccE6r3xb.s", line 7 : Syntax error
        Near line: "$quux:"
        "/var/tmp//ccE6r3xb.s", line 15 : Syntax error
        Near line: "    .size   $quux, .-$quux"
        "/var/tmp//ccE6r3xb.s", line 24 : Syntax error
        Near line: "    movl    $($a), %eax"
        "/var/tmp//ccE6r3xb.s", line 38 : Syntax error
        Near line: "    leal    ($a)(,%eax,4), %eax"
        "/var/tmp//ccE6r3xb.s", line 51 : Syntax error
        Near line: "    movl    ($a), %eax"
        "/var/tmp//ccE6r3xb.s", line 63 : Syntax error
        Near line: "    movl    ($a)+16, %eax"
        "/var/tmp//ccE6r3xb.s", line 97 : Syntax error
        Near line: "    movl    $($quux), %eax"
        "/var/tmp//ccE6r3xb.s", line 101 : Syntax error
        Near line: "    .globl  $a"
        "/var/tmp//ccE6r3xb.s", line 104 : Syntax error
        Near line: "    .type   $a, @object"
        "/var/tmp//ccE6r3xb.s", line 105 : Syntax error
        Near line: "    .size   $a, 72"
        "/var/tmp//ccE6r3xb.s", line 106 : Syntax error
        Near line: "$a:"
        "/var/tmp//ccE6r3xb.s", line 228 : Syntax error
        Near line: "    .long   ($a)"

FAIL: gcc.target/i386/pr91298-2.c (test for excess errors)

It only allows letters, digits, '_' and '.' in identifiers:
https://docs.oracle.com/cd/E37838_01/html/E61064/eqbsx.html#XALRMeoqjw

For lack of an effective-target keyword matching -fdollars-in-identifiers,
this patch fixes this by xfailing them on *-*-solaris2.* && !gas.

Tested on i386-pc-solaris2.11 with as and gas and x86_64-pc-linux-gnu.

	* gcc.target/i386/pr91298-1.c: xfail on Solaris/x86 with native
	assembler.
	* gcc.target/i386/pr91298-2.c: Likewise.

Here, we end up calling gen_type_die_with_usage for a type that's in the
middle of finish_struct_1, after we set TYPE_NEEDS_CONSTRUCTING on it but
before we copy all the flags to the variants--and, significantly, before we
set its TYPE_SIZE.  It seems reasonable to only look at
TYPE_NEEDS_CONSTRUCTING on complete types, since we aren't going to try to
create an object of an incomplete type any other way.

	PR c++/92601
	* tree.c (verify_type_variant): Only verify TYPE_NEEDS_CONSTRUCTING
	of complete types.

	* config/rx/rx.md (setmemsi): Added rx_allow_string_insns constraint
	(rx_setmem): Likewise.

In the *{add,sub}v<dwi>4_doubleword patterns, we don't really want to see a
VOIDmode last operand, because it then means invalid RTL
(sign_extend:{TI,POI} (const_int ...)) or so, and therefore something we
don't really handle in the splitter either.  We have
*{add,sub}v<dwi>4_doubleword_1 pattern for those and that is what combine
will match, the problem in this testcase is just that it was only RA that
propagated the constant into the instruction.

In the similar *{add,sub}v<mode>4 patterns, we make sure not to accept
VOIDmode operand and similarly to these have _1 suffixed variant that allows
constants.

2020-01-26  Jakub Jelinek  <jakub@redhat.com>

	PR target/93412
	* config/i386/i386.md (*addv<dwi>4_doubleword, *subv<dwi>4_doubleword):
	Use nonimmediate_operand instead of x86_64_hilo_general_operand and
	drop <di> from constraint of last operand.

	* gcc.dg/pr93412.c: New test.

Apparently my recent patch which moved the *avx_vperm_broadcast* and
*vpermil* patterns before vpermpd broke the following testcase, the
define_insn_and_split matched always but the splitter condition only split
it if not -mavx2 for V4DFmode, basically relying on the vpermpd pattern to
come first.

The following patch fixes it by moving that part of SPLIT-CONDITION into
CONDITION, so that when it is not met, we just don't match the pattern
and thus match the later vpermpd pattern in that case.
Except, for { 0, 0, 0, 0 } permutation, there is actually no reason to do
that, vbroadcastsd from memory seems to be slightly cheaper than vpermpd $0.

2020-01-26  Jakub Jelinek  <jakub@redhat.com>

	PR target/93430
	* config/i386/sse.md (*avx_vperm_broadcast_<mode>): Disallow for
	TARGET_AVX2 and V4DFmode not in the split condition, but in the
	pattern condition, though allow { 0, 0, 0, 0 } broadcast always.

	* gcc.dg/pr93430.c: New test.
	* gcc.target/i386/avx2-pr93430.c: New test.

warn_for_memset calls fold_for_warn, which calls fold_non_dependent_expr, so
also calling instantiate_non_dependent_expr here is undesirable.

	PR c++/90997
	* semantics.c (finish_call_expr): Don't call
	instantiate_non_dependent_expr before warn_for_memset.

testsuite: Fix up pr93166.C test, so that it doesn't FAIL with -std=c++98 and tests what it is supposed to test.

2020-01-26  Jakub Jelinek  <jakub@redhat.com>

	PR ipa/93166
	* g++.dg/pr93166.C: Move to ...
	* g++.dg/pr93166_0.C: ... here.  Turn it into a proper lto test.

2020-01-26  Jakub Jelinek  <jakub@redhat.com>

	PR tree-optimization/92788
	* g++.dg/pr92788.C: Move to ...
	* g++.target/i386/pr92788.C: ... here.  Remove target from dg-do line.
	Change type of operator new's first parameter to __SIZE_TYPE__.

I neglected to add a proper diagnostic for the reference dynamic_cast
case when the operand of a dynamic_cast doesn't refer to a public base
of Derived, resulting in suboptimal error message

   error: call to non-'constexpr' function 'void* __cxa_bad_cast()'

2020-01-25  Marek Polacek  <polacek@redhat.com>

	PR c++/93414 - poor diagnostic for dynamic_cast in constexpr context.
	* constexpr.c (cxx_eval_dynamic_cast_fn): Add a reference
	dynamic_cast diagnostic.

	* g++.dg/cpp2a/constexpr-dynamic18.C: New test.

	2020-01-25  John David Anglin  <danglin@gcc.gnu.org>

	* inclhack.def (hpux_c99_inttypes4): New, add missing SCNuMAX defines.
	* fixincl.x: Regenerate.
	* tests/base/inttypes.h: Update for above fix.