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  1. 17 Oct, 2019 1 commit
  3. 16 Oct, 2019 22 commits
    • decl.c (cxx_maybe_build_cleanup): When clearing location of cleanup... · 606358fa 
      	* decl.c (cxx_maybe_build_cleanup): When clearing location of cleanup,
	if cleanup is a nop, clear location of its operand too.

From-SVN: r277084
      Jakub Jelinek committed
    • tree-ssa-strlen.c (maybe_invalidate): Use HOST_WIDE_INT_PRINT_UNSIGNED instead of "%zu". · e5b04038 
      	* tree-ssa-strlen.c (maybe_invalidate): Use
	HOST_WIDE_INT_PRINT_UNSIGNED instead of "%zu".

From-SVN: r277083
      Jakub Jelinek committed
    • RISC-V: Include more registers in SIBCALL_REGS. · 3599dfba 
      This finishes the part 1 of 2 patch submitted by Andrew Burgess on Aug 19.
This adds the argument registers but not t0 (aka x5) to SIBCALL_REGS.  It
also adds the missing riscv_regno_to_class change.

Tested with cross riscv32-elf and riscv64-linux toolchain build and check.
There were no regressions.  I see about a 0.01% code size reduction for the
C and libstdc++ libraries.

	gcc/
	* config/riscv/riscv.h (REG_CLASS_CONTENTS): Add argument passing
	regs to SIBCALL_REGS.
	* config/riscv/riscv.c (riscv_regno_to_class): Change argument
	passing regs to SIBCALL_REGS.

Co-Authored-By: Jim Wilson <jimw@sifive.com>

From-SVN: r277082
      Andrew Burgess committed
    • PR tree-optimization/83821 - local aggregate initialization defeats strlen optimization · 2fcb55d1 
      gcc/ChangeLog:

	PR tree-optimization/83821
	* tree-ssa-strlen.c (maybe_invalidate): Add argument.  Consider
	the length of a string when available.
	(handle_builtin_memset) Add argument.
	(handle_store, strlen_check_and_optimize_call): Same.
	(check_and_optimize_stmt): Same.  Pass it to callees.

gcc/testsuite/ChangeLog:

	PR tree-optimization/83821
	* c-c++-common/Warray-bounds-4.c: Remove XFAIL.
	* gcc.dg/strlenopt-82.c: New test.
	* gcc.dg/strlenopt-83.c: Same.
	* gcc.dg/strlenopt-84.c: Same.
	* gcc.dg/strlenopt-85.c: Same.
	* gcc.dg/strlenopt-86.c: Same.
	* gcc.dg/tree-ssa/calloc-4.c: Same.
	* gcc.dg/tree-ssa/calloc-5.c: Same.

From-SVN: r277080
      Martin Sebor committed
    • PR tree-optimization/91996 - fold non-constant strlen relational expressions · 27c14dbc 
      gcc/testsuite/ChangeLog:

	PR tree-optimization/91996
	* gcc.dg/strlenopt-80.c: New test.
	* gcc.dg/strlenopt-81.c: New test.

gcc/ChangeLog:

	PR tree-optimization/91996
	* tree-ssa-strlen.c (maybe_warn_pointless_strcmp): Improve location
	information.
	(compare_nonzero_chars): Add an overload.
	(count_nonzero_bytes): Add an argument.  Call overload above.
	Handle non-constant lengths in some range.
	(handle_store): Add an argument.
	(check_and_optimize_stmt): Pass an argument to handle_store.

From-SVN: r277076
      Martin Sebor committed
    • [arm] fix bootstrap failure due to uninitialized warning · b7bfd3c5 
      The Arm port is failing bootstrap because GCC is now warning about an
unitialized array.

The code is complex enough that I certainly can't be sure the compiler
is wrong, so perhaps the best fix here is just to memset the entire
array before use.

	* config/arm/arm.c (neon_valid_immediate): Clear bytes before use.

From-SVN: r277073
      Richard Earnshaw committed
    • mips.c (mips_expand_builtin_insn): Force the operands which correspond to the… · c32ffa8d 
      mips.c (mips_expand_builtin_insn): Force the operands which correspond to the same input-output register to have...

	* config/mips/mips.c (mips_expand_builtin_insn): Force the
	operands which correspond to the same input-output register to
	have the same pseudo assigned to them.

	* gcc.target/mips/msa-dpadd-dpsub.c: New test.

From-SVN: r277071
      Mihailo Stojanovic committed
    • find_partition_fixes: remove unused bbs_in_cold_partition variable · 26e7516a 
      gcc/ChangeLog:

2019-10-16  Ilya Leoshkevich  <iii@linux.ibm.com>

	* cfgrtl.c (find_partition_fixes): Remove bbs_in_cold_partition.

From-SVN: r277070
      Ilya Leoshkevich committed
    • [AArch64] Fix symbol offset limit · 7d3b27ff 
      In aarch64_classify_symbol symbols are allowed large offsets on relocations. 
This means the offset can use all of the +/-4GB offset, leaving no offset
available for the symbol itself.  This results in relocation overflow and
link-time errors for simple expressions like &global_array + 0xffffff00.

To avoid this, unless the offset_within_block_p is true, limit the offset
to +/-1MB so that the symbol needs to be within a 3.9GB offset from its
references.  For the tiny code model use a 64KB offset, allowing most of
the 1MB range for code/data between the symbol and its references.

    gcc/
	* config/aarch64/aarch64.c (aarch64_classify_symbol):
	Apply reasonable limit to symbol offsets.

    testsuite/
	* gcc.target/aarch64/symbol-range.c: Improve testcase.
	* gcc.target/aarch64/symbol-range-tiny.c: Likewise.

From-SVN: r277068
      Wilco Dijkstra committed
    • tree-vect-loop.c (vect_valid_reduction_input_p): Remove. · aab8c2fd 
      2019-10-16  Richard Biener  <rguenther@suse.de>

	* tree-vect-loop.c (vect_valid_reduction_input_p): Remove.
	(vect_is_simple_reduction): Delay checking to
	vectorizable_reduction and relax the checking.
	(vectorizable_reduction): Check we have a simple use.  Check
	for bogus condition reductions.
	* tree-vect-stmts.c (vect_transform_stmt): Make sure we
	are looking at the last stmt in a pattern sequence when
	filling in backedge PHI values.

	* gcc.dg/vect/vect-cond-reduc-3.c: New testcase.
	* gcc.dg/vect/vect-cond-reduc-4.c: Likewise.

From-SVN: r277067
      Richard Biener committed
    • In PR70010, a function is marked with target(no-vsx) to disable VSX code generation. · 1624d351 
      In PR70010, a function is marked with target(no-vsx) to disable VSX code
generation.  To avoid VSX code generation, this function should not be
inlined into VSX function.  To fix the bug, in the current logic when
checking whether the caller's ISA flags supports the callee's ISA flags, we
just need to add a test that enforces that the caller's ISA flags match
exactly the callee's flags, for those flags that were explicitly set in the
callee.  If caller without target attribute then using options from command
line.

gcc/
2019-10-16  Peter Bergner <bergner@linux.ibm.com>
	    Jiufu Guo  <guojiufu@linux.ibm.com>

	PR target/70010
	* config/rs6000/rs6000.c (rs6000_can_inline_p): Prohibit inlining if
	the callee explicitly disables some isa_flags the caller is using.

gcc.testsuite/
2019-10-16  Peter Bergner <bergner@linux.ibm.com>
	    Jiufu Guo  <guojiufu@linux.ibm.com>

	PR target/70010
	* gcc.target/powerpc/pr70010.c: New test.
	* gcc.target/powerpc/pr70010-1.c: New test.
	* gcc.target/powerpc/pr70010-2.c: New test.
	* gcc.target/powerpc/pr70010-3.c: New test.
	* gcc.target/powerpc/pr70010-4.c: New test.

Co-Authored-By: Jiufu Guo <guojiufu@linux.ibm.com>

From-SVN: r277065
      Peter Bergner committed
    • Assert for POINTER_TYPE_P in expr_callee_abi · 50425706 
      2019-10-16  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
	* function-abi.cc (expr_callee_abi): Assert for POINTER_TYPE_P.

From-SVN: r277063
      Richard Sandiford committed
    • [AArch64] Add partial SVE vector modes · 550a3380 
      This patch adds extra vector modes that represent a half, quarter or
eighth of what an SVE vector can hold.  This is useful for describing
the memory vector involved in an extending load or truncating store.
It might also be useful in future for representing "unpacked" SVE
registers, i.e. registers that contain values in the low bits of a
wider containing element.

The new modes could have the same width as an Advanced SIMD mode for
certain -msve-vector-bits=N options, so we need to ensure that they
come later in the mode list and that Advanced SIMD modes always "win".

2019-10-16  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
	* genmodes.c (mode_data::order): New field.
	(blank_mode): Update accordingly.
	(VECTOR_MODES_WITH_PREFIX): Add an order parameter.
	(make_vector_modes): Likewise.
	(VECTOR_MODES): Update use accordingly.
	(cmp_modes): Sort by the new order field ahead of sorting by size.
	* config/aarch64/aarch64-modes.def (VNx2QI, VN2xHI, VNx2SI)
	(VNx4QI, VNx4HI, VNx8QI): New partial vector modes.
	* config/aarch64/aarch64.c (VEC_PARTIAL): New flag value.
	(aarch64_classify_vector_mode): Handle the new partial modes.
	(aarch64_vl_bytes): New function.
	(aarch64_hard_regno_nregs): Use it instead of BYTES_PER_SVE_VECTOR
	when counting the number of registers in an SVE mode.
	(aarch64_class_max_nregs): Likewise.
	(aarch64_hard_regno_mode_ok): Don't allow partial vectors
	in registers yet.
	(aarch64_classify_address): Treat partial vectors analogously
	to full vectors.
	(aarch64_print_address_internal): Consolidate the printing of
	MUL VL addresses, using aarch64_vl_bytes as the number of
	bytes represented by "VL".
	(aarch64_vector_mode_supported_p): Reject partial vector modes.

From-SVN: r277062
      Richard Sandiford committed
    • [AArch64] Improve poly_int handling in aarch64_layout_frame · 9b17a646 
      I'd used known_lt when converting these conditions to poly_int,
but on reflection that was a bad choice.  The code isn't just
doing a range check; it specifically needs constants that will
fit in a certain encoding.

2019-10-16  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
	* config/aarch64/aarch64.c (aarch64_layout_frame): Use is_constant
	rather than known_lt when choosing frame layouts.

From-SVN: r277061
      Richard Sandiford committed
    • [AArch64] Add an assert to aarch64_layout_frame · 8e66b377 
      This patch adds an assert that all the individual *_adjust allocations
add up to the full frame size.  With that safety net, it seemed slightly
clearer to use crtl->outgoing_args_size as the final adjustment where
appropriate, to match what's used in the comments.

This is a bit overkill on its own, but I need to add more cases for SVE.

2019-10-16  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
	* config/aarch64/aarch64.c (aarch64_layout_frame): Assert
	that all the adjustments add up to the full frame size.
	Use crtl->outgoing_args_size directly as the final adjustment
	where appropriate.

From-SVN: r277060
      Richard Sandiford committed
    • [AArch64] Use frame reference in aarch64_layout_frame · ab43763e 
      Using the full path "cfun->machine->frame" in aarch64_layout_frame
led to awkward formatting in some follow-on patches, so it seemed
worth using a local reference instead.

2019-10-16  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
	* config/aarch64/aarch64.c (aarch64_layout_frame): Use a local
	"frame" reference instead of always referring directly to
	"cfun->machine->frame".

From-SVN: r277059
      Richard Sandiford committed
    • Only use GCC-specific __is_same_as built-in conditionally · 44af818f 
      Clang doesn't support __is_same_as but provides __is_same instead.
Restore the original implementation (pre r276891) when neither of those
built-ins is available.

	* include/bits/c++config (_GLIBCXX_BUILTIN_IS_SAME_AS): Define to
	one of __is_same_as or __is_same when available.
	* include/std/concepts (__detail::__same_as): Use std::is_same_v.
	* include/std/type_traits (is_same) [_GLIBCXX_BUILTIN_IS_SAME_AS]:
	Use new macro instead of __is_same_as.
	(is_same) [!_GLIBCXX_BUILTIN_IS_SAME_AS]: Restore partial
	specialization.
	(is_same_v) [_GLIBCXX_BUILTIN_IS_SAME_AS]: Use new macro.
	(is_same_v) [!_GLIBCXX_BUILTIN_IS_SAME_AS]: Use std::is_same.

From-SVN: r277058
      Jonathan Wakely committed
    • re PR tree-optimization/92119 (ICE: SIGSEGV in contains_struct_check… · bf78ed91 
      re PR tree-optimization/92119 (ICE: SIGSEGV in contains_struct_check (tree.h:3380) with -Os -fno-tree-dce -fno-tree-dse -ftree-slp-vectorize)

2019-10-16  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/92119
	* tree-vect-patterns.c (vect_recog_rotate_pattern): Guard
	against missing bswap lhs.

From-SVN: r277057
      Richard Biener committed
    • Deal with incoming POLY_INT_CST ranges (PR92033) · 96eb7d7a 
      This patch makes value_range_base::set convert POLY_INT_CST bounds
into the worst-case INTEGER_CST bounds.  The main case in which this
gives useful ranges is a lower bound of A + B * X becoming A when B >= 0.
E.g.:

  [32 + 16X, 100] -> [32, 100]
  [32 + 16X, 32 + 16X] -> [32, MAX]

But the same thing can be useful for the upper bound with negative
X coefficients.

2019-10-16  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
	PR middle-end/92033
	* poly-int.h (constant_lower_bound_with_limit): New function.
	(constant_upper_bound_with_limit): Likewise.
	* doc/poly-int.texi: Document them.
	* tree-vrp.c (value_range_base::set): Convert POLY_INT_CST bounds
	into the worst-case INTEGER_CST bounds.

From-SVN: r277056
      Richard Sandiford committed
    • Generalized IPA predicate on parameter reference · 4307a485 
      2019-10-16  Feng Xue  <fxue@os.amperecomputing.com>

        PR ipa/91088
        * doc/invoke.texi (ipa-max-param-expr-ops): Document new option.
        * params.def (PARAM_IPA_MAX_PARAM_EXPR_OPS): New.
        * ipa-predicat.h (struct expr_eval_op): New struct.
        (expr_eval_ops): New typedef.
        (struct condition): Add type and param_ops fields, remove size field.
        (add_condition): Replace size parameter with type parameter, add
        param_ops parameter.
        * ipa-predicat.c (expr_eval_ops_equal_p): New function.
        (predicate::add_clause): Add comparisons on type and param_ops.
        (dump_condition): Add debug dump for param_ops.
        (remap_after_inlining): Adjust call arguments to add_condition.
        (add_condition): Replace size parameter with type parameter, add
        param_ops parameter. Unshare constant value used in conditions.
        * ipa-fnsummary.c (evaluate_conditions_for_known_args): Fold
        parameter expressions using param_ops.
        (decompose_param_expr):  New function.
        (set_cond_stmt_execution_predicate): Use call to decompose_param_expr
        to replace call to unmodified_parm_or_parm_agg_item.
        (set_switch_stmt_execution_predicate): Likewise.
        (will_be_nonconstant_expr_predicate): Likewise. Replace usage of size
        with type.
        (inline_read_section): Read param_ops from summary stream.
        (ipa_fn_summary_write): Write param_ops to summary stream.

2019-10-16  Feng Xue  <fxue@os.amperecomputing.com>

        PR ipa/91088
        * gcc.dg/ipa/pr91088.c: New test.
        * gcc.dg/ipa/pr91089.c: Add sub-test for range analysis.
        * g++.dg/tree-ssa/ivopts-3.C: Force a function to be noinline.

From-SVN: r277054
      Feng Xue committed
    • [_GLIBCXX_DEBUG] Clarify constness and state <unknown> entries. · 8cf9bbd2 
      	* src/c++11/debug.cc (print_field): Replace constness_names <unknown>
	entry with <unknown constness>. Replace state_names <unknown> entry with
	<unknown state>.

From-SVN: r277049
      François Dumont committed
    • Daily bump. · 6c1ee906 
      From-SVN: r277033
      GCC Administrator committed
  5. 15 Oct, 2019 17 commits