Commit 3599dfba by Andrew Burgess Committed by Jim Wilson

RISC-V: Include more registers in SIBCALL_REGS.

This finishes the part 1 of 2 patch submitted by Andrew Burgess on Aug 19.
This adds the argument registers but not t0 (aka x5) to SIBCALL_REGS.  It
also adds the missing riscv_regno_to_class change.

Tested with cross riscv32-elf and riscv64-linux toolchain build and check.
There were no regressions.  I see about a 0.01% code size reduction for the
C and libstdc++ libraries.

	gcc/
	* config/riscv/riscv.h (REG_CLASS_CONTENTS): Add argument passing
	regs to SIBCALL_REGS.
	* config/riscv/riscv.c (riscv_regno_to_class): Change argument
	passing regs to SIBCALL_REGS.

Co-Authored-By: Jim Wilson <jimw@sifive.com>

From-SVN: r277082
parent 2fcb55d1
2019-10-16 Andrew Burgess <andrew.burgess@embecosm.com>
Jim Wilson <jimw@sifive.com>
* config/riscv/riscv.h (REG_CLASS_CONTENTS): Add argument passing
regs to SIBCALL_REGS.
* config/riscv/riscv.c (riscv_regno_to_class): Change argument
passing regs to SIBCALL_REGS.
2019-10-16 Martin Sebor <msebor@redhat.com> 2019-10-16 Martin Sebor <msebor@redhat.com>
PR tree-optimization/83821 PR tree-optimization/83821
......
...@@ -256,9 +256,9 @@ enum riscv_microarchitecture_type riscv_microarchitecture; ...@@ -256,9 +256,9 @@ enum riscv_microarchitecture_type riscv_microarchitecture;
const enum reg_class riscv_regno_to_class[FIRST_PSEUDO_REGISTER] = { const enum reg_class riscv_regno_to_class[FIRST_PSEUDO_REGISTER] = {
GR_REGS, GR_REGS, GR_REGS, GR_REGS, GR_REGS, GR_REGS, GR_REGS, GR_REGS,
GR_REGS, GR_REGS, SIBCALL_REGS, SIBCALL_REGS, GR_REGS, GR_REGS, SIBCALL_REGS, SIBCALL_REGS,
JALR_REGS, JALR_REGS, JALR_REGS, JALR_REGS, JALR_REGS, JALR_REGS, SIBCALL_REGS, SIBCALL_REGS,
JALR_REGS, JALR_REGS, JALR_REGS, JALR_REGS, SIBCALL_REGS, SIBCALL_REGS, SIBCALL_REGS, SIBCALL_REGS,
JALR_REGS, JALR_REGS, JALR_REGS, JALR_REGS, SIBCALL_REGS, SIBCALL_REGS, JALR_REGS, JALR_REGS,
JALR_REGS, JALR_REGS, JALR_REGS, JALR_REGS, JALR_REGS, JALR_REGS, JALR_REGS, JALR_REGS,
JALR_REGS, JALR_REGS, JALR_REGS, JALR_REGS, JALR_REGS, JALR_REGS, JALR_REGS, JALR_REGS,
SIBCALL_REGS, SIBCALL_REGS, SIBCALL_REGS, SIBCALL_REGS, SIBCALL_REGS, SIBCALL_REGS, SIBCALL_REGS, SIBCALL_REGS,
......
...@@ -400,7 +400,7 @@ enum reg_class ...@@ -400,7 +400,7 @@ enum reg_class
#define REG_CLASS_CONTENTS \ #define REG_CLASS_CONTENTS \
{ \ { \
{ 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \ { 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
{ 0xf00000c0, 0x00000000, 0x00000000 }, /* SIBCALL_REGS */ \ { 0xf003fcc0, 0x00000000, 0x00000000 }, /* SIBCALL_REGS */ \
{ 0xffffffc0, 0x00000000, 0x00000000 }, /* JALR_REGS */ \ { 0xffffffc0, 0x00000000, 0x00000000 }, /* JALR_REGS */ \
{ 0xffffffff, 0x00000000, 0x00000000 }, /* GR_REGS */ \ { 0xffffffff, 0x00000000, 0x00000000 }, /* GR_REGS */ \
{ 0x00000000, 0xffffffff, 0x00000000 }, /* FP_REGS */ \ { 0x00000000, 0xffffffff, 0x00000000 }, /* FP_REGS */ \
......
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