* include/experimental/bits/fs_path.h (__is_path_src)
	(_S_range_begin, _S_range_end): Overload to treat string_view as a
	Source object.
	(path::operator+=, path::compare): Overload for basic_string_view.
	* testsuite/experimental/filesystem/path/construct/string_view.cc:
	New test.
	* testsuite/experimental/filesystem/path/construct/
	string_view_cxx17.cc: New test.

From-SVN: r241658

	* dojump.c (do_jump_by_parts_greater_rtx): Invert probability when
	swapping the arms of the branch.
	* internal-fn.c (expand_addsub_overflow): Use a straight-line code
	sequence for the generic signed-signed-signed case.

From-SVN: r241656

    
    I noticed a stray useless output line when building libgo.
    
    Reviewed-on: https://go-review.googlesource.com/32294

From-SVN: r241655

	* include/experimental/bits/fs_path.h
	(path::_S_convert<_Iter>(_Iter, _Iter)): Remove cv-qualifiers from
	iterator's value_type.
	(path::_S_convert<_Iter>(_Iter __first, __null_terminated)): Likewise.
	Do not use operation not supported by input iterators.
	(path::__is_path_iter_src): Add partial specialization for const
	encoded character types.
	* testsuite/experimental/filesystem/path/construct/range.cc: Test
	construction from input iterators with const value types.

From-SVN: r241654

re PR debug/77773 (Segfault when compiling __simd64_float16_t using arm-none-eabi-g++ with debug information)

	PR debug/77773
	* c-pretty-print.c (simple_type_specifier): Do not dereference `t'
	if NULL.

From-SVN: r241653

	* config/bfin/bfin.c (bfin_legitimate_address_p): Add missing
	fallthru comment.
	* config/bfin/bfin.h (TARGET_CPU_CPP_BUILTINS): Likewise.

From-SVN: r241651

This patch makes scheduling not reorder prologue insns relative to
epilogue insns and vice versa.  This fixes PR78029.

The problem in that PR:
We have two insns, in this order:

(insn/f 300 299 267 8 (set (reg:DI 65 lr)
        (reg:DI 0 0)) 579 {*movdi_internal64}
     (expr_list:REG_DEAD (reg:DI 0 0)
        (expr_list:REG_CFA_RESTORE (reg:DI 65 lr)
            (nil))))
...
(insn/f 310 268 134 8 (set (mem/c:DI (plus:DI (reg/f:DI 1 1)
                (const_int 144 [0x90])) [6  S8 A8])
        (reg:DI 0 0)) 579 {*movdi_internal64}
     (expr_list:REG_DEAD (reg:DI 0 0)
        (expr_list:REG_CFA_OFFSET (set (mem/c:DI (plus:DI (reg/f:DI 1 1)
                        (const_int 144 [0x90])) [6  S8 A8])
                (reg:DI 65 lr))
            (nil))))

and sched swaps them (when compiling for power6, it tries to put memory
stores together, so insn 310 is moved up past 300 to go together with
some other store).  But the REG_CFA_RESTORE and REG_CFA_OFFSET cannot be
swapped (they both say where the orig value of LR now lives).


	PR rtl-optimization/78029
	* function.c (prologue_contains, epilogue_contains): New functions.
	(record_prologue_seq, record_epilogue_seq): New functions.
	* function.h (prologue_contains, epilogue_contains,
	record_prologue_seq, record_epilogue_seq): New declarations.
	* sched-deps.c (sched_analyze_insn): Make dependencies to prevent
	mixing prologue and epilogue insns.
	(init_deps): Initialize the new fields in struct deps_desc.
	* sched-int.h (struct deps_desc): New fields last_prologue,
	last_epilogue, and last_logue_was_epilogue.
	* shrink-wrap.c (emit_common_heads_for_components): Record all
	emitted prologue and epilogue insns.
	(emit_common_tails_for_components): Ditto.
	(insert_prologue_epilogue_for_components): Ditto.

From-SVN: r241650

2016-10-28  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

	PR middle-end/22141
	* Makefile.in (OBJS): Add gimple-ssa-store-merging.o.
	* common.opt (fstore-merging): New Optimization option.
	* opts.c (default_options_table): Add entry for
	OPT_ftree_store_merging.
	* fold-const.h (can_native_encode_type_p): Declare prototype.
	* fold-const.c (can_native_encode_type_p): Define.
	* params.def (PARAM_STORE_MERGING_ALLOW_UNALIGNED): Define.
	(PARAM_MAX_STORES_TO_MERGE): Likewise.
	* timevar.def (TV_GIMPLE_STORE_MERGING): New timevar.
	* passes.def: Insert pass_tree_store_merging.
	* tree-pass.h (make_pass_store_merging): Declare extern
	prototype.
	* gimple-ssa-store-merging.c: New file.
	* doc/invoke.texi (Optimization Options): Document
	-fstore-merging.
	(--param documentation): Document store-merging-allow-unaligned
	and max-stores-to-merge.

2016-10-28  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
            Jakub Jelinek  <jakub@redhat.com>
            Andrew Pinski  <pinskia@gmail.com>

	PR middle-end/22141
	PR rtl-optimization/23684
	* gcc.c-torture/execute/pr22141-1.c: New test.
	* gcc.c-torture/execute/pr22141-2.c: Likewise.
	* gcc.target/aarch64/ldp_stp_1.c: Adjust for -fstore-merging.
	* gcc.target/aarch64/ldp_stp_4.c: Likewise.
	* gcc.dg/store_merging_1.c: New test.
	* gcc.dg/store_merging_2.c: Likewise.
	* gcc.dg/store_merging_3.c: Likewise.
	* gcc.dg/store_merging_4.c: Likewise.
	* gcc.dg/store_merging_5.c: Likewise.
	* gcc.dg/store_merging_6.c: Likewise.
	* gcc.dg/store_merging_7.c: Likewise.
	* gcc.target/i386/pr22141.c: Likewise.
	* gcc.target/i386/pr34012.c: Add -fno-store-merging to dg-options.
	* g++.dg/init/new17.C: Likewise.



Co-Authored-By: Andrew Pinski <pinskia@gmail.com>
Co-Authored-By: Jakub Jelinek <jakub@redhat.com>

From-SVN: r241649

	* doc/xml/manual/status_cxx2017.xml: Update status.
	* doc/html/*: Regenerate.
	* include/std/type_traits (has_unique_object_representations): Guard
	with __has_builtin check.
	* libsupc++/new (launder): Define for C++17.
	* testsuite/18_support/launder/1.cc: New test.
	* testsuite/18_support/launder/requirements.cc: New test.
	* testsuite/18_support/launder/requirements_neg.cc: New test.

From-SVN: r241648

gcc:
2016-10-26  Will Schmidt <will_schmidt@vnet.ibm.com>

        PR middle-end/72747
        * gimplify.c (gimplify_init_constructor): Move emit of constructor
        assignment to earlier in the if/else logic.

testsuite:
2016-10-26  Will Schmidt <will_schmidt@vnet.ibm.com>

        PR middle-end/72747
        * c-c++-common/pr72747-1.c: New test.
        * c-c++-common/pr72747-2.c: Likewise.

From-SVN: r241647

2016-10-28  Richard Biener  <rguenther@suse.de>

	PR middle-end/78128
	PR middle-end/71002
	* fold-const.c (make_bit_field_ref): Only adjust alias set
	when the original alias set was zero.

From-SVN: r241645

This patch adds a magic OSC (operand store compare) break instruction
which is necessary if a store is followed closely by a load with same
base+indx+displ while either base or index get modified in between.

The patch improves several SpecCPU testcases running on IBM z13.

gcc/testsuite/ChangeLog:

2016-10-28  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>

	* gcc.target/s390/oscbreak-1.c: New test.

gcc/ChangeLog:

2016-10-28  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>

	* config/s390/s390.c (s390_adjust_loop_scan_osc): New function.
	(s390_adjust_loops): New function.
	(s390_reorg): Invoke s390_adjust_loops.
	* config/s390/s390.md: (UNSPEC_OSC_BREAK): New constant.
	("osc_break"): New insn definition.

From-SVN: r241644

This patch adds an alternate CPU level naming following the
architecture level number in the Principles of Operations manual.  So
instead of having z196, zEC12, and z13 you can use arch9, arch10, and
arch11.  The old cpu names stay valid and should preferably be used.

The alternate names are supposed to improve compatibility with the IBM
XL compiler toolchain which uses the arch numbering.

gcc/testsuite/ChangeLog:

2016-10-28  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>

	* gcc.target/s390/target-attribute/tattr-m64-33.c: New test.

gcc/ChangeLog:

2016-10-28  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>

	* config/s390/s390.opt: Support alternate cpu level naming (archXX).
	* config.gcc: Support alternate archXX cpu levels with
	--with-arch= and --with-tune=.
	* config/s390/linux.h: Translate new archXX cpu levels to the
	original names when calling GAS.
	* config/s390/tpf.h: Likewise.
	* doc/invoke.texi: Document the alternate cpu level names.

From-SVN: r241643

	PR rtl-optimization/77919
	* expr.c (expand_expr_real_1) <normal_inner_ref>: Force CONCAT into
	MEM if mode1 is not a complex mode.

	* g++.dg/torture/pr77919.C: New test.

From-SVN: r241642

	PR rtl-optimization/78132
	* ree.c (combine_reaching_defs): Give up if copy_needed and
	!HARD_REGNO_MODE_OK (REGNO (src_reg), dst_mode).

	* gcc.target/i386/pr78132.c: New test.

From-SVN: r241641

From-SVN: r241640

Index: ChangeLog
===================================================================
--- ChangeLog	(revision 241636)
+++ ChangeLog	(working copy)
@@ -1,3 +1,7 @@
+2016-10-27  Carl Love  <cel@us.ibm.com>
+
+	* MAINTAINERS (Write After Approval): Add myself.
+
 2016-10-27  Andrew Burgess  <andrew.burgess@embecosm.com>
 
 	* MAINTAINERS (Reviewers): Add myself.
Index: MAINTAINERS
===================================================================
--- MAINTAINERS	(revision 241636)
+++ MAINTAINERS	(working copy)
@@ -479,6 +479,7 @@
 Manuel López-Ibáñez				<manu@gcc.gnu.org>
 Martin v. Löwis					<loewis@informatik.hu-berlin.de>
 H.J. Lu						<hjl.tools@gmail.com>
+Carl Love					<cel@us.ibm.com>
 Christophe Lyon					<christophe.lyon@st.com>
 Luis Machado					<luisgpm@br.ibm.com>
 Ziga Mahkovec					<ziga.mahkovec@klika.si>

From-SVN: r241637

From-SVN: r241634

From-SVN: r241632

constraints.md (wH constraint): Add new constraints for allowing 32-bit integers (and eventually 8/16-bit...

[gcc]
2016-10-27  Michael Meissner  <meissner@linux.vnet.ibm.com>

	* config/rs6000/constraints.md (wH constraint): Add new
	constraints for allowing 32-bit integers (and eventually 8/16-bit
	integers) into the vector registers.
	(wI constraint): Likewise.
	(wJ constraint): Likewise.
	(wK constraint): Likewise.
	* config/rs6000/rs6000-cpus.def (ISA_2_7_MASKS_SERVER): Add
	-mvsx-small-integer as a default option for ISA 2.07
	(i.e. power8).
	(POWERPC_MASKS): Likewise.
	* config/rs6000/rs6000.opt (-mvsx-small-integer): Add new debug
	switch to turn off small integer support in vector registers.
	* config/rs6000/rs6000.c (rs6000_hard_regno_mode_ok): Eliminate
	test for -mupper-regs-di, since it is already done with the
	reg_add[mode].scalar_in_vsx_p.  Add support for the switch
	-mvsx-small-integer.
	(rs6000_debug_reg_global): Add support for wH, wI, wJ, and wK
	constraints.
	(rs6000_setup_reg_addr_masks): Likewise.
	(rs6000_init_hard_regno_mode_ok): Likewise.
	(rs6000_option_override_internal): Add consistency checks for
	-mvsx-small-integer.
	(rs6000_secondary_reload_simple_move): SImode is a simple move if
	-mvsx-small-integer.
	(rs6000_secondary_reload): Use std::swap.
	(rs6000_preferred_reload_class): Don't prefer FLOAT_REGS over
	VSX_REGS for small integers in vector registers, since there is no
	D-FORM address mode for such types.
	(rs6000_register_move_cost): Use FIRST_FPR_REGNO instead of 32.
	(rs6000_opt_masks): Add -mvsx-small-integer.
	* config/rs6000/vsx.md (VSINT_84): Add SImode for small integer
	support.
	(VSX_EXTRACT_I2): Clone VSX_EXTRACT_I, but drop V4SI since SImode
	extracts can be done on ISA 2.07.
	(vsx_extract_<mode>): Add support for small integers in vsx
	registers.
	(vsx_extract_<mode>_p9): Use 'v' instead of VSX_EX, since we no
	longer support V4SImode in this pattern.
	(vsx_extract_si): New insn to support extraction of SImode in ISA
	2.07 using either xxextractuw or vspltw.
	(vsx_extract_<mode>_p8): Use 'v' instead of VSX_EX, since we no
	longer support V4SImode in this pattern.
	* config/rs6000/rs6000.h (enum rs6000_reg_class_enum): Add wH, wI,
	wJ, and wK constraints.
	* config/rs6000/rs6000.md (f32_sv): Use correct instruction for
	storing SDmode with VSX instructions.
	(zero_extendsi<mode>2): Reorder pattern, so RLDICL comes after the
	GPR load and before the FPR and VSX loads.  Remove ??, ! from the
	constraints.  Add MFVSRWZ and XXEXTRACTUW instructions to support
	small integers in vector registers.
	(extendsi<mode>2): Reorder pattern, so EXTSW comes after the GPR
	load and before the FPR and VSX loads.  Remove ??, ! from the
	constraints.  Add VEXTSW2D support for small integers in vector
	registers.
	(lfiwax): Remove ! constraint.  Add VEXTSW2D support for small
	integers in vector registers.
	(floatsi<mode>2_lfiwax): If -mvsx-small-integer issue a normal
	move instead of using an UNSPEC.
	(lfiwzx): Remove ! constraint.  Add XXEXTRACTUW support for small
	integers in vector registers.
	(floatunssi<mode>2_lfiwzx): If -mvsx-small-integer issue a normal
	move instead of using an UNSPEC.
	(movsi_internal1): Add support for -mvsx-small-integer.  Align
	columns so that it is more readable.
	(SImode splitter for ISA 3.0 constants): Add splitter for
	-128..127 constants that can easily be constructed on ISA 3.0.
	* doc/md.texi (PowerPC Constraints): Document wH, wI, wJ, and wK
	constraints.

[gcc/testsuite]
2016-10-27  Michael Meissner  <meissner@linux.vnet.ibm.com>

	* gcc.target/powerpc/vsx-simode.c: New test.
	* gcc.target/powerpc/vsx-simode2.c: Likewise.
	* gcc.target/powerpc/vsx-simode3.c: Likewise.

From-SVN: r241631

	PR fortran/78026
	* parse.c (decode_statement): Don't create namespace for possible
	select type here and destroy it afterwards.
	(parse_select_type_block): Set gfc_current_ns to new_st.ext.block.ns.
	(parse_executable, gfc_parse_file): Formatting fixes.
	* match.c (gfc_match_select_type): Create namespace for select type
	here, only after matching select type.  Formatting fixes.  Free that
	namespace if not returning MATCH_YES, after gfc_undo_symbols,
	otherwise remember it in new_st.ext.block.ns and switch to parent
	namespace anyway.

	* gfortran.dg/gomp/pr78026.f03: New test.
	* gfortran.dg/select_type_38.f03: New test.

From-SVN: r241630

	PR libstdc++/70975
	* src/filesystem/ops.cc (do_copy_file) [_GLIBCXX_USE_SENDFILE]:
	Pass non-null pointer to sendfile for offset argument.

From-SVN: r241629

	PR middle-end/78025
	* omp-simd-clone.c (simd_clone_adjust): Handle noreturn declare simd
	functions.

	* g++.dg/gomp/declare-simd-7.C: New test.

From-SVN: r241628

	* oacc-init.c (goacc_new_thread): Use sizeof of the appropriate
	size when allocating new thread.

From-SVN: r241627

	gcc/fortran/
	* expr.c (generate_union_initializer, get_union_initializer): New.
	* expr.c (component_initializer): Consider BT_UNION specially.
	* resolve.c (resolve_structure_cons): Hack for BT_UNION.
	* trans-expr.c (gfc_trans_subcomponent_assign): Ditto.
	* trans-expr.c (gfc_conv_union_initializer): New.
	* trans-expr.c (gfc_conv_structure): Replace UNION handling code with
	new function gfc_conv_union_initializer.

	gcc/testsuite/gfortran.dg/
	* dec_init_1.f90, dec_init_2.f90: Remove -fdump-tree-original.
	* dec_init_3.f90, dec_init_4.f90: New tests.

From-SVN: r241626

	* builtins.c (expand_builtin_nonlocal_goto): Avoid evaluating
	PIC_OFFSET_TABLE_REGNUM twice.

From-SVN: r241625

match.pd ((convert (op:s (convert@2 @0) (convert?@3 @1)))): Add support for constant operand for OP.

	* match.pd ((convert (op:s (convert@2 @0) (convert?@3 @1)))): Add
	support for constant operand for OP.

	gcc/testsuite
	* gcc.dg/fold-narrowbopcst-1.c: New test.

From-SVN: r241624

	gcc/testsuite/gfortran.dg/
	* dec_io_5.f90, dec_io_6.f90: Don't use "test.txt", and use
	dg-shouldfail/dg-output instead of XFAIL.

From-SVN: r241623

	* dwarf2out.c (gen_member_die): Only reparent_child instead of
	splice_child_die if child doesn't have DW_AT_specification attribute.

From-SVN: r241622

	* testsuite/ext/random/uniform_inside_sphere_distribution/cons/
	default.cc: Fix effective target selector.
	* testsuite/ext/random/uniform_inside_sphere_distribution/cons/
	parms.cc: Likewise.
	* testsuite/ext/random/uniform_inside_sphere_distribution/operators/
	equal.cc: Likewise.
	* testsuite/ext/random/uniform_inside_sphere_distribution/operators/
	generate.cc: Likewise.
	* testsuite/ext/random/uniform_inside_sphere_distribution/operators/
	inequal.cc: Likewise.
	* testsuite/ext/random/uniform_inside_sphere_distribution/operators/
	serialize.cc: Likewise.

From-SVN: r241621

From-SVN: r241620

	* MAINTAINERS (Reviewers): Add myself.
	(Write After Approval): Add myself.

From-SVN: r241619

	* testsuite/experimental/filesystem/iterators/directory_iterator.cc:
	Use end() function to get end iterator.
	* testsuite/experimental/filesystem/iterators/pop.cc: Remove printf
	statements that were present for debugging.
	* testsuite/experimental/filesystem/iterators/
	recursive_directory_iterator.cc: Use end() function to get end
	iterator.
	* testsuite/experimental/filesystem/operations/last_write_time.cc:
	Only require file timestamps to be accurate to one second.

From-SVN: r241616

2016-10-27  Thomas Preud'homme  <thomas.preudhomme@arm.com>

    gcc/
    * config/arm/arm.h (TARGET_HAVE_LDREX): Define for ARMv8-M Baseline.
    (TARGET_HAVE_LDREXBH): Likewise.
    (TARGET_HAVE_LDACQ): Likewise.

    gcc/testsuite/
    * gcc.target/arm/atomic-comp-swap-release-acquire-3.c: New test.
    * gcc.target/arm/atomic-op-acq_rel-3.c: Likewise.
    * gcc.target/arm/atomic-op-acquire-3.c: Likewise.
    * gcc.target/arm/atomic-op-char-3.c: Likewise.
    * gcc.target/arm/atomic-op-consume-3.c: Likewise.
    * gcc.target/arm/atomic-op-int-3.c: Likewise.
    * gcc.target/arm/atomic-op-relaxed-3.c: Likewise.
    * gcc.target/arm/atomic-op-release-3.c: Likewise.
    * gcc.target/arm/atomic-op-seq_cst-3.c: Likewise.
    * gcc.target/arm/atomic-op-short-3.c: Likewise.

From-SVN: r241615

2016-10-27  Thomas Preud'homme  <thomas.preudhomme@arm.com>

    gcc/
    * config/arm/arm.c (arm_split_atomic_op): Add function comment.  Add
    logic to to decide whether to copy over old value to register for new
    value.
    * config/arm/sync.md: Add comments explaning why mode and code
    attribute are not defined in iterators.md
    (thumb1_atomic_op_str): New code attribute.
    (thumb1_atomic_newop_str): Likewise.
    (thumb1_atomic_fetch_op_str): Likewise.
    (thumb1_atomic_fetch_newop_str): Likewise.
    (thumb1_atomic_fetch_oldop_str): Likewise.
    (atomic_exchange<mode>): Add new ARMv8-M Baseline only alternatives to
    mirror the more restrictive constraints of the Thumb-1 insns after
    split compared to Thumb-2 counterpart insns.
    (atomic_<sync_optab><mode>): Likewise.  Add comment to keep constraints
    in sync with non atomic version.
    (atomic_nand<mode>): Likewise.
    (atomic_fetch_<sync_optab><mode>): Likewise.
    (atomic_fetch_nand<mode>): Likewise.
    (atomic_<sync_optab>_fetch<mode>): Likewise.
    (atomic_nand_fetch<mode>): Likewise.
    * config/arm/thumb1.md (thumb1_addsi3): Add comment to keep contraint
    in sync with atomic version.
    (thumb1_subsi3_insn): Likewise.
    (thumb1_andsi3_insn): Likewise.
    (thumb1_iorsi3_insn): Likewise.
    (thumb1_xorsi3_insn): Likewise.

From-SVN: r241614

plugin.c (register_plugin_info): Produce an error message if the plugin is not found in the hash table.

	* plugin.c (register_plugin_info): Produce an error message if the
	plugin is not found in the hash table.

From-SVN: r241613

	* match.pd ((convert1 (minmax ((convert2 (x) c)))) -> minmax (x c)):
	New pattern.

	gcc/testsuite
	* gcc.dg/fold-convmaxconv-1.c: New test.
	* gcc.dg/fold-convminconv-1.c: New test.

From-SVN: r241612

2016-10-26  Steven G. Kargl <kargl@gcc.gnu.org>

	PR fortran/78092
	* trans-intrinsic.c (gfc_conv_intrinsic_sizeof):  Fix reference to an
	array element of type CLASS.

2016-10-26  Steven G. Kargl <kargl@gcc.gnu.org>

	PR fortran/78092
	* gfortran.dg/pr78092.f90: New test.

From-SVN: r241610

From-SVN: r241609

2016-10-26  François Dumont  <fdumont@gcc.gnu.org>

	* include/bits/stl_map.h (map()): Make default.
	* include/bits/stl_multimap.h (multimap()): Likewise.
	* include/bits/stl_multiset.h (multiset()): Likewise.
	* include/bits/stl_set.h (set()): Likewise.
	* include/bits/stl_tree.h (_Rb_tree_impl()): Add conditional noexcept.
	(_Rb_tree()): Make default.

From-SVN: r241601