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Commit ddb92ab9 by Thomas Preud'homme Committed by Thomas Preud'homme
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Enable ARMv8-M atomic and synchronization support for ARMv8-M Baseline 

2016-10-27  Thomas Preud'homme  <thomas.preudhomme@arm.com>

    gcc/
    * config/arm/arm.h (TARGET_HAVE_LDREX): Define for ARMv8-M Baseline.
    (TARGET_HAVE_LDREXBH): Likewise.
    (TARGET_HAVE_LDACQ): Likewise.

    gcc/testsuite/
    * gcc.target/arm/atomic-comp-swap-release-acquire-3.c: New test.
    * gcc.target/arm/atomic-op-acq_rel-3.c: Likewise.
    * gcc.target/arm/atomic-op-acquire-3.c: Likewise.
    * gcc.target/arm/atomic-op-char-3.c: Likewise.
    * gcc.target/arm/atomic-op-consume-3.c: Likewise.
    * gcc.target/arm/atomic-op-int-3.c: Likewise.
    * gcc.target/arm/atomic-op-relaxed-3.c: Likewise.
    * gcc.target/arm/atomic-op-release-3.c: Likewise.
    * gcc.target/arm/atomic-op-seq_cst-3.c: Likewise.
    * gcc.target/arm/atomic-op-short-3.c: Likewise.

From-SVN: r241615
parent 33cab746
Showing with 127 additions and 3 deletions
gcc/ChangeLog
2016-10-27 Thomas Preud'homme <thomas.preudhomme@arm.com>
* config/arm/arm.h (TARGET_HAVE_LDREX): Define for ARMv8-M Baseline.
(TARGET_HAVE_LDREXBH): Likewise.
(TARGET_HAVE_LDACQ): Likewise.
2016-10-27 Thomas Preud'homme <thomas.preudhomme@arm.com>
* config/arm/arm.c (arm_split_atomic_op): Add function comment. Add
logic to to decide whether to copy over old value to register for new
value.
gcc/config/arm/arm.h
......@@ -252,21 +252,25 @@ extern void (*arm_lang_output_object_attributes_hook)(void);
#define TARGET_HAVE_MEMORY_BARRIER (TARGET_HAVE_DMB || TARGET_HAVE_DMB_MCR)
/* Nonzero if this chip supports ldrex and strex */
#define TARGET_HAVE_LDREX ((arm_arch6 && TARGET_ARM) || arm_arch7)
#define TARGET_HAVE_LDREX ((arm_arch6 && TARGET_ARM) \
|| arm_arch7 \
|| (arm_arch8 && !arm_arch_notm))
/* Nonzero if this chip supports LPAE. */
#define TARGET_HAVE_LPAE \
(arm_arch7 && ARM_FSET_HAS_CPU1 (insn_flags, FL_FOR_ARCH7VE))
/* Nonzero if this chip supports ldrex{bh} and strex{bh}. */
#define TARGET_HAVE_LDREXBH ((arm_arch6k && TARGET_ARM) || arm_arch7)
#define TARGET_HAVE_LDREXBH ((arm_arch6k && TARGET_ARM) \
|| arm_arch7 \
|| (arm_arch8 && !arm_arch_notm))
/* Nonzero if this chip supports ldrexd and strexd. */
#define TARGET_HAVE_LDREXD (((arm_arch6k && TARGET_ARM) \
|| arm_arch7) && arm_arch_notm)
/* Nonzero if this chip supports load-acquire and store-release. */
#define TARGET_HAVE_LDACQ (TARGET_ARM_ARCH >= 8 && TARGET_32BIT)
#define TARGET_HAVE_LDACQ (TARGET_ARM_ARCH >= 8)
/* Nonzero if this chip supports LDAEXD and STLEXD. */
#define TARGET_HAVE_LDACQEXD (TARGET_ARM_ARCH >= 8 \
......
gcc/testsuite/ChangeLog
2016-10-27 Thomas Preud'homme <thomas.preudhomme@arm.com>
* gcc.target/arm/atomic-comp-swap-release-acquire-3.c: New test.
* gcc.target/arm/atomic-op-acq_rel-3.c: Likewise.
* gcc.target/arm/atomic-op-acquire-3.c: Likewise.
* gcc.target/arm/atomic-op-char-3.c: Likewise.
* gcc.target/arm/atomic-op-consume-3.c: Likewise.
* gcc.target/arm/atomic-op-int-3.c: Likewise.
* gcc.target/arm/atomic-op-relaxed-3.c: Likewise.
* gcc.target/arm/atomic-op-release-3.c: Likewise.
* gcc.target/arm/atomic-op-seq_cst-3.c: Likewise.
* gcc.target/arm/atomic-op-short-3.c: Likewise.
2016-10-27 Bin Cheng <bin.cheng@arm.com>
* gcc.dg/fold-convmaxconv-1.c: New test.
......
gcc/testsuite/gcc.target/arm/atomic-comp-swap-release-acquire-3.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_arch_v8m_base_ok } */
/* { dg-options "-O2 -fno-ipa-icf" } */
/* { dg-add-options arm_arch_v8m_base } */
#include "../aarch64/atomic-comp-swap-release-acquire.x"
/* { dg-final { scan-assembler-times "ldaex" 4 } } */
/* { dg-final { scan-assembler-times "stlex" 4 } } */
/* { dg-final { scan-assembler-not "dmb" } } */
gcc/testsuite/gcc.target/arm/atomic-op-acq_rel-3.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_arch_v8m_base_ok } */
/* { dg-options "-O2" } */
/* { dg-add-options arm_arch_v8m_base } */
#include "../aarch64/atomic-op-acq_rel.x"
/* { dg-final { scan-assembler-times "ldaex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
/* { dg-final { scan-assembler-times "stlex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
/* { dg-final { scan-assembler-not "dmb" } } */
gcc/testsuite/gcc.target/arm/atomic-op-acquire-3.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_arch_v8m_base_ok } */
/* { dg-options "-O2" } */
/* { dg-add-options arm_arch_v8m_base } */
#include "../aarch64/atomic-op-acquire.x"
/* { dg-final { scan-assembler-times "ldaex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
/* { dg-final { scan-assembler-times "strex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
/* { dg-final { scan-assembler-not "dmb" } } */
gcc/testsuite/gcc.target/arm/atomic-op-char-3.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_arch_v8m_base_ok } */
/* { dg-options "-O2" } */
/* { dg-add-options arm_arch_v8m_base } */
#include "../aarch64/atomic-op-char.x"
/* { dg-final { scan-assembler-times "ldrexb\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
/* { dg-final { scan-assembler-times "strexb\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
/* { dg-final { scan-assembler-not "dmb" } } */
gcc/testsuite/gcc.target/arm/atomic-op-consume-3.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_arch_v8m_base_ok } */
/* { dg-options "-O2" } */
/* { dg-add-options arm_arch_v8m_base } */
#include "../aarch64/atomic-op-consume.x"
/* Scan for ldaex is a PR59448 consume workaround. */
/* { dg-final { scan-assembler-times "ldaex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
/* { dg-final { scan-assembler-times "strex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
/* { dg-final { scan-assembler-not "dmb" } } */
gcc/testsuite/gcc.target/arm/atomic-op-int-3.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_arch_v8m_base_ok } */
/* { dg-options "-O2" } */
/* { dg-add-options arm_arch_v8m_base } */
#include "../aarch64/atomic-op-int.x"
/* { dg-final { scan-assembler-times "ldrex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
/* { dg-final { scan-assembler-times "strex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
/* { dg-final { scan-assembler-not "dmb" } } */
gcc/testsuite/gcc.target/arm/atomic-op-relaxed-3.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_arch_v8m_base_ok } */
/* { dg-options "-O2" } */
/* { dg-add-options arm_arch_v8m_base } */
#include "../aarch64/atomic-op-relaxed.x"
/* { dg-final { scan-assembler-times "ldrex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
/* { dg-final { scan-assembler-times "strex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
/* { dg-final { scan-assembler-not "dmb" } } */
gcc/testsuite/gcc.target/arm/atomic-op-release-3.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_arch_v8m_base_ok } */
/* { dg-options "-O2" } */
/* { dg-add-options arm_arch_v8m_base } */
#include "../aarch64/atomic-op-release.x"
/* { dg-final { scan-assembler-times "ldrex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
/* { dg-final { scan-assembler-times "stlex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
/* { dg-final { scan-assembler-not "dmb" } } */
gcc/testsuite/gcc.target/arm/atomic-op-seq_cst-3.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_arch_v8m_base_ok } */
/* { dg-options "-O2" } */
/* { dg-add-options arm_arch_v8m_base } */
#include "../aarch64/atomic-op-seq_cst.x"
/* { dg-final { scan-assembler-times "ldaex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
/* { dg-final { scan-assembler-times "stlex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
/* { dg-final { scan-assembler-not "dmb" } } */
gcc/testsuite/gcc.target/arm/atomic-op-short-3.c 0 → 100644
/* { dg-do compile } */
/* { dg-require-effective-target arm_arch_v8m_base_ok } */
/* { dg-options "-O2" } */
/* { dg-add-options arm_arch_v8m_base } */
#include "../aarch64/atomic-op-short.x"
/* { dg-final { scan-assembler-times "ldrexh\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
/* { dg-final { scan-assembler-times "strexh\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
/* { dg-final { scan-assembler-not "dmb" } } */
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