This fixes a discrepancy in the mechanism tracking the private and full
views of entities when entering and leaving scopes.  This mechanism
records private entities that are dependent on other private entities,
so that the exchange done on entering and leaving scopes can be
propagated.

The propagation is done recursively on entering child units, but it was
not done recursively on leaving them, which would leave the dependency
chains in a uncertain state in this case.  That's mostly visible when
inlining across units is enabled for code involving a lot of generic
units.

2019-08-14  Eric Botcazou  <ebotcazou@adacore.com>

gcc/ada/

	* sem_ch7.adb (Install_Private_Declarations)
	<Swap_Private_Dependents>: Do not rely solely on the
	Is_Child_Unit flag on the unit to recurse.
	(Uninstall_Declarations) <Swap_Private_Dependents>: New
	function.  Use it to recurse on the private dependent entities
	for child units.

gcc/testsuite/

	* gnat.dg/inline18.adb, gnat.dg/inline18.ads,
	gnat.dg/inline18_gen1-inner_g.ads, gnat.dg/inline18_gen1.adb,
	gnat.dg/inline18_gen1.ads, gnat.dg/inline18_gen2.adb,
	gnat.dg/inline18_gen2.ads, gnat.dg/inline18_gen3.adb,
	gnat.dg/inline18_gen3.ads, gnat.dg/inline18_pkg1.adb,
	gnat.dg/inline18_pkg1.ads, gnat.dg/inline18_pkg2-child.ads,
	gnat.dg/inline18_pkg2.ads: New testcase.

From-SVN: r274451

2019-08-14  Javier Miranda  <miranda@adacore.com>

gcc/ada/

	* exp_aggr.adb (Is_CCG_Supported_Aggregate): Return False for
	arrays with bounds not known at compile time.

From-SVN: r274450

This patch fixes a compiler abort on a precondition whose condition
includes a quantified expression.

2019-08-14  Ed Schonberg  <schonberg@adacore.com>

gcc/ada/

	* sem_util.adb (New_Copy_Tree, Visit_Entity): A quantified
	expression includes the implicit declaration of the loop
	parameter. When a quantified expression is copied during
	expansion, for example when building the precondition code from
	the generated pragma, a new loop parameter must be created for
	the new tree, to prevent duplicate declarations for the same
	symbol.

gcc/testsuite/

	* gnat.dg/predicate12.adb, gnat.dg/predicate12.ads: New
	testcase.

From-SVN: r274449

Checking of SPARK elaboration rules may lead to assertion failures on a
compiler built with assertions. Now fixed.

There is no impact on compilation.

2019-08-14  Yannick Moy  <moy@adacore.com>

gcc/ada/

	* sem_disp.adb (Check_Dispatching_Operation): Update assertion
	for the separate declarations created in GNATprove mode.
	* sem_disp.ads (Is_Overriding_Subprogram): Update comment.
	* sem_elab.adb (SPARK_Processor): Fix test for checking of
	overriding primitives.

From-SVN: r274448

No functional changes.

2019-08-14  Eric Botcazou  <ebotcazou@adacore.com>

gcc/ada/

	* inline.adb (Add_Inlined_Body): Tweak comments.
	(List_Inlining_Info): Also list information about non-main
	units.

From-SVN: r274447

The compiler was improperly allowing selection of an object declared
within a task body when the prefix was of the task type, specifically in
the case where the object was the very first declared in the body
(selections of later body declarations were being flagged).  The flag
Is_Private_Op was only set at the point of the first "private"
declaration of the type in cases where the first declaration's name
didn't match the selector.

2019-08-14  Gary Dismukes  <dismukes@adacore.com>

gcc/ada/

	* sem_ch4.adb (Analyze_Selected_Component): In the case where
	the prefix is of a concurrent type, and the selected entity
	matching the selector is the first private declaration of the
	type (such as the first local variable in a task's body), set
	Is_Private_Op.

gcc/testsuite/

	* gnat.dg/task5.adb: New testcase.

From-SVN: r274446

2019-08-14  Piotr Trojanek  <trojanek@adacore.com>

gcc/ada/

	* einfo.adb (Is_Generic_Actual_Subprogram): Replace repeated
	calls to Ekind with Ekind_In.

From-SVN: r274445

2019-08-14  Richard Biener  <rguenther@suse.de>

	PR testsuite/91419
	* lib/target-supports.exp (natural_alignment_32): Amend target
	list based on BIGGEST_ALIGNMENT.
	(natural_alignment_64): Targets not natural_alignment_32 cannot
	be natural_alignment_64.
	* gcc.dg/tree-ssa/pr91091-2.c: XFAIL for !natural_alignment_32.
	* gcc.dg/tree-ssa/ssa-fre-77.c: Likewise.
	* gcc.dg/tree-ssa/ssa-fre-61.c: Require natural_alignment_32.

From-SVN: r274444

This patch adds support for floating-point absolute comparisons
FACLT and FACLE (aliased as FACGT and FACGE with swapped operands).

2019-08-14  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
	* config/aarch64/iterators.md (SVE_COND_FP_ABS_CMP): New iterator.
	* config/aarch64/aarch64-sve.md (*aarch64_pred_fac<cmp_op><mode>):
	New pattern.

gcc/testsuite/
	* gcc.target/aarch64/sve/vcond_21.c: New test.
	* gcc.target/aarch64/sve/vcond_21_run.c: Likewise.

From-SVN: r274443

This patch uses MOV /M to optimise selects between a duplicated
scalar variable and a vector.

2019-08-14  Richard Sandiford  <richard.sandiford@arm.com>
	    Kugan Vivekanandarajah  <kugan.vivekanandarajah@linaro.org>

gcc/
	* config/aarch64/aarch64-sve.md (*aarch64_sel_dup<mode>): New pattern.

gcc/testsuite/
	* g++.target/aarch64/sve/dup_sel_1.C: New test.
	* g++.target/aarch64/sve/dup_sel_2.C: Likewise.
	* g++.target/aarch64/sve/dup_sel_3.C: Likewise.
	* g++.target/aarch64/sve/dup_sel_4.C: Likewise.
	* g++.target/aarch64/sve/dup_sel_5.C: Likewise.
	* g++.target/aarch64/sve/dup_sel_6.C: Likewise.

Co-Authored-By: Kugan Vivekanandarajah <kuganv@linaro.org>

From-SVN: r274442

This patch extends the SVE UNSPEC_SEL patterns so that they can use:

(1) MOV /M of a duplicated integer constant
(2) MOV /M of a duplicated floating-point constant bitcast to an integer,
    accepting the same constants as (1)
(3) FMOV /M of a duplicated floating-point constant
(4) MOV /Z of a duplicated integer constant
(5) MOV /Z of a duplicated floating-point constant bitcast to an integer,
    accepting the same constants as (4)
(6) MOVPRFXed FMOV /M of a duplicated floating-point constant

We already handled (4) with a special pattern; the rest are new.

2019-08-14  Richard Sandiford  <richard.sandiford@arm.com>
	    Kugan Vivekanandarajah  <kugan.vivekanandarajah@linaro.org>

gcc/
	* config/aarch64/aarch64.c (aarch64_bit_representation): New function.
	(aarch64_print_vector_float_operand): Also handle 8-bit floats.
	(aarch64_print_operand): Add support for %I.
	(aarch64_sve_dup_immediate_p): Handle scalars as well as vectors.
	Bitcast floating-point constants to the corresponding integer constant.
	(aarch64_float_const_representable_p): Handle vectors as well
	as scalars.
	(aarch64_expand_sve_vcond): Make sure that the operands are valid
	for the new vcond_mask_<mode><vpred> expander.
	* config/aarch64/predicates.md (aarch64_sve_dup_immediate): Also
	test aarch64_float_const_representable_p.
	(aarch64_sve_reg_or_dup_imm): New predicate.
	* config/aarch64/aarch64-sve.md (vec_extract<vpred><Vel>): Use
	gen_vcond_mask_<mode><vpred> instead of
	gen_aarch64_sve_dup<mode>_const.
	(vcond_mask_<mode><vpred>): Turn into a define_expand that
	accepts aarch64_sve_reg_or_dup_imm and aarch64_simd_reg_or_zero
	for operands 1 and 2 respectively.  Force operand 2 into a
	register if operand 1 is a register.  Fold old define_insn...
	(aarch64_sve_dup<mode>_const): ...and this define_insn...
	(*vcond_mask_<mode><vpred>): ...into this new pattern.  Handle
	floating-point constants that can be moved as integers.  Add
	alternatives for MOV /M and FMOV /M.
	(vcond<mode><v_int_equiv>, vcondu<mode><v_int_equiv>)
	(vcond<mode><v_fp_equiv>): Accept nonmemory_operand for operands
	1 and 2 respectively.
	* config/aarch64/constraints.md (Ufc): Handle vectors as well
	as scalars.
	(vss): New constraint.

gcc/testsuite/
	* gcc.target/aarch64/sve/vcond_18.c: New test.
	* gcc.target/aarch64/sve/vcond_18_run.c: Likewise.
	* gcc.target/aarch64/sve/vcond_19.c: Likewise.
	* gcc.target/aarch64/sve/vcond_19_run.c: Likewise.
	* gcc.target/aarch64/sve/vcond_20.c: Likewise.
	* gcc.target/aarch64/sve/vcond_20_run.c: Likewise.

Co-Authored-By: Kugan Vivekanandarajah <kuganv@linaro.org>

From-SVN: r274441

This patch uses the immediate forms of FMAXNM and FMINNM for
unconditional arithmetic.

The same rules apply to FMAX and FMIN, but we only generate those
via the ACLE.

2019-08-14  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
	* config/aarch64/predicates.md (aarch64_sve_float_maxmin_immediate)
	(aarch64_sve_float_maxmin_operand): New predicates.
	* config/aarch64/constraints.md (vsB): New constraint.
	(vsM): Fix typo.
	* config/aarch64/iterators.md (sve_pred_fp_rhs2_operand): Use
	aarch64_sve_float_maxmin_operand for UNSPEC_COND_FMAXNM and
	UNSPEC_COND_FMINNM.
	* config/aarch64/aarch64-sve.md (<maxmin_uns><SVE_F:mode>3):
	Use aarch64_sve_float_maxmin_operand for operand 2.
	(*<SVE_COND_FP_MAXMIN_PUBLIC:optab><SVE_F:mode>3): Likewise.
	Add alternatives for the constant forms.

gcc/testsuite/
	* gcc.target/aarch64/sve/fmaxnm_1.c: New test.
	* gcc.target/aarch64/sve/fminnm_1.c: Likewise.

From-SVN: r274440

This patch adds support for the immediate forms of SVE SMAX, SMIN, UMAX
and UMIN.  SMAX and SMIN take the same range as MUL, so the patch
basically just moves and generalises the existing MUL patterns.

2019-08-14  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
	* config/aarch64/constraints.md (vsb): New constraint.
	(vsm): Generalize description.
	* config/aarch64/iterators.md (SVE_INT_BINARY_IMM): New code
	iterator.
	(sve_imm_con): Handle smax, smin, umax and umin.
	(sve_imm_prefix): New code attribute.
	* config/aarch64/predicates.md (aarch64_sve_vsb_immediate)
	(aarch64_sve_vsb_operand): New predicates.
	(aarch64_sve_mul_immediate): Rename to...
	(aarch64_sve_vsm_immediate): ...this.
	(aarch64_sve_mul_operand): Rename to...
	(aarch64_sve_vsm_operand): ...this.
	* config/aarch64/aarch64-sve.md (mul<mode>3): Generalize to...
	(<SVE_INT_BINARY_IMM:optab><SVE_I:mode>3): ...this.
	(*mul<mode>3, *post_ra_mul<mode>3): Generalize to...
	(*<SVE_INT_BINARY_IMM:optab><SVE_I:mode>3)
	(*post_ra_<SVE_INT_BINARY_IMM:optab><SVE_I:mode>3): ...these and
	add movprfx support for the immediate alternatives.
	(<su><maxmin><mode>3, *<su><maxmin><mode>3): Delete in favor
	of the above.
	(*<SVE_INT_BINARY_SD:optab><SVE_SDI:mode>3): Fix incorrect predicate
	for operand 3.

gcc/testsuite/
	* gcc.target/aarch64/sve/smax_1.c: New test.
	* gcc.target/aarch64/sve/smin_1.c: Likewise.
	* gcc.target/aarch64/sve/umax_1.c: Likewise.
	* gcc.target/aarch64/sve/umin_1.c: Likewise.

From-SVN: r274439

This patch adds support for predicated and unpredicated CNOT
(logical NOT on integers).  In RTL terms, this is a select between
1 and 0 in which the predicate is fed by a comparison with zero.

2019-08-14  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
	* config/aarch64/predicates.md (aarch64_simd_imm_one): New predicate.
	* config/aarch64/aarch64-sve.md (*cnot<mode>): New pattern.
	(*cond_cnot<mode>_2, *cond_cnot<mode>_any): Likewise.

gcc/testsuite/
	* gcc.target/aarch64/sve/cnot_1.c: New test.
	* gcc.target/aarch64/sve/cond_cnot_1.c: Likewise.
	* gcc.target/aarch64/sve/cond_cnot_1_run.c: Likewise.
	* gcc.target/aarch64/sve/cond_cnot_2.c: Likewise.
	* gcc.target/aarch64/sve/cond_cnot_2_run.c: Likewise.
	* gcc.target/aarch64/sve/cond_cnot_3.c: Likewise.
	* gcc.target/aarch64/sve/cond_cnot_3_run.c: Likewise.

From-SVN: r274438

This patch adds support for unpredicated SVE CLS and CLZ.  A later patch
will add support for predicated unary integer arithmetic.

2019-08-14  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
	* config/aarch64/iterators.md (SVE_INT_UNARY): Add clrsb and clz.
	(optab, sve_int_op): Handle them.
	* config/aarch64/aarch64-sve.md: Expand comment.

gcc/testsuite/
	* gcc.target/aarch64/vect-clz.c: Force SVE off.
	* gcc.target/aarch64/sve/clrsb_1.c: New test.
	* gcc.target/aarch64/sve/clrsb_1_run.c: Likewise.
	* gcc.target/aarch64/sve/clz_1.c: Likewise.
	* gcc.target/aarch64/sve/clz_1_run.c: Likewise.

From-SVN: r274437

This patch uses SVE ADR to optimise shift-and-add and uxtw-and-add
sequences.

2019-08-14  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
	* config/aarch64/predicates.md (const_1_to_3_operand): New predicate.
	* config/aarch64/aarch64-sve.md (*aarch64_adr_uxtw)
	(*aarch64_adr<mode>_shift, *aarch64_adr_shift_uxtw): New patterns.

gcc/testsuite/
	* gcc.target/aarch64/sve/adr_1.c: New test.
	* gcc.target/aarch64/sve/adr_1_run.c: Likewise.
	* gcc.target/aarch64/sve/adr_2.c: Likewise.
	* gcc.target/aarch64/sve/adr_2_run.c: Likewise.
	* gcc.target/aarch64/sve/adr_3.c: Likewise.
	* gcc.target/aarch64/sve/adr_3_run.c: Likewise.
	* gcc.target/aarch64/sve/adr_4.c: Likewise.
	* gcc.target/aarch64/sve/adr_4_run.c: Likewise.
	* gcc.target/aarch64/sve/adr_5.c: Likewise.
	* gcc.target/aarch64/sve/adr_5_run.c: Likewise.

From-SVN: r274436

/cp
2019-08-08  Paolo Carlini  <paolo.carlini@oracle.com>

	* decl.c (grokdeclarator): Use id_loc and EXPR_LOCATION in
	a few error messages.

/testsuite
2019-08-08  Paolo Carlini  <paolo.carlini@oracle.com>

	* g++.dg/cpp0x/enum20.C: Test location(s) too.
	* g++.dg/other/friend3.C: Likewise.
	* g++.dg/parse/dtor5.C: Likewise.
	* g++.dg/parse/friend7.C: Likewise.
	* g++.dg/template/error22.C: Likewise.
	* g++.old-deja/g++.brendan/err-msg5.C: Likewise.

From-SVN: r274435

This patch handles more predicate constants by using TRN1, TRN2
and EOR.  For now, only one operation is allowed before we fall
back to loading from memory or doing an integer move and a compare.
The EOR support includes the important special case of an inverted
predicate.

The real motivating case for this is the ACLE svdupq function,
which allows a repeating 16-bit predicate to be built from
individual scalar booleans.  It's not easy to test properly
before that support is merged.

2019-08-14  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
	* config/aarch64/aarch64.c (aarch64_expand_sve_const_pred_eor)
	(aarch64_expand_sve_const_pred_trn): New functions.
	(aarch64_expand_sve_const_pred_1): Add a recurse_p parameter and
	use the above functions when the parameter is true.
	(aarch64_expand_sve_const_pred): Update call accordingly.
	* config/aarch64/aarch64-sve.md (*aarch64_sve_<perm_insn><mode>):
	Rename to...
	(@aarch64_sve_<perm_insn><mode>): ...this.

gcc/testsuite/
	* gcc.target/aarch64/sve/peel_ind_1.c: Look for an inverted .B VL1.
	* gcc.target/aarch64/sve/peel_ind_2.c: Likewise .S VL7.

From-SVN: r274434

decl.c (grokdeclarator): Check here for typedef a function definition or a member function definition.

/cp
2019-08-14  Paolo Carlini  <paolo.carlini@oracle.com>

	* decl.c (grokdeclarator): Check here for typedef a function
	definition or a member function definition.
	(start_function): Adjust.
	(grokmethod): Likewise.

/testsuite
2019-08-14  Paolo Carlini  <paolo.carlini@oracle.com>

	* g++.dg/parse/typedef9.C: Test locations too.

From-SVN: r274433

decl.c (grokdeclarator): Check here for typedef a function definition or a member function definition.

/cp
2019-08-14  Paolo Carlini  <paolo.carlini@oracle.com>

	* decl.c (grokdeclarator): Check here for typedef a function
	definition or a member function definition.
	(start_function): Adjust.
	(grokmethod): Likewise.

/testsuite
2019-08-14  Paolo Carlini  <paolo.carlini@oracle.com>

	* g++.dg/parse/typedef9.C: Test locations too.

From-SVN: r274432

decl.c (grokdeclarator): Check here for typedef a function definition or a member function definition.

/cp
2019-08-14  Paolo Carlini  <paolo.carlini@oracle.com>

	* decl.c (grokdeclarator): Check here for typedef a function
	definition or a member function definition.
	(start_function): Adjust.
	(grokmethod): Likewise.

/testsuite
2019-08-14  Paolo Carlini  <paolo.carlini@oracle.com>

	* g++.dg/parse/typedef9.C: Test locations too.

From-SVN: r274431

2019-08-14  Martin Liska  <mliska@suse.cz>

	* LOCAL_PATCHES: Refresh based on what was committed.

From-SVN: r274430

The remaining uses of UNSPEC_MERGE_PTRUE were in integer comparison
patterns.  These aren't actually merging operations but zeroing ones,
although there's no practical difference when the predicate is a PTRUE.

All comparisons produced by expand are predicated on a PTRUE,
although we try to pattern-match a compare-and-AND as a predicated
comparison during combine.

Like previous patches, this one rearranges things in a way that works
better with the ACLE, where the initial predicate might or might not
be a PTRUE.  The new patterns use UNSPEC_PRED_Z to represent zeroing
predication, with a aarch64_sve_ptrue_flag to record whether the
predicate is all-true (as for UNSPEC_PTEST).

See the block comment in the patch for more details.

2019-08-14  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
	* config/aarch64/aarch64-protos.h (aarch64_sve_same_pred_for_ptest_p):
	Declare.
	* config/aarch64/aarch64.c (aarch64_sve_same_pred_for_ptest_p)
	(aarch64_sve_emit_int_cmp): New functions.
	(aarch64_convert_sve_data_to_pred): Use aarch64_sve_emit_int_cmp.
	(aarch64_sve_cmp_operand_p, aarch64_emit_sve_ptrue_op_cc): Delete.
	(aarch64_expand_sve_vec_cmp_int): Use aarch64_sve_emit_int_cmp.
	* config/aarch64/aarch64.md (UNSPEC_MERGE_PTRUE): Delete.
	(UNSPEC_PRED_Z): New unspec.
	(set_clobber_cc_nzc): Delete.
	* config/aarch64/aarch64-sve.md: Add a block comment about
	UNSPEC_PRED_Z.
	(*cmp<SVE_INT_CMP:cmp_op><mode>): Rename to...
	(@aarch64_pred_cmp<SVE_INT_CMP:cmp_op><mode>): ...this, replacing
	the old pattern with that name.  Use UNSPEC_PRED_Z instead of
	UNSPEC_MERGE_PTRUE.
	(*cmp<SVE_INT_CMP:cmp_op><mode>_cc): Use UNSPEC_PRED_Z instead of
	UNSPEC_MERGE_PTRUE.  Use aarch64_sve_same_pred_for_ptest_p to
	check for compatible predicates.
	(*cmp<cmp_op><SVE_INT_CMP:mode>_ptest): Likewise.
	(*cmp<cmp_op><mode>_and): Match a known-ptrue UNSPEC_PRED_Z instead
	of UNSPEC_MERGE_PTRUE.  Split into the new form of predicated
	comparisons above.

From-SVN: r274429

2019-08-14  Martin Liska  <mliska@suse.cz>

	* c-c++-common/asan/memcmp-1.c: There's a new function in the
	stack-trace on the top.  So shift expected output in stack
	trace.

From-SVN: r274428

2019-08-14  Martin Liska  <mliska@suse.cz>

	* asan/asan_globals.cpp (CheckODRViolationViaIndicator): Reapply
	patch from trunk.
	(CheckODRViolationViaPoisoning): Likewise.
	(RegisterGlobal): Likewise.
	* asan/asan_mapping.h: Likewise.
	* sanitizer_common/sanitizer_linux_libcdep.cpp (defined): Likewise.
	* sanitizer_common/sanitizer_mac.cpp (defined): Likewise.
	* sanitizer_common/sanitizer_platform_limits_linux.cpp (defined): Likewise.
	* sanitizer_common/sanitizer_platform_limits_posix.h (defined): Likewise.
	* sanitizer_common/sanitizer_stacktrace.cpp (GetCanonicFrame): Likewise.
	* ubsan/ubsan_handlers.cpp (__ubsan::__ubsan_handle_cfi_bad_icall): Likewise.
	(__ubsan::__ubsan_handle_cfi_bad_icall_abort): Likewise.
	* ubsan/ubsan_handlers.h (struct CFIBadIcallData): Likewise.
	(struct CFICheckFailData): Likewise.
	(RECOVERABLE): Likewise.
	* ubsan/ubsan_platform.h: Likewise.

From-SVN: r274427

2019-08-14  Martin Liska  <mliska@suse.cz>

	PR sanitizer/89832
	PR sanitizer/91325
	* All source files: Merge from upstream 368656.

From-SVN: r274426

The SVE patterns used an UNSPEC_MERGE_PTRUE unspec to attach a predicate
to an otherwise unpredicated integer arithmetic operation.  As its name
suggests, this was designed to be a wrapper used for merging instructions
in which the predicate is known to be a PTRUE.

This unspec dates from the very early days of the port and nothing has
ever taken advantage of the PTRUE guarantee for arithmetic (as opposed
to comparisons).  This patch replaces it with the less stringent
guarantee that:

(a) the values of inactive lanes don't matter and
(b) it is valid to make extra lanes active if there's a specific benefit

Doing this makes the patterns suitable for the ACLE _x functions, which
have the above semantics.

See the block comment in the patch for more details.

2019-08-14  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
	* config/aarch64/aarch64.md (UNSPEC_PRED_X): New unspec.
	* config/aarch64/aarch64-sve.md: Add a section describing it.
	(@aarch64_pred_mov<mode>, @aarch64_pred_mov<mode>)
	(<SVE_INT_UNARY:optab><mode>2, *<SVE_INT_UNARY:optab><mode>2)
	(aarch64_<su>abd<mode>_3, mul<SVE_I:mode>3, *mul<SVE_I:mode>3)
	(<su>mul<mode>3_highpart, *<su>mul<mode>3_highpart)
	(<SVE_INT_BINARY:optab><mode>3, *<SVE_INT_BINARY:optab><mode>3)
	(*bic<mode>3, v<ASHIFT:optab><mode>3, *v<ASHIFT:optab><mode>3)
	(<su><maxmin><mode>3, *<su><maxmin><mode>3, *madd<SVE_I:mode>)
	(*msub<SVE_I:mode>3, *aarch64_sve_rev64<mode>)
	(*aarch64_sve_rev32<mode>, *aarch64_sve_rev16vnx16qi): Use
	UNSPEC_PRED_X instead of UNSPEC_MERGE_PTRUE.
	* config/aarch64/aarch64-sve2.md (<u>avg<mode>3_floor)
	(<u>avg<mode>3_ceil, *<sur>h<addsub><mode>): Likewise.
	* config/aarch64/aarch64.c (aarch64_split_sve_subreg_move)
	(aarch64_evpc_rev_local): Update accordingly.

From-SVN: r274425

The SVE int<->float conversion patterns need to handle various
combinations of modes, making sure that the predicate mode is based
on the widest element size.  We did this using separate patterns for
conversions involving:

- HF (converting to/from [HSD]I, predicated based on the int operand)
- SF (converting to/from [SD]I, predicated based on the int operand)
- DF (converting to/from [SD]I, predicated based on the float operand)

This worked, and meant that there were no redundant patterns.  However,
the ACLE needs various new predicated patterns too, and having three
versions of each one seemed excessive.

This patch instead splits the patterns into two groups rather than three.
For conversions to integers:

- truncating (predicated based on the source type, DF->SI only)
- non-truncating (predicated based on the destination type)

For conversions from integers:

- extending (predicated based on the destination type, SI->DF only)
- non-extending (predicated based on the source type)

This means that we still don't create pattern names for the invalid
combinations DF<->HI and SF<->HI.  The downside is that we need to
use C conditions to exclude the SI<->DF case from the non-truncating/
non-extending patterns.  We therefore have two pattern names for SI<->DF,
but genconditions ensures that the invalid one always has the value
CODE_FOR_nothing.

2019-08-14  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
	* config/aarch64/iterators.md (VNx4SI_ONLY, VNx2DF_ONLY): New mode
	iterators.
	(SVE_BHSI, SVE_SDI): Tweak comment.
	(SVE_HSDI): Likewise.  Fix definition.
	(SVE_SDF): New mode iterator.
	(elem_bits): New mode attribute.
	(SVE_COND_FCVT): New int iterator.
	* config/aarch64/aarch64-sve.md
	(*<SVE_COND_ICVTF:optab>v16hsf<SVE_HSDI:mode>2)
	(*<SVE_COND_ICVTF:optab>vnx4sf<SVE_SDI:mode>2)
	(*<SVE_COND_ICVTF:optab>vnx2df<SVE_SDI:mode>2): Merge into...
	(*aarch64_sve_<SVE_COND_ICVTF:optab>_nontrunc<SVE_F:mode><SVE_HSDI:mode>)
	(*aarch64_sve_<SVE_COND_ICVTF:optab>_trunc<VNx2DF_ONLY:mode><VNx4SI_ONLY:mode>):
	...these new patterns.
	(*<SVE_COND_FCVTI:optab><SVE_HSDI:mode>vnx8hf2)
	(*<SVE_COND_FCVTI:optab><SVE_SDI:mode>vnx4sf2)
	(aarch64_sve_<SVE_COND_FCVTI:optab><SVE_SDI:mode>vnx2df2):
	Merge into...
	(*aarch64_sve_<SVE_COND_FCVTI:optab>_nonextend<SVE_HSDI:mode><SVE_F:mode>)
	(aarch64_sve_<SVE_COND_FCVTI:optab>_extend<VNx4SI_ONLY:mode><VNx2DF_ONLY:mode>):
	...these new patterns.
	(vec_unpack<su_optab>_float_<perm_hilo>_vnx4si): Update accordingly.
	(*trunc<Vwide><SVE_SDF:mode>2): Replace with...
	(*aarch64_sve_<SVE_COND_FCVT:optab>_trunc<SVE_SDF:mode><SVE_HSF:mode>):
	...this new pattern.
	(aarch64_sve_extend<SVE_HSDF:mode><Vwide>2): Replace with...
	(aarch64_sve_<SVE_COND_FCVT:optab>_nontrunc<SVE_HSF:mode><SVE_SDF:mode>):
	...this new pattern.
	(vec_unpacks_<perm_hilo>_<mode>): Update accordingly.

From-SVN: r274424

This patch changes the SVE FP<->FP and FP<->INT patterns so that
they use unspecs rather than rtx codes, continuing the series
to make the patterns work with predicates that might not be all-true.

2019-08-14  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
	* config/aarch64/aarch64.md (UNSPEC_FLOAT_CONVERT): Delete.
	* config/aarch64/iterators.md (UNSPEC_COND_FCVT, UNSPEC_COND_FCVTZS)
	(UNSPEC_COND_FCVTZU, UNSPEC_COND_SCVTF, UNSPEC_COND_UCVTF): New
	unspecs.
	(optab, su): Handle them.
	(SVE_COND_FCVTI, SVE_COND_ICVTF): New int iterators.
	* config/aarch64/aarch64-sve.md
	(<fix_trunc_optab><SVE_F:mode><v_int_equiv>2): Replace with...
	(<SVE_COND_FCVTI:optab><SVE_F:mode><v_int_equiv>2): ...this.
	(*<fix_trunc_optab>v16hsf<:SVE_HSDImode>2): Replace with...
	(*<SVE_COND_FCVTI:optab>v16hsf<SVE_F:mode>2): ...this.
	(*<fix_trunc_optab>vnx4sf<SVE_SDI:mode>2): Replace with...
	(*<SVE_COND_FCVTI:optab>vnx4sf<SVE_SDI:mode>2): ...this.
	(*<fix_trunc_optab>vnx2df<SVE_SDI:mode>2): Replace with...
	(*<SVE_COND_FCVTI:optab>vnx2df<SVE_SDI:mode>2): ...this.
	(vec_pack_<su>fix_trunc_vnx2df): Use SVE_COND_FCVTI instead of
	FIXUORS.
	(<FLOATUORS:optab><v_int_equiv><SVE_F:mode>2): Replace with...
	(<SVE_COND_ICVTF:optab><v_int_equiv><SVE_F:mode>2): ...this.
	(*<FLOATUORS:optab><SVE_HSDI:mode>vnx8hf2): Replace with...
	(*<SVE_COND_ICVTF:optab><SVE_HSDI:mode>vnx8hf2): ...this.
	(*<FLOATUORS:optab><SVE_SDI:mode>vnx4sf2): Replace with...
	(*<SVE_COND_ICVTF:optab><SVE_SDI:mode>vnx4sf2): ...this.
	(aarch64_sve_<FLOATUORS:optab><SVE_SDI:mode>vnx2df2): Replace with...
	(aarch64_sve_<SVE_COND_ICVTF:optab><SVE_SDI:mode>vnx2df2): ...this.
	(vec_unpack<su_optab>_float_<perm_hilo>_vnx4si): Pass a GP strictness
	operand to aarch64_sve_<SVE_COND_ICVTF:optab><SVE_SDI:mode>vnx2df2.
	(vec_pack_trunc_<SVE_HSF:Vwide>, *trunc<Vwide><SVE_HSF:mode>2)
	(aarch64_sve_extend<mode><Vwide>2): Use UNSPEC_COND_FCVT instead
	of UNSPEC_FLOAT_CONVERT.
	(vec_unpacks_<perm_hilo>_<mode>): Pass a GP strictness operand to
	aarch64_sve_extend<mode><Vwide>2.

From-SVN: r274423

2019-08-14  Richard Biener  <rguenther@suse.de>

	PR target/91154
	* config/i386/i386-features.c
	(dimode_scalar_chain::compute_convert_gain): Compute and dump
	individual instruction gain.  Fix reg-reg copy GRP cost.  Use
	ix86_cost->sse_op for vector instruction costs.

From-SVN: r274422

This patch rewrites the SVE FP comparisons so that they always use
unspecs and so that they have an additional operand to indicate
whether the predicate is known to be a PTRUE.  It's part of a series
that rewrites the SVE FP patterns so that they can cope with non-PTRUE
predicates.

2019-08-14  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
	* config/aarch64/iterators.md (UNSPEC_COND_FCMUO): New unspec.
	(cmp_op): Handle it.
	(SVE_COND_FP_CMP): Rename to...
	(SVE_COND_FP_CMP_I0): ...this.
	(SVE_FP_CMP): Remove.
	* config/aarch64/aarch64-sve.md
	(*fcm<SVE_FP_CMP:cmp_op><SVE_F:mode>): Replace with...
	(*fcm<SVE_COND_FP_CMP_I0:cmp_op><SVE_F:mode>): ...this new pattern,
	using unspecs to represent the comparison.
	(*fcmuo<SVE_F:mode>): Use UNSPEC_COND_FCMUO.
	(*fcm<cmp_op><mode>_and_combine, *fcmuo<mode>_and_combine): Update
	accordingly.
	* config/aarch64/aarch64.c (aarch64_emit_sve_ptrue_op): Delete.
	(aarch64_unspec_cond_code): Move after integer code.  Handle
	UNORDERED.
	(aarch64_emit_sve_predicated_cond): Replace with...
	(aarch64_emit_sve_fp_cond): ...this new function.
	(aarch64_emit_sve_or_conds): Replace with...
	(aarch64_emit_sve_or_fp_conds): ...this new function.
	(aarch64_emit_sve_inverted_cond): Replace with...
	(aarch64_emit_sve_invert_fp_cond): ...this new function.
	(aarch64_expand_sve_vec_cmp_float): Update accordingly.

From-SVN: r274421

We were missing vcond patterns that had HF comparisons and HI or HF data.

2019-08-14  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
	* config/aarch64/iterators.md (SVE_HSD): New mode iterator.
	(V_FP_EQUIV, v_fp_equiv): Handle VNx8HI and VNx8HF.
	* config/aarch64/aarch64-sve.md (vcond<mode><v_fp_equiv>): Use
	SVE_HSD instead of SVE_SD.

gcc/testsuite/
	* gcc.target/aarch64/sve/vcond_17.c: New test.
	* gcc.target/aarch64/sve/vcond_17_run.c: Likewise.

From-SVN: r274420

This patch uses a single expander for generic FP binary optabs
that map to predicated SVE instructions.  This makes them consistent
with the associated conditional optabs, which already work this way.

The patch also generalises the division handling to be one example
of a register-only predicated FP operation.  The ACLE patches will
add FMULX to the same category.

2019-08-14  Richard Sandiford  <richard.sandiford@arm.com>
	    Kugan Vivekanandarajah  <kugan.vivekanandarajah@linaro.org>

gcc/
	* config/aarch64/iterators.md (SVE_COND_FP_BINARY_REG): New int
	iterator.
	(sve_pred_fp_rhs1_operand, sve_pred_fp_rhs1_operand): New int
	attributes.
	* config/aarch64/aarch64-sve.md (add<SVE_F:mode>3, sub<SVE_F:mode>3)
	(mul<SVE_F:mode>3, div<SVE_F:mode>3)
	(<SVE_COND_FP_MAXMIN_PUBLIC:optab><SVE_F:mode>3): Merge into...
	(<SVE_COND_FP_BINARY:optab><SVE_F:mode>3): ...this new expander.
	(*div<SVE_F:mode>3): Generalize to...
	(*<SVE_COND_FP_BINARY:optab><SVE_F:mode>3): ...this.

Co-Authored-By: Kugan Vivekanandarajah <kuganv@linaro.org>

From-SVN: r274419

This patch makes the SVE unary, binary and ternary FP unspecs
take a new "GP strictness" operand that indicates whether the
predicate has to be taken literally, or whether it is valid to
make extra lanes active (up to and including using a PTRUE).

This again is laying the groundwork for the ACLE patterns,
in which the value can depend on the FP command-line flags.

At the moment it's only needed for addition, subtraction and
multiplication, which have unpredicated forms that can only
be used when operating on all lanes is safe.  But in future
it might be useful for optimising predicate usage.

The strict mode requires extra alternatives for addition,
subtraction and multiplication, but I've left those for the
main ACLE patch.

2019-08-14  Richard Sandiford  <richard.sandiford@arm.com>
	    Kugan Vivekanandarajah  <kugan.vivekanandarajah@linaro.org>

gcc/
	* config/aarch64/aarch64.md (SVE_RELAXED_GP, SVE_STRICT_GP): New
	constants.
	* config/aarch64/predicates.md (aarch64_sve_gp_strictness): New
	predicate.
	* config/aarch64/aarch64-protos.h (aarch64_sve_pred_dominates_p):
	Declare.
	* config/aarch64/aarch64.c (aarch64_sve_pred_dominates_p): New
	function.
	* config/aarch64/aarch64-sve.md: Add a block comment about the
	handling of predicated FP operations.
	(<SVE_COND_FP_UNARY:optab><SVE_F:mode>2, add<SVE_F:mode>3)
	(sub<SVE_F:mode>3, mul<SVE_F:mode>3, div<SVE_F:mode>3)
	(<SVE_COND_FP_MAXMIN_PUBLIC:optab><SVE_F:mode>3)
	(<SVE_COND_FP_MAXMIN_PUBLIC:maxmin_uns><SVE_F:mode>3)
	(<SVE_COND_FP_TERNARY:optab><SVE_F:mode>4): Add an SVE_RELAXED_GP
	operand.
	(cond_<SVE_COND_FP_BINARY:optab><SVE_F:mode>)
	(cond_<SVE_COND_FP_TERNARY:optab><SVE_F:mode>): Add an SVE_STRICT_GP
	operand.
	(*<SVE_COND_FP_UNARY:optab><SVE_F:mode>2)
	(*cond_<SVE_COND_FP_BINARY:optab><SVE_F:mode>_2)
	(*cond_<SVE_COND_FP_BINARY:optab><SVE_F:mode>_3)
	(*cond_<SVE_COND_FP_BINARY:optab><SVE_F:mode>_any)
	(*fabd<SVE_F:mode>3, *div<SVE_F:mode>3)
	(*<SVE_COND_FP_MAXMIN_PUBLIC:optab><SVE_F:mode>3)
	(*<SVE_COND_FP_TERNARY:optab><SVE_F:mode>4)
	(*cond_<SVE_COND_FP_TERNARY:optab><SVE_F:mode>_2)
	(*cond_<SVE_COND_FP_TERNARY:optab><SVE_F:mode>_4)
	(*cond_<SVE_COND_FP_TERNARY:optab><SVE_F:mode>_any): Match the
	strictness operands.  Use aarch64_sve_pred_dominates_p to check
	whether the predicate on the conditional operation is suitable
	for merging.  Split patterns into the canonical equal-predicate form.
	(*add<SVE_F:mode>3, *sub<SVE_F:mode>3, *mul<SVE_F:mode>3): Likewise.
	Restrict the unpredicated alternatives to SVE_RELAXED_GP.

Co-Authored-By: Kugan Vivekanandarajah <kuganv@linaro.org>

From-SVN: r274418

Another patch in the series to make the SVE FP patterns use unspecs,
so that they can accurately describe cases in which the predicate
isn't a PTRUE.

2019-08-14  Richard Sandiford  <richard.sandiford@arm.com>
	    Kugan Vivekanandarajah  <kugan.vivekanandarajah@linaro.org>

gcc/
	* config/aarch64/aarch64-sve.md (add<mode>3, *add<mode>3)
	(sub<mode>3, *sub<mode>3, *fabd<mode>3, mul<mode>3, *mul<mode>3)
	(div<mode>3, *div<mode>3): Use SVE_COND_FP_* unspecs instead of
	rtx codes.
	(cond_<optab><mode>, *cond_<optab><mode>_2, *cond_<optab><mode>_3)
	(*cond_<optab><mode>_any): Add the predicate to the SVE_COND_FP_*
	unspecs.

Co-Authored-By: Kugan Vivekanandarajah <kuganv@linaro.org>

From-SVN: r274417

This patch generalises the SVE BIC pattern so that it doesn't
rely on REG_EQUAL notes.  The danger with relying on the notes
is that an optimisation could for example replace the original
(not ...) note with an (unspec ... UNSPEC_MERGE_PTRUE) in which
the predicate is a constant.  That's a legitimate change and
could even be useful in some situations.

The patch also makes the operand order match the SVE operand order in
both the vector and predicate BIC patterns, which makes things easier
for the ACLE.

2019-08-14  Richard Sandiford  <richard.sandiford@arm.com>
	    Kugan Vivekanandarajah  <kugan.vivekanandarajah@linaro.org>

gcc/
	* config/aarch64/aarch64-sve.md (bic<mode>3): Rename to...
	(*bic<SVE_I:mode>3): ...this.  Match the form that an SVE inverse
	actually has, rather than relying on REG_EQUAL notes.
	Make the insn operand order match the SVE operand order.
	(*<nlogical><PRED_ALL:mode>3): Make the insn operand order match
	the SVE operand order.

Co-Authored-By: Kugan Vivekanandarajah <kuganv@linaro.org>

From-SVN: r274416

This patch makes sure that we build all SVE predicate constants as
VNx16BI before RA, to encourage similar constants to be reused
between modes.  This is also useful for the ACLE, where the single
predicate type svbool_t is always a VNx16BI.

Also, and again to encourage reuse, the patch makes us use a .B PTRUE
for all ptrue-predicated operations, rather than (for example) using
a .S PTRUE for 32-bit operations and a .D PTRUE for 64-bit operations.

The only current case in which a .H, .S or .D operation needs to be
predicated by a "strict" .H/.S/.D PTRUE is the PTEST in a conditional
branch, which an earlier patch fixed to use an appropriate VNx16BI
constant.

2019-08-14  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
	* config/aarch64/aarch64.c (aarch64_target_reg): New function.
	(aarch64_emit_set_immediate): Likewise.
	(aarch64_ptrue_reg): Build a VNx16BI constant and then bitcast it.
	(aarch64_pfalse_reg): Likewise.
	(aarch64_convert_sve_data_to_pred): New function.
	(aarch64_sve_move_pred_via_while): Take an optional target register
	and the required register mode.
	(aarch64_expand_sve_const_pred_1): New function.
	(aarch64_expand_sve_const_pred): Likewise.
	(aarch64_expand_mov_immediate): Build an all-true predicate
	if the significant bits of the immediate are all true.  Use
	aarch64_expand_sve_const_pred for all compile-time predicate constants.
	(aarch64_mov_operand_p): Force predicate constants to be VNx16BI
	before register allocation.
	* config/aarch64/aarch64-sve.md (*vec_duplicate<mode>_reg): Use
	a VNx16BI PTRUE when splitting the memory alternative.
	(vec_duplicate<mode>): Update accordingly.
	(*pred_cmp<cmp_op><mode>): Rename to...
	(@aarch64_pred_cmp<cmp_op><mode>): ...this.

gcc/testsuite/
	* gcc.target/aarch64/sve/spill_4.c: Expect all ptrues to be .Bs.
	* gcc.target/aarch64/sve/single_1.c: Likewise.
	* gcc.target/aarch64/sve/single_2.c: Likewise.
	* gcc.target/aarch64/sve/single_3.c: Likewise.
	* gcc.target/aarch64/sve/single_4.c: Likewise.

From-SVN: r274415

This patch reworks the rtl representation of the SVE PTEST operation
so that:

- the governing predicate is always VNx16BI (and so all bits are defined)

- it is still possible to pattern-match the governing predicate in the
  mode that it had previously

- a new hint operand says whether the governing predicate is known to be
  all true for the element size of interest, rather than this being part
  of the unspec name.

These changes make it easier to handle more flag-setting instructions
as part of the ACLE work.

See the comment in aarch64-sve.md for more details.

2019-08-14  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
	* config/aarch64/aarch64-protos.h (aarch64_ptrue_all): Declare.
	* config/aarch64/aarch64.c (aarch64_ptrue_all): New function.
	* config/aarch64/aarch64.md (UNSPEC_PTEST_PTRUE): Delete.
	(UNSPEC_PTEST): New unspec.
	(SVE_MAYBE_NOT_PTRUE, SVE_KNOWN_PTRUE): New constants.
	* config/aarch64/iterators.md (data_bytes): New mode attribute.
	* config/aarch64/predicates.md (aarch64_sve_ptrue_flag): New predicate.
	* config/aarch64/aarch64-sve.md: Add a new section describing the
	handling of UNSPEC_PTEST.
	(pred_<LOGICAL:optab><PRED_ALL:mode>3): Rename to...
	(@aarch64_pred_<LOGICAL:optab><PRED_ALL:mode>_z): ...this.
	(ptest_ptrue<mode>): Replace with...
	(aarch64_ptest<mode>): ...this new pattern.
	(cbranch<mode>4): Update after above changes.
	(*<LOGICAL:optab><PRED_ALL:mode>3_cc): Use UNSPEC_PTEST instead of
	UNSPEC_PTEST_PTRUE.
	(*cmp<SVE_INT_CMP:cmp_op><SVE_I:mode>_cc): Likewise.
	(*cmp<SVE_INT_CMP:cmp_op><SVE_I:mode>_ptest): Likewise.
	(*while_ult<GPI:mode><PRED_ALL:mode>_cc): Likewise.

From-SVN: r274414

2019-08-13  Steven G. Kargl  <kargl@gcc.gnu.org>

	PR fortran/87991
	* resolve.c (check_data_variable): data-stmt-object with pointer
	attribute requires a data-stmt-value with the target attribute.
 
2019-08-13  Steven G. Kargl  <kargl@gcc.gnu.org>

	PR fortran/87991
	* gfortran.dg/pr87991.f90: New test.

From-SVN: r274412

In LTO mode, if static library and dynamic library contains same
function and both libraries are passed as arguments, linker will link
the function in dynamic library no matter the sequence.  This patch
will output LTO symbol node as UNDEF if BUILT_IN_NORMAL function FNDECL
is a math function, then the function in static library will be linked
first if its sequence is ahead of the dynamic library.

gcc/ChangeLog

2019-08-14  Xiong Hu Luo  <luoxhu@linux.ibm.com>

	PR lto/91287
	* builtins.c (builtin_with_linkage_p): New function.
	* builtins.h (builtin_with_linkage_p): New function.
	* symtab.c (write_symbol): Remove redundant assert.
	* lto-streamer-out.c (symtab_node::output_to_lto_symbol_table_p):
	Remove FIXME and use builtin_with_linkage_p.

From-SVN: r274411