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riscv-gcc-1
Commit 99361551 by Richard Sandiford Committed by Richard Sandiford
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[AArch64] Use unspecs for SVE conversions involving floats 

This patch changes the SVE FP<->FP and FP<->INT patterns so that
they use unspecs rather than rtx codes, continuing the series
to make the patterns work with predicates that might not be all-true.

2019-08-14  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
	* config/aarch64/aarch64.md (UNSPEC_FLOAT_CONVERT): Delete.
	* config/aarch64/iterators.md (UNSPEC_COND_FCVT, UNSPEC_COND_FCVTZS)
	(UNSPEC_COND_FCVTZU, UNSPEC_COND_SCVTF, UNSPEC_COND_UCVTF): New
	unspecs.
	(optab, su): Handle them.
	(SVE_COND_FCVTI, SVE_COND_ICVTF): New int iterators.
	* config/aarch64/aarch64-sve.md
	(<fix_trunc_optab><SVE_F:mode><v_int_equiv>2): Replace with...
	(<SVE_COND_FCVTI:optab><SVE_F:mode><v_int_equiv>2): ...this.
	(*<fix_trunc_optab>v16hsf<:SVE_HSDImode>2): Replace with...
	(*<SVE_COND_FCVTI:optab>v16hsf<SVE_F:mode>2): ...this.
	(*<fix_trunc_optab>vnx4sf<SVE_SDI:mode>2): Replace with...
	(*<SVE_COND_FCVTI:optab>vnx4sf<SVE_SDI:mode>2): ...this.
	(*<fix_trunc_optab>vnx2df<SVE_SDI:mode>2): Replace with...
	(*<SVE_COND_FCVTI:optab>vnx2df<SVE_SDI:mode>2): ...this.
	(vec_pack_<su>fix_trunc_vnx2df): Use SVE_COND_FCVTI instead of
	FIXUORS.
	(<FLOATUORS:optab><v_int_equiv><SVE_F:mode>2): Replace with...
	(<SVE_COND_ICVTF:optab><v_int_equiv><SVE_F:mode>2): ...this.
	(*<FLOATUORS:optab><SVE_HSDI:mode>vnx8hf2): Replace with...
	(*<SVE_COND_ICVTF:optab><SVE_HSDI:mode>vnx8hf2): ...this.
	(*<FLOATUORS:optab><SVE_SDI:mode>vnx4sf2): Replace with...
	(*<SVE_COND_ICVTF:optab><SVE_SDI:mode>vnx4sf2): ...this.
	(aarch64_sve_<FLOATUORS:optab><SVE_SDI:mode>vnx2df2): Replace with...
	(aarch64_sve_<SVE_COND_ICVTF:optab><SVE_SDI:mode>vnx2df2): ...this.
	(vec_unpack<su_optab>_float_<perm_hilo>_vnx4si): Pass a GP strictness
	operand to aarch64_sve_<SVE_COND_ICVTF:optab><SVE_SDI:mode>vnx2df2.
	(vec_pack_trunc_<SVE_HSF:Vwide>, *trunc<Vwide><SVE_HSF:mode>2)
	(aarch64_sve_extend<mode><Vwide>2): Use UNSPEC_COND_FCVT instead
	of UNSPEC_FLOAT_CONVERT.
	(vec_unpacks_<perm_hilo>_<mode>): Pass a GP strictness operand to
	aarch64_sve_extend<mode><Vwide>2.

From-SVN: r274423
parent c6521daa
Showing with 109 additions and 56 deletions
gcc/ChangeLog
2019-08-14 Richard Sandiford <richard.sandiford@arm.com>
* config/aarch64/aarch64.md (UNSPEC_FLOAT_CONVERT): Delete.
* config/aarch64/iterators.md (UNSPEC_COND_FCVT, UNSPEC_COND_FCVTZS)
(UNSPEC_COND_FCVTZU, UNSPEC_COND_SCVTF, UNSPEC_COND_UCVTF): New
unspecs.
(optab, su): Handle them.
(SVE_COND_FCVTI, SVE_COND_ICVTF): New int iterators.
* config/aarch64/aarch64-sve.md
(<fix_trunc_optab><SVE_F:mode><v_int_equiv>2): Replace with...
(<SVE_COND_FCVTI:optab><SVE_F:mode><v_int_equiv>2): ...this.
(*<fix_trunc_optab>v16hsf<:SVE_HSDImode>2): Replace with...
(*<SVE_COND_FCVTI:optab>v16hsf<SVE_F:mode>2): ...this.
(*<fix_trunc_optab>vnx4sf<SVE_SDI:mode>2): Replace with...
(*<SVE_COND_FCVTI:optab>vnx4sf<SVE_SDI:mode>2): ...this.
(*<fix_trunc_optab>vnx2df<SVE_SDI:mode>2): Replace with...
(*<SVE_COND_FCVTI:optab>vnx2df<SVE_SDI:mode>2): ...this.
(vec_pack_<su>fix_trunc_vnx2df): Use SVE_COND_FCVTI instead of
FIXUORS.
(<FLOATUORS:optab><v_int_equiv><SVE_F:mode>2): Replace with...
(<SVE_COND_ICVTF:optab><v_int_equiv><SVE_F:mode>2): ...this.
(*<FLOATUORS:optab><SVE_HSDI:mode>vnx8hf2): Replace with...
(*<SVE_COND_ICVTF:optab><SVE_HSDI:mode>vnx8hf2): ...this.
(*<FLOATUORS:optab><SVE_SDI:mode>vnx4sf2): Replace with...
(*<SVE_COND_ICVTF:optab><SVE_SDI:mode>vnx4sf2): ...this.
(aarch64_sve_<FLOATUORS:optab><SVE_SDI:mode>vnx2df2): Replace with...
(aarch64_sve_<SVE_COND_ICVTF:optab><SVE_SDI:mode>vnx2df2): ...this.
(vec_unpack<su_optab>_float_<perm_hilo>_vnx4si): Pass a GP strictness
operand to aarch64_sve_<SVE_COND_ICVTF:optab><SVE_SDI:mode>vnx2df2.
(vec_pack_trunc_<SVE_HSF:Vwide>, *trunc<Vwide><SVE_HSF:mode>2)
(aarch64_sve_extend<mode><Vwide>2): Use UNSPEC_COND_FCVT instead
of UNSPEC_FLOAT_CONVERT.
(vec_unpacks_<perm_hilo>_<mode>): Pass a GP strictness operand to
aarch64_sve_extend<mode><Vwide>2.
2019-08-14 Richard Biener <rguenther@suse.de> 2019-08-14 Richard Biener <rguenther@suse.de>
PR target/91154 PR target/91154
......
gcc/config/aarch64/aarch64-sve.md
...@@ -3643,13 +3643,13 @@ ...@@ -3643,13 +3643,13 @@
;; Unpredicated conversion of floats to integers of the same size (HF to HI, ;; Unpredicated conversion of floats to integers of the same size (HF to HI,
;; SF to SI or DF to DI). ;; SF to SI or DF to DI).
(define_expand "<fix_trunc_optab><mode><v_int_equiv>2" (define_expand "<optab><mode><v_int_equiv>2"
[(set (match_operand:<V_INT_EQUIV> 0 "register_operand") [(set (match_operand:<V_INT_EQUIV> 0 "register_operand")
(unspec:<V_INT_EQUIV> (unspec:<V_INT_EQUIV>
[(match_dup 2) [(match_dup 2)
(FIXUORS:<V_INT_EQUIV> (const_int SVE_RELAXED_GP)
(match_operand:SVE_F 1 "register_operand"))] (match_operand:SVE_F 1 "register_operand")]
UNSPEC_MERGE_PTRUE))] SVE_COND_FCVTI))]
"TARGET_SVE" "TARGET_SVE"
{ {
operands[2] = aarch64_ptrue_reg (<VPRED>mode); operands[2] = aarch64_ptrue_reg (<VPRED>mode);
...@@ -3657,37 +3657,37 @@ ...@@ -3657,37 +3657,37 @@
) )
;; Conversion of SF to DI, SI or HI, predicated with a PTRUE. ;; Conversion of SF to DI, SI or HI, predicated with a PTRUE.
(define_insn "*<fix_trunc_optab>v16hsf<mode>2" (define_insn "*<optab>v16hsf<mode>2"
[(set (match_operand:SVE_HSDI 0 "register_operand" "=w") [(set (match_operand:SVE_HSDI 0 "register_operand" "=w")
(unspec:SVE_HSDI (unspec:SVE_HSDI
[(match_operand:<VPRED> 1 "register_operand" "Upl") [(match_operand:<VPRED> 1 "register_operand" "Upl")
(FIXUORS:SVE_HSDI (match_operand:SI 3 "aarch64_sve_gp_strictness")
(match_operand:VNx8HF 2 "register_operand" "w"))] (match_operand:VNx8HF 2 "register_operand" "w")]
UNSPEC_MERGE_PTRUE))] SVE_COND_FCVTI))]
"TARGET_SVE" "TARGET_SVE"
"fcvtz<su>\t%0.<Vetype>, %1/m, %2.h" "fcvtz<su>\t%0.<Vetype>, %1/m, %2.h"
) )
;; Conversion of SF to DI or SI, predicated with a PTRUE. ;; Conversion of SF to DI or SI, predicated with a PTRUE.
(define_insn "*<fix_trunc_optab>vnx4sf<mode>2" (define_insn "*<optab>vnx4sf<mode>2"
[(set (match_operand:SVE_SDI 0 "register_operand" "=w") [(set (match_operand:SVE_SDI 0 "register_operand" "=w")
(unspec:SVE_SDI (unspec:SVE_SDI
[(match_operand:<VPRED> 1 "register_operand" "Upl") [(match_operand:<VPRED> 1 "register_operand" "Upl")
(FIXUORS:SVE_SDI (match_operand:SI 3 "aarch64_sve_gp_strictness")
(match_operand:VNx4SF 2 "register_operand" "w"))] (match_operand:VNx4SF 2 "register_operand" "w")]
UNSPEC_MERGE_PTRUE))] SVE_COND_FCVTI))]
"TARGET_SVE" "TARGET_SVE"
"fcvtz<su>\t%0.<Vetype>, %1/m, %2.s" "fcvtz<su>\t%0.<Vetype>, %1/m, %2.s"
) )
;; Conversion of DF to DI or SI, predicated with a PTRUE. ;; Conversion of DF to DI or SI, predicated with a PTRUE.
(define_insn "*<fix_trunc_optab>vnx2df<mode>2" (define_insn "*<optab>vnx2df<mode>2"
[(set (match_operand:SVE_SDI 0 "register_operand" "=w") [(set (match_operand:SVE_SDI 0 "register_operand" "=w")
(unspec:SVE_SDI (unspec:SVE_SDI
[(match_operand:VNx2BI 1 "register_operand" "Upl") [(match_operand:VNx2BI 1 "register_operand" "Upl")
(FIXUORS:SVE_SDI (match_operand:SI 3 "aarch64_sve_gp_strictness")
(match_operand:VNx2DF 2 "register_operand" "w"))] (match_operand:VNx2DF 2 "register_operand" "w")]
UNSPEC_MERGE_PTRUE))] SVE_COND_FCVTI))]
"TARGET_SVE" "TARGET_SVE"
"fcvtz<su>\t%0.<Vetype>, %1/m, %2.d" "fcvtz<su>\t%0.<Vetype>, %1/m, %2.d"
) )
...@@ -3703,13 +3703,15 @@ ...@@ -3703,13 +3703,15 @@
[(set (match_dup 4) [(set (match_dup 4)
(unspec:VNx4SI (unspec:VNx4SI
[(match_dup 3) [(match_dup 3)
(FIXUORS:VNx4SI (match_operand:VNx2DF 1 "register_operand"))] (const_int SVE_RELAXED_GP)
UNSPEC_MERGE_PTRUE)) (match_operand:VNx2DF 1 "register_operand")]
SVE_COND_FCVTI))
(set (match_dup 5) (set (match_dup 5)
(unspec:VNx4SI (unspec:VNx4SI
[(match_dup 3) [(match_dup 3)
(FIXUORS:VNx4SI (match_operand:VNx2DF 2 "register_operand"))] (const_int SVE_RELAXED_GP)
UNSPEC_MERGE_PTRUE)) (match_operand:VNx2DF 2 "register_operand")]
SVE_COND_FCVTI))
(set (match_operand:VNx4SI 0 "register_operand") (set (match_operand:VNx4SI 0 "register_operand")
(unspec:VNx4SI [(match_dup 4) (match_dup 5)] UNSPEC_UZP1))] (unspec:VNx4SI [(match_dup 4) (match_dup 5)] UNSPEC_UZP1))]
"TARGET_SVE" "TARGET_SVE"
...@@ -3740,9 +3742,9 @@ ...@@ -3740,9 +3742,9 @@
[(set (match_operand:SVE_F 0 "register_operand") [(set (match_operand:SVE_F 0 "register_operand")
(unspec:SVE_F (unspec:SVE_F
[(match_dup 2) [(match_dup 2)
(FLOATUORS:SVE_F (const_int SVE_RELAXED_GP)
(match_operand:<V_INT_EQUIV> 1 "register_operand"))] (match_operand:<V_INT_EQUIV> 1 "register_operand")]
UNSPEC_MERGE_PTRUE))] SVE_COND_ICVTF))]
"TARGET_SVE" "TARGET_SVE"
{ {
operands[2] = aarch64_ptrue_reg (<VPRED>mode); operands[2] = aarch64_ptrue_reg (<VPRED>mode);
...@@ -3755,11 +3757,11 @@ ...@@ -3755,11 +3757,11 @@
[(set (match_operand:VNx8HF 0 "register_operand" "=w") [(set (match_operand:VNx8HF 0 "register_operand" "=w")
(unspec:VNx8HF (unspec:VNx8HF
[(match_operand:<VPRED> 1 "register_operand" "Upl") [(match_operand:<VPRED> 1 "register_operand" "Upl")
(FLOATUORS:VNx8HF (match_operand:SI 3 "aarch64_sve_gp_strictness")
(match_operand:SVE_HSDI 2 "register_operand" "w"))] (match_operand:SVE_HSDI 2 "register_operand" "w")]
UNSPEC_MERGE_PTRUE))] SVE_COND_ICVTF))]
"TARGET_SVE" "TARGET_SVE"
"<su_optab>cvtf\t%0.h, %1/m, %2.<Vetype>" "<su>cvtf\t%0.h, %1/m, %2.<Vetype>"
) )
;; Conversion of DI or SI to the same number of SFs, predicated with a PTRUE. ;; Conversion of DI or SI to the same number of SFs, predicated with a PTRUE.
...@@ -3767,11 +3769,11 @@ ...@@ -3767,11 +3769,11 @@
[(set (match_operand:VNx4SF 0 "register_operand" "=w") [(set (match_operand:VNx4SF 0 "register_operand" "=w")
(unspec:VNx4SF (unspec:VNx4SF
[(match_operand:<VPRED> 1 "register_operand" "Upl") [(match_operand:<VPRED> 1 "register_operand" "Upl")
(FLOATUORS:VNx4SF (match_operand:SI 3 "aarch64_sve_gp_strictness")
(match_operand:SVE_SDI 2 "register_operand" "w"))] (match_operand:SVE_SDI 2 "register_operand" "w")]
UNSPEC_MERGE_PTRUE))] SVE_COND_ICVTF))]
"TARGET_SVE" "TARGET_SVE"
"<su_optab>cvtf\t%0.s, %1/m, %2.<Vetype>" "<su>cvtf\t%0.s, %1/m, %2.<Vetype>"
) )
;; Conversion of DI or SI to DF, predicated with a PTRUE. ;; Conversion of DI or SI to DF, predicated with a PTRUE.
...@@ -3779,11 +3781,11 @@ ...@@ -3779,11 +3781,11 @@
[(set (match_operand:VNx2DF 0 "register_operand" "=w") [(set (match_operand:VNx2DF 0 "register_operand" "=w")
(unspec:VNx2DF (unspec:VNx2DF
[(match_operand:VNx2BI 1 "register_operand" "Upl") [(match_operand:VNx2BI 1 "register_operand" "Upl")
(FLOATUORS:VNx2DF (match_operand:SI 3 "aarch64_sve_gp_strictness")
(match_operand:SVE_SDI 2 "register_operand" "w"))] (match_operand:SVE_SDI 2 "register_operand" "w")]
UNSPEC_MERGE_PTRUE))] SVE_COND_ICVTF))]
"TARGET_SVE" "TARGET_SVE"
"<su_optab>cvtf\t%0.d, %1/m, %2.<Vetype>" "<su>cvtf\t%0.d, %1/m, %2.<Vetype>"
) )
;; ------------------------------------------------------------------------- ;; -------------------------------------------------------------------------
...@@ -3818,8 +3820,9 @@ ...@@ -3818,8 +3820,9 @@
: gen_aarch64_sve_zip1vnx4si) : gen_aarch64_sve_zip1vnx4si)
(temp, operands[1], operands[1])); (temp, operands[1], operands[1]));
rtx ptrue = aarch64_ptrue_reg (VNx2BImode); rtx ptrue = aarch64_ptrue_reg (VNx2BImode);
emit_insn (gen_aarch64_sve_<FLOATUORS:optab>vnx4sivnx2df2 (operands[0], rtx strictness = gen_int_mode (SVE_RELAXED_GP, SImode);
ptrue, temp)); emit_insn (gen_aarch64_sve_<FLOATUORS:optab>vnx4sivnx2df2
(operands[0], ptrue, temp, strictness));
DONE; DONE;
} }
) )
...@@ -3837,15 +3840,15 @@ ...@@ -3837,15 +3840,15 @@
[(set (match_dup 4) [(set (match_dup 4)
(unspec:SVE_HSF (unspec:SVE_HSF
[(match_dup 3) [(match_dup 3)
(unspec:SVE_HSF [(match_operand:<VWIDE> 1 "register_operand")] (const_int SVE_RELAXED_GP)
UNSPEC_FLOAT_CONVERT)] (match_operand:<VWIDE> 1 "register_operand")]
UNSPEC_MERGE_PTRUE)) UNSPEC_COND_FCVT))
(set (match_dup 5) (set (match_dup 5)
(unspec:SVE_HSF (unspec:SVE_HSF
[(match_dup 3) [(match_dup 3)
(unspec:SVE_HSF [(match_operand:<VWIDE> 2 "register_operand")] (const_int SVE_RELAXED_GP)
UNSPEC_FLOAT_CONVERT)] (match_operand:<VWIDE> 2 "register_operand")]
UNSPEC_MERGE_PTRUE)) UNSPEC_COND_FCVT))
(set (match_operand:SVE_HSF 0 "register_operand") (set (match_operand:SVE_HSF 0 "register_operand")
(unspec:SVE_HSF [(match_dup 4) (match_dup 5)] UNSPEC_UZP1))] (unspec:SVE_HSF [(match_dup 4) (match_dup 5)] UNSPEC_UZP1))]
"TARGET_SVE" "TARGET_SVE"
...@@ -3862,10 +3865,9 @@ ...@@ -3862,10 +3865,9 @@
[(set (match_operand:SVE_HSF 0 "register_operand" "=w") [(set (match_operand:SVE_HSF 0 "register_operand" "=w")
(unspec:SVE_HSF (unspec:SVE_HSF
[(match_operand:<VWIDE_PRED> 1 "register_operand" "Upl") [(match_operand:<VWIDE_PRED> 1 "register_operand" "Upl")
(unspec:SVE_HSF (match_operand:SI 3 "aarch64_sve_gp_strictness")
[(match_operand:<VWIDE> 2 "register_operand" "w")] (match_operand:<VWIDE> 2 "register_operand" "w")]
UNSPEC_FLOAT_CONVERT)] UNSPEC_COND_FCVT))]
UNSPEC_MERGE_PTRUE))]
"TARGET_SVE" "TARGET_SVE"
"fcvt\t%0.<Vetype>, %1/m, %2.<Vewtype>" "fcvt\t%0.<Vetype>, %1/m, %2.<Vewtype>"
) )
...@@ -3896,8 +3898,9 @@ ...@@ -3896,8 +3898,9 @@
: gen_aarch64_sve_zip1<mode>) : gen_aarch64_sve_zip1<mode>)
(temp, operands[1], operands[1])); (temp, operands[1], operands[1]));
rtx ptrue = aarch64_ptrue_reg (<VWIDE_PRED>mode); rtx ptrue = aarch64_ptrue_reg (<VWIDE_PRED>mode);
emit_insn (gen_aarch64_sve_extend<mode><Vwide>2 (operands[0], rtx strictness = gen_int_mode (SVE_RELAXED_GP, SImode);
ptrue, temp)); emit_insn (gen_aarch64_sve_extend<mode><Vwide>2
(operands[0], ptrue, temp, strictness));
DONE; DONE;
} }
) )
...@@ -3908,10 +3911,9 @@ ...@@ -3908,10 +3911,9 @@
[(set (match_operand:<VWIDE> 0 "register_operand" "=w") [(set (match_operand:<VWIDE> 0 "register_operand" "=w")
(unspec:<VWIDE> (unspec:<VWIDE>
[(match_operand:<VWIDE_PRED> 1 "register_operand" "Upl") [(match_operand:<VWIDE_PRED> 1 "register_operand" "Upl")
(unspec:<VWIDE> (match_operand:SI 3 "aarch64_sve_gp_strictness")
[(match_operand:SVE_HSF 2 "register_operand" "w")] (match_operand:SVE_HSF 2 "register_operand" "w")]
UNSPEC_FLOAT_CONVERT)] UNSPEC_COND_FCVT))]
UNSPEC_MERGE_PTRUE))]
"TARGET_SVE" "TARGET_SVE"
"fcvt\t%0.<Vewtype>, %1/m, %2.<Vetype>" "fcvt\t%0.<Vewtype>, %1/m, %2.<Vetype>"
) )
......
gcc/config/aarch64/aarch64.md
...@@ -226,7 +226,6 @@ ...@@ -226,7 +226,6 @@
UNSPEC_UNPACKSLO UNSPEC_UNPACKSLO
UNSPEC_UNPACKULO UNSPEC_UNPACKULO
UNSPEC_PACK UNSPEC_PACK
UNSPEC_FLOAT_CONVERT
UNSPEC_WHILE_LO UNSPEC_WHILE_LO
UNSPEC_LDN UNSPEC_LDN
UNSPEC_STN UNSPEC_STN
......
gcc/config/aarch64/iterators.md
...@@ -480,6 +480,9 @@ ...@@ -480,6 +480,9 @@
UNSPEC_COND_FCMLT ; Used in aarch64-sve.md. UNSPEC_COND_FCMLT ; Used in aarch64-sve.md.
UNSPEC_COND_FCMNE ; Used in aarch64-sve.md. UNSPEC_COND_FCMNE ; Used in aarch64-sve.md.
UNSPEC_COND_FCMUO ; Used in aarch64-sve.md. UNSPEC_COND_FCMUO ; Used in aarch64-sve.md.
UNSPEC_COND_FCVT ; Used in aarch64-sve.md.
UNSPEC_COND_FCVTZS ; Used in aarch64-sve.md.
UNSPEC_COND_FCVTZU ; Used in aarch64-sve.md.
UNSPEC_COND_FDIV ; Used in aarch64-sve.md. UNSPEC_COND_FDIV ; Used in aarch64-sve.md.
UNSPEC_COND_FMAXNM ; Used in aarch64-sve.md. UNSPEC_COND_FMAXNM ; Used in aarch64-sve.md.
UNSPEC_COND_FMINNM ; Used in aarch64-sve.md. UNSPEC_COND_FMINNM ; Used in aarch64-sve.md.
...@@ -498,6 +501,8 @@ ...@@ -498,6 +501,8 @@
UNSPEC_COND_FRINTZ ; Used in aarch64-sve.md. UNSPEC_COND_FRINTZ ; Used in aarch64-sve.md.
UNSPEC_COND_FSQRT ; Used in aarch64-sve.md. UNSPEC_COND_FSQRT ; Used in aarch64-sve.md.
UNSPEC_COND_FSUB ; Used in aarch64-sve.md. UNSPEC_COND_FSUB ; Used in aarch64-sve.md.
UNSPEC_COND_SCVTF ; Used in aarch64-sve.md.
UNSPEC_COND_UCVTF ; Used in aarch64-sve.md.
UNSPEC_LASTB ; Used in aarch64-sve.md. UNSPEC_LASTB ; Used in aarch64-sve.md.
UNSPEC_FCADD90 ; Used in aarch64-simd.md. UNSPEC_FCADD90 ; Used in aarch64-simd.md.
UNSPEC_FCADD270 ; Used in aarch64-simd.md. UNSPEC_FCADD270 ; Used in aarch64-simd.md.
...@@ -1642,6 +1647,9 @@ ...@@ -1642,6 +1647,9 @@
UNSPEC_COND_FRINTZ UNSPEC_COND_FRINTZ
UNSPEC_COND_FSQRT]) UNSPEC_COND_FSQRT])
(define_int_iterator SVE_COND_FCVTI [UNSPEC_COND_FCVTZS UNSPEC_COND_FCVTZU])
(define_int_iterator SVE_COND_ICVTF [UNSPEC_COND_SCVTF UNSPEC_COND_UCVTF])
(define_int_iterator SVE_COND_FP_BINARY [UNSPEC_COND_FADD (define_int_iterator SVE_COND_FP_BINARY [UNSPEC_COND_FADD
UNSPEC_COND_FDIV UNSPEC_COND_FDIV
UNSPEC_COND_FMAXNM UNSPEC_COND_FMAXNM
...@@ -1715,6 +1723,9 @@ ...@@ -1715,6 +1723,9 @@
(UNSPEC_FMINV "smin_nan") (UNSPEC_FMINV "smin_nan")
(UNSPEC_COND_FABS "abs") (UNSPEC_COND_FABS "abs")
(UNSPEC_COND_FADD "add") (UNSPEC_COND_FADD "add")
(UNSPEC_COND_FCVT "fcvt")
(UNSPEC_COND_FCVTZS "fix_trunc")
(UNSPEC_COND_FCVTZU "fixuns_trunc")
(UNSPEC_COND_FDIV "div") (UNSPEC_COND_FDIV "div")
(UNSPEC_COND_FMAXNM "smax") (UNSPEC_COND_FMAXNM "smax")
(UNSPEC_COND_FMINNM "smin") (UNSPEC_COND_FMINNM "smin")
...@@ -1732,7 +1743,9 @@ ...@@ -1732,7 +1743,9 @@
(UNSPEC_COND_FRINTX "rint") (UNSPEC_COND_FRINTX "rint")
(UNSPEC_COND_FRINTZ "btrunc") (UNSPEC_COND_FRINTZ "btrunc")
(UNSPEC_COND_FSQRT "sqrt") (UNSPEC_COND_FSQRT "sqrt")
(UNSPEC_COND_FSUB "sub")]) (UNSPEC_COND_FSUB "sub")
(UNSPEC_COND_SCVTF "float")
(UNSPEC_COND_UCVTF "floatuns")])
(define_int_attr maxmin_uns [(UNSPEC_UMAXV "umax") (define_int_attr maxmin_uns [(UNSPEC_UMAXV "umax")
(UNSPEC_UMINV "umin") (UNSPEC_UMINV "umin")
...@@ -1773,7 +1786,11 @@ ...@@ -1773,7 +1786,11 @@
(UNSPEC_UNPACKSLO "s") (UNSPEC_UNPACKSLO "s")
(UNSPEC_UNPACKULO "u") (UNSPEC_UNPACKULO "u")
(UNSPEC_SMUL_HIGHPART "s") (UNSPEC_SMUL_HIGHPART "s")
(UNSPEC_UMUL_HIGHPART "u")]) (UNSPEC_UMUL_HIGHPART "u")
(UNSPEC_COND_FCVTZS "s")
(UNSPEC_COND_FCVTZU "u")
(UNSPEC_COND_SCVTF "s")
(UNSPEC_COND_UCVTF "u")])
(define_int_attr sur [(UNSPEC_SHADD "s") (UNSPEC_UHADD "u") (define_int_attr sur [(UNSPEC_SHADD "s") (UNSPEC_UHADD "u")
(UNSPEC_SRHADD "sr") (UNSPEC_URHADD "ur") (UNSPEC_SRHADD "sr") (UNSPEC_URHADD "ur")
......
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