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  1. 30 Jan, 2018 7 commits
    • Fix LRA subreg calculation for big-endian targets · e89b01f2 
      LRA was using a subreg offset of 0 whenever constraints matched
two operands with different modes.  That leads to an invalid offset
(and ICE) on big-endian targets if one of the modes is narrower
than a word.  E.g. if a (reg:SI X) is matched to a (reg:QI Y),
the big-endian subreg should be (subreg:QI (reg:SI X) 3) rather
than (subreg:QI (reg:SI X) 0).

But this raises the issue of what the behaviour should be when the
matched operands occupy different numbers of registers.  Should the
register numbers match, or should the locations of the lsbs match?
Although the documentation isn't clear, reload went for the second
interpretation (which seems the most natural to me):

      /* On a REG_WORDS_BIG_ENDIAN machine, point to the last register of a
         multiple hard register group of scalar integer registers, so that
         for example (reg:DI 0) and (reg:SI 1) will be considered the same
         register.  */

So I think this means that we can/must use the lowpart offset
unconditionally, rather than trying to separate out the multi-register
case.  This also matches the LRA handling of constant integers, which
already uses lowpart subregs.

The patch fixes gcc.target/aarch64/sve/extract_[34].c for aarch64_be.

2018-01-30  Richard Sandiford  <richard.sandiford@linaro.org>

gcc/
	* lra-constraints.c (match_reload): Use subreg_lowpart_offset
	rather than 0 when creating partial subregs.

From-SVN: r257177
      Richard Sandiford committed
    • Expand vec_perm_indices::series_p comment · 65aa25a4 
      2018-01-30  Richard Sandiford  <richard.sandiford@linaro.org>

gcc/
	* vec-perm-indices.c (vec_perm_indices::series_p): Give examples
	of usage.

From-SVN: r257176
      Richard Sandiford committed
    • [testsuite] XFAIL gcc.dg/tree-ssa/ssa-dom-cse-2.c on non-NEON arm targets · 502f6447 
      This test fails to optimise away the PLUS reduction in the loop on arm targets when vectorisation
is not enabled due to absence of SIMD instructions.
From reading the logs and the PR I gather that the presence or absence of SIMD affects the passing of this test
on other targets as well, as evidenced by the long list of xfail targets.
This list looks quite unwieldy to me, but here is a patch adding non-NEON arm to that list. 

    * gcc.dg/tree-ssa/ssa-dom-cse-2.c: XFAIL on !arm_neon arm targets.

From-SVN: r257175
      Kyrylo Tkachov committed
    • Fix AVX-512BITALG test failures · a236a499 
      gcc/testsuite
        PR target/83828
	* gcc.target/i386/avx512bitalg-vpopcntb-1.c: Fix test.
	* gcc.target/i386/avx512bitalg-vpopcntw-1.c: Ditto.
	* gcc.target/i386/avx512bitalgvl-vpopcntb-1.c: Ditto.
	* gcc.target/i386/avx512bitalgvl-vpopcntw-1.c: Ditto.

From-SVN: r257173
      Kirill Yukhin committed
    • re PR testsuite/81010 (test case gcc.target/powerpc/pr56605.c fails starting with r248958) · 6beb01d0 
      	PR testsuite/81010
	* gcc.target/powerpc/pr56605.c: Update various dg- directives to
	better match other tests which require vsx.  Verify the zero
	extension is part of the test in the combiner dump.

From-SVN: r257172
      Jeff Law committed
    • internal/syscall/unix: add randomTrap for sh/shbe · 111c8b4c 
          
    CL 84555 added support for the SuperH architecture, but didn't add the
    randomTrap definition to be used for the getrandom syscall on Linux.
    Add it now.
    
    Reviewed-on: https://go-review.googlesource.com/90535

From-SVN: r257171
      Ian Lance Taylor committed
    • Daily bump. · a8e4cea4 
      From-SVN: r257170
      GCC Administrator committed
  3. 29 Jan, 2018 18 commits
  5. 28 Jan, 2018 2 commits
  7. 27 Jan, 2018 9 commits
  9. 26 Jan, 2018 4 commits