re PR target/81550 (gcc.target/powerpc/loop_align.c fails starting with r250482)

2018-01-29  Michael Meissner  <meissner@linux.vnet.ibm.com>

	PR target/81550
	* config/rs6000/rs6000.c (rs6000_setup_reg_addr_masks): If DFmode
	and SFmode can go in Altivec registers (-mcpu=power7 for DFmode,
	-mcpu=power8 for SFmode) don't set the PRE_INCDEC or PRE_MODIFY
	flags.  This restores the settings used before the 2017-07-24.
	Turning off pre increment/decrement/modify allows IVOPTS to
	optimize DF/SF loops where the index is an int.

From-SVN: r257166

gcc/ChangeLog

+2018-01-29  Michael Meissner  <meissner@linux.vnet.ibm.com>
+
+	PR target/81550
+	* config/rs6000/rs6000.c (rs6000_setup_reg_addr_masks): If DFmode
+	and SFmode can go in Altivec registers (-mcpu=power7 for DFmode,
+	-mcpu=power8 for SFmode) don't set the PRE_INCDEC or PRE_MODIFY
+	flags.  This restores the settings used before the 2017-07-24.
+	Turning off pre increment/decrement/modify allows IVOPTS to
+	optimize DF/SF loops where the index is an int.
+
 2018-01-29  Richard Biener <rguenther@suse.de>
 	    Kelvin Nilsen  <kelvin@gcc.gnu.org>
 

gcc/config/rs6000/rs6000.c

@@ -2982,7 +2982,15 @@ rs6000_setup_reg_addr_masks (void)
 
 	      /* Figure out if we can do PRE_INC, PRE_DEC, or PRE_MODIFY
 		 addressing.  If we allow scalars into Altivec registers,
-		 don't allow PRE_INC, PRE_DEC, or PRE_MODIFY.  */
+		 don't allow PRE_INC, PRE_DEC, or PRE_MODIFY.
+
+		 For VSX systems, we don't allow update addressing for
+		 DFmode/SFmode if those registers can go in both the
+		 traditional floating point registers and Altivec registers.
+		 The load/store instructions for the Altivec registers do not
+		 have update forms.  If we allowed update addressing, it seems
+		 to break IV-OPT code using floating point if the index type is
+		 int instead of long (PR target/81550 and target/84042).  */
 
 	      if (TARGET_UPDATE
 		  && (rc == RELOAD_REG_GPR || rc == RELOAD_REG_FPR)
@@ -2990,6 +2998,8 @@ rs6000_setup_reg_addr_masks (void)
 		  && !VECTOR_MODE_P (m2)
 		  && !FLOAT128_VECTOR_P (m2)
 		  && !complex_p
+		  && (m != E_DFmode || !TARGET_VSX)
+		  && (m != E_SFmode || !TARGET_P8_VECTOR)
 		  && !small_int_vsx_p)
 		{
 		  addr_mask |= RELOAD_REG_PRE_INCDEC;