From-SVN: r269201

re PR c/89495 (gcc/c-family/c-format.c:1272:20: runtime error: signed integer overflow: 214748365 * 10 cannot be represented in type 'int')

	PR c/89495
	* c-format.c (maybe_read_dollar_number): Compute nargnum in
	HOST_WIDE_INT type to avoid overflows and change overflow_flag
	checking.

From-SVN: r269198

	PR c/77754
	* gcc.c-torture/compile/pr77754-1.c: New test.
	* gcc.c-torture/compile/pr77754-2.c: New test.
	* gcc.c-torture/compile/pr77754-3.c: New test.
	* gcc.c-torture/compile/pr77754-4.c: New test.
	* gcc.c-torture/compile/pr77754-5.c: New test.
	* gcc.c-torture/compile/pr77754-6.c: New test.

From-SVN: r269197

2019-02-25  Sandra Loosemore  <sandra@codesourcery.com>
	    Martin Sebor  <msebor@gmail.com>

	gcc/
	* c-family/c.opt (Wmissing-attributes): Clean up doc string.
	* common.opt (Wattribute-alias): Likewise.
	* doc/invoke.texi (Option Summary): List general form of
	-Wattribute-alias=.  List positive form of -Wmissing-attributes.
	(-Wmissing-attributes): Invert entry, rewrite and correct default.
	Add cross-references.
	(-Wattribute-alias): Rewrite and correct default.  Mention
	considered attributes (same as for -Wmissing-attributes).

Co-Authored-By: Martin Sebor <msebor@gmail.com>

From-SVN: r269196

Test FAILS: sse2-cvtpd2dq-1, sse2-cvtpd2ps, sse2-cvttpd2dq on powerpc64
(big-endian).

_mm_cvtpd_epi32, _mm_cvtpd_ps, _mm_cvttpd_epi32: Type conversion from
vector doubleword type to vector word type leaves the results in even
lanes in big endian mode.

Test FAILS: sse-cvtss2si-1, sse-cvtss2si-2, sse-movmskb-1 on powerpc
(32-bit big-endian).

Incorrect type for interpreting the result from mfvsrd instruction leads
to incorrect results.  Also, mfvsrd instruction only works as expected in
64-bit mode or for 32-bit quantities in 32-bit mode.  A more general,
if slower, solution is needed for 32-bit mode.

2019-02-25  Paul A. Clarke  <pc@us.ibm.com>

[gcc]

	* config/rs6000/emmintrin.h (_mm_cvtpd_epi32): Fix big endian.
	(_mm_cvtpd_ps): Likewise.
	(_mm_cvttpd_epi32): Likewise.

	PR target/89338
	* config/rs6000/xmmintrin.h (_mm_cvtss_f32):  Fix type mismatch.
	(_mm_cvt_ss2si): Fix type mismatch and 32-bit.

	PR target/89339
	* config/rs6000/xmmintrin.h (_mm_movemask_pi8): Fix 32-bit.

From-SVN: r269195

From-SVN: r269194

Commandline options on AArch64 don't get canonicalized into the smallest
possible set before output to the assembler. This means that overlapping feature
sets are emitted with superfluous parts.

Normally this isn't an issue, but in the case of crypto we have retro-actively
split it into aes and sha2. We need to emit only +crypto to the assembler
so old assemblers continue to work.

Because of how -mcpu=native and -march=native work they end up enabling all
feature bits. Instead we need to get the smallest possible set, which would also
fix the problem with older the assemblers and the retro-active split.

The function that handles this is called quite often.  It is called for any
push/pop options or attribute that changes arch, cpu etc.  In order to not make
this search for the smallest set too expensive we sort the options based on the
number of features (bits) they enable.  This allows us to process the list
linearly instead of quadratically (Once we have enabled a feature, we know that
anything else that enables it can be ignored.  By sorting we'll get the biggest
groups first and thus the smallest combination of commandline flags).

The Option handling structures have been extended to have a boolean to indicate
whether the option is synthetic, with that I mean if the option flag itself
enables a new feature.

e.g. +crypto isn't an actual feature, it just enables other features, but others
like +rdma enable multiple dependent features but is itself also a feature.

There are two ways to solve this.

1) Either have the options that are feature bits also turn themselves on, e.g.
   change rdma to turn on FP, SIMD and RDMA as dependency bits.

2) Make a distinction between these two different type of features and have the
   framework handle it correctly.

Even though it's more code I went for the second approach, as it's the one
that'll be less fragile (people can't forget it) and gives the least surprises.

Effectively this patch changes the following:

The values before the => are the old compiler and after the => the new code.

-march=armv8.2-a+crypto+sha2 => -march=armv8.2-a+crypto
-march=armv8.2-a+sha2+aes => -march=armv8.2-a+crypto

The remaining behaviors stay the same.

gcc/ChangeLog:

	PR target/88530
	* common/config/aarch64/aarch64-common.c
	(struct aarch64_option_extension): Add is_synthetic.
	(all_extensions): Use it.
	(TARGET_OPTION_INIT_STRUCT): Define hook.
	(struct gcc_targetm_common): Moved to end.
	(all_extensions_by_on): New.
	(opt_ext_cmp, typedef opt_ext): New.
	(aarch64_option_init_struct): New.
	(aarch64_contains_opt): New.
	(aarch64_get_extension_string_for_isa_flags): Output smallest set.
	* config/aarch64/aarch64-option-extensions.def
	(AARCH64_OPT_EXTENSION): Explicitly include AES and SHA2 in crypto.
	(fp, simd, crc, lse, fp16, rcpc, rdma, dotprod, aes, sha2, sha3,
	sm4, fp16fml, sve, profile, rng, memtag, sb, ssbs, predres):
	Set is_synthetic to false.
	(crypto): Set is_synthetic to true.
	* config/aarch64/driver-aarch64.c (AARCH64_OPT_EXTENSION): Add
	SYNTHETIC.

gcc/testsuite/ChangeLog:

	PR target/88530
	* gcc.target/aarch64/options_set_1.c: New test.
	* gcc.target/aarch64/options_set_2.c: New test.
	* gcc.target/aarch64/options_set_3.c: New test.
	* gcc.target/aarch64/options_set_4.c: New test.
	* gcc.target/aarch64/options_set_5.c: New test.
	* gcc.target/aarch64/options_set_6.c: New test.
	* gcc.target/aarch64/options_set_7.c: New test.
	* gcc.target/aarch64/options_set_8.c: New test.
	* gcc.target/aarch64/options_set_9.c: New test.

From-SVN: r269193

This patch updates the Armv8.4-a FP16 FML intrinsics's suffixes from u32 to f16
to be more consistent with the naming convention for intrinsics.

The specifications for these intrinsics have not been published yet so we do
not need to maintain the old names.

The patch was created with the following script:

grep -lIE "(vfml[as].+)_u32" -r gcc/ | grep -iEv ".+Changelog.*" \
  | xargs sed -i -E -e "s/(vfml[as].+)_u32/\1_f16/g" 

gcc/ChangeLog:

	* config/arm/arm_neon.h (vfmlal_low_u32, vfmlsl_low_u32,
	vfmlal_high_u32, vfmlsl_high_u32, vfmlalq_low_u32, vfmlslq_low_u32,
	vfmlalq_high_u32, vfmlslq_high_u32, vfmlal_lane_low_u32,
	vfmlal_lane_high_u32, vfmlalq_laneq_low_u32, vfmlalq_lane_low_u32,
	vfmlal_laneq_low_u32, vfmlalq_laneq_high_u32, vfmlalq_lane_high_u32,
	vfmlal_laneq_high_u32, vfmlsl_lane_low_u32, vfmlsl_lane_high_u32,
	vfmlslq_laneq_low_u32, vfmlslq_lane_low_u32, vfmlsl_laneq_low_u32,
	vfmlslq_laneq_high_u32, vfmlslq_lane_high_u32, vfmlsl_laneq_high_u32):
	Rename ...
	(vfmlal_low_f16, vfmlsl_low_f16, vfmlal_high_f16, vfmlsl_high_f16,
	vfmlalq_low_f16, vfmlslq_low_f16, vfmlalq_high_f16, vfmlslq_high_f16,
	vfmlal_lane_low_f16, vfmlal_lane_high_f16, vfmlalq_laneq_low_f16,
	vfmlalq_lane_low_f16, vfmlal_laneq_low_f16, vfmlalq_laneq_high_f16,
	vfmlalq_lane_high_f16, vfmlal_laneq_high_f16, vfmlsl_lane_low_f16,
	vfmlsl_lane_high_f16, vfmlslq_laneq_low_f16, vfmlslq_lane_low_f16,
	vfmlsl_laneq_low_f16, vfmlslq_laneq_high_f16, vfmlslq_lane_high_f16,
	vfmlsl_laneq_high_f16): ... To this.
	* config/arm/neon.md: Update comments.

gcc/testsuite/ChangeLog:

	* gcc.target/arm/simd/fp16fml_high.c (test_vfmlal_high_u32,
	test_vfmlalq_high_u32, test_vfmlsl_high_u32, test_vfmlslq_high_u32):
	Rename ....
	(test_vfmlal_high_f16, test_vfmlalq_high_f16, test_vfmlsl_high_f16,
	test_vfmlslq_high_f16): ... To this.
	* gcc.target/arm/simd/fp16fml_lane_high.c (test_vfmlal_lane_high_u32,
	tets_vfmlsl_lane_high_u32, test_vfmlal_laneq_high_u32,
	test_vfmlsl_laneq_high_u32, test_vfmlalq_lane_high_u32,
	test_vfmlslq_lane_high_u32, test_vfmlalq_laneq_high_u32,
	test_vfmlslq_laneq_high_u32): Rename ...
	(test_vfmlal_lane_high_f16, tets_vfmlsl_lane_high_f16,
	test_vfmlal_laneq_high_f16, test_vfmlsl_laneq_high_f16,
	test_vfmlalq_lane_high_f16, test_vfmlslq_lane_high_f16,
	test_vfmlalq_laneq_high_f16, test_vfmlslq_laneq_high_f16): ... To this.
	* gcc.target/arm/simd/fp16fml_lane_low.c (test_vfmlal_lane_low_u32,
	test_vfmlsl_lane_low_u32, test_vfmlal_laneq_low_u32,
	test_vfmlsl_laneq_low_u32, test_vfmlalq_lane_low_u32,
	test_vfmlslq_lane_low_u32, test_vfmlalq_laneq_low_u32,
	test_vfmlslq_laneq_low_u32): Rename ...
	(test_vfmlal_lane_low_f16, test_vfmlsl_lane_low_f16,
	test_vfmlal_laneq_low_f16, test_vfmlsl_laneq_low_f16,
	test_vfmlalq_lane_low_f16, test_vfmlslq_lane_low_f16,
	test_vfmlalq_laneq_low_f16, test_vfmlslq_laneq_low_f16): ... To this.
	* gcc.target/arm/simd/fp16fml_low.c (test_vfmlal_low_u32,
	test_vfmlalq_low_u32, test_vfmlsl_low_u32, test_vfmlslq_low_u32):
	Rename ...
	(test_vfmlal_low_f16, test_vfmlalq_low_f16, test_vfmlsl_low_f16,
	test_vfmlslq_low_f16): ... To this.

From-SVN: r269192

This patch updates the Armv8.4-a FP16 FML intrinsics's suffixes from u32 to f16
to be more consistent with the naming convention for intrinsics.

The specifications for these intrinsics have not been published yet so we do
not need to maintain the old names.

The patch was created with the following script:

grep -lIE "(vfml[as].+)_u32" -r gcc/ | grep -iEv ".+Changelog.*" \
  | xargs sed -i -E -e "s/(vfml[as].+)_u32/\1_f16/g"

gcc/ChangeLog:

	* config/aarch64/arm_neon.h (vfmlal_low_u32, vfmlsl_low_u32,
	vfmlalq_low_u32, vfmlslq_low_u32, vfmlal_high_u32, vfmlsl_high_u32,
	vfmlalq_high_u32, vfmlslq_high_u32, vfmlal_lane_low_u32,
	vfmlsl_lane_low_u32, vfmlal_laneq_low_u32, vfmlsl_laneq_low_u32,
	vfmlalq_lane_low_u32, vfmlslq_lane_low_u32, vfmlalq_laneq_low_u32,
	vfmlslq_laneq_low_u32, vfmlal_lane_high_u32, vfmlsl_lane_high_u32,
	vfmlal_laneq_high_u32, vfmlsl_laneq_high_u32, vfmlalq_lane_high_u32,
	vfmlslq_lane_high_u32, vfmlalq_laneq_high_u32, vfmlslq_laneq_high_u32):
	Rename ...
	(vfmlal_low_f16, vfmlsl_low_f16, vfmlalq_low_f16, vfmlslq_low_f16,
	vfmlal_high_f16, vfmlsl_high_f16, vfmlalq_high_f16, vfmlslq_high_f16,
	vfmlal_lane_low_f16, vfmlsl_lane_low_f16, vfmlal_laneq_low_f16,
	vfmlsl_laneq_low_f16, vfmlalq_lane_low_f16, vfmlslq_lane_low_f16,
	vfmlalq_laneq_low_f16, vfmlslq_laneq_low_f16, vfmlal_lane_high_f16,
	vfmlsl_lane_high_f16, vfmlal_laneq_high_f16, vfmlsl_laneq_high_f16,
	vfmlalq_lane_high_f16, vfmlslq_lane_high_f16, vfmlalq_laneq_high_f16,
	vfmlslq_laneq_high_f16): ... To this.

gcc/testsuite/ChangeLog:

	* gcc.target/aarch64/fp16_fmul_high.h (test_vfmlal_high_u32,
	test_vfmlalq_high_u32, test_vfmlsl_high_u32, test_vfmlslq_high_u32):
	Rename ...
	(test_vfmlal_high_f16, test_vfmlalq_high_f16, test_vfmlsl_high_f16,
	test_vfmlslq_high_f16): ... To this.
	* gcc.target/aarch64/fp16_fmul_lane_high.h (test_vfmlal_lane_high_u32,
	tets_vfmlsl_lane_high_u32, test_vfmlal_laneq_high_u32,
	test_vfmlsl_laneq_high_u32, test_vfmlalq_lane_high_u32,
	test_vfmlslq_lane_high_u32, test_vfmlalq_laneq_high_u32,
	test_vfmlslq_laneq_high_u32): Rename ...
	(test_vfmlal_lane_high_f16, tets_vfmlsl_lane_high_f16,
	test_vfmlal_laneq_high_f16, test_vfmlsl_laneq_high_f16,
	test_vfmlalq_lane_high_f16, test_vfmlslq_lane_high_f16,
	test_vfmlalq_laneq_high_f16, test_vfmlslq_laneq_high_f16): ... To this.
	* gcc.target/aarch64/fp16_fmul_lane_low.h (test_vfmlal_lane_low_u32,
	test_vfmlsl_lane_low_u32, test_vfmlal_laneq_low_u32,
	test_vfmlsl_laneq_low_u32, test_vfmlalq_lane_low_u32,
	test_vfmlslq_lane_low_u32, test_vfmlalq_laneq_low_u32,
	test_vfmlslq_laneq_low_u32): Rename ...
	(test_vfmlal_lane_low_f16, test_vfmlsl_lane_low_f16,
	test_vfmlal_laneq_low_f16, test_vfmlsl_laneq_low_f16,
	test_vfmlalq_lane_low_f16, test_vfmlslq_lane_low_f16,
	test_vfmlalq_laneq_low_f16, test_vfmlslq_laneq_low_f16): ... To this.
	* gcc.target/aarch64/fp16_fmul_low.h (test_vfmlal_low_u32,
	test_vfmlalq_low_u32, test_vfmlsl_low_u32, test_vfmlslq_low_u32):
	Rename ...
	(test_vfmlal_low_f16, test_vfmlalq_low_f16, test_vfmlsl_low_f16,
	test_vfmlslq_low_f16): ... To This.
	* lib/target-supports.exp
	(check_effective_target_arm_fp16fml_neon_ok_nocache): Update test.

From-SVN: r269191

2019-02-25  Dominique d'Humieres  <dominiq@gcc.gnu.org>

	PR fortran/89282
	* gfortran.dg/overload_3.f90: New test.

From-SVN: r269190

	PR rtl-optimization/86096
	* df-scan.c (df_mw_compare): Do not check mw_reg fields when
	comparing mw_order values.

From-SVN: r269189

	PR c++/89285
	* g++.dg/cpp1y/constexpr-89285-2.C: New test.

From-SVN: r269188

2019-02-25  Dominique d'Humieres  <dominiq@gcc.gnu.org>

	PR libfortran/89274
	* gfortran.dg/list_directed_large.f90: New test. 

2019-02-25  Dominique d'Humieres  <dominiq@gcc.gnu.org>

	PR libfortran/89274
	* io/write.c (write_integer): Add width for INTEGER(16).

From-SVN: r269187

	PR target/89434
	* config/arm/arm.md (*subsi3_carryin_const): Use
	arm_neg_immediate_operand predicate instead of
	arm_not_immediate_operand, "L" constraint instead of "K" and
	print it using %n2 instead of %B2.
	(*subsi3_carryin_const0): New define_insn.
	(*subsi3_carryin_compare_const): Use const_int_I_operand predicate
	instead of arm_not_operand and "I" constraint instead of "K" and
	print it using %n3 instead of %B2.  Instead of using match_dup 2 add
	another match_operand and in the condition check that it is negation
	of operands[2].
	(*subsi3_carryin_compare_const0): New define_ins.
	(*subdi_di_zesidi): Adjust to use *subsi3_carryin_const0 instead of
	*subsi3_carryin_const.
	(*arm_cmpdi_insn): Fix splitting into *subsi3_carryin_compare_const,
	split into *subsi3_carryin_compare_const0 if the highpart is zero.

	* gcc.c-torture/execute/pr89434.c: New test.

From-SVN: r269186

re PR target/89438 (ICE in glibc/sysdeps/ieee754/dbl-64/e_pow.c (internal compiler error: in decompose, at rtl.h:2266))

	PR target/89438
	* config/arm.vfp.md (*negdf2_vfp): Use
	gen_int_mode (0x80000000, SImode) instead of GEN_INT (0x80000000).
	* config/arm/neon.md (neon_copysignf<mode>): Likewise.

	* gcc.dg/pr89438.c: New test.

From-SVN: r269185

From-SVN: r269183

2019-02-24  Paolo Carlini  <paolo.carlini@oracle.com>

	PR c++/84585
	* g++.dg/cpp0x/pr84585.C: New.

From-SVN: r269180

2019-02-24  Thomas Koenig  <tkoenig@gcc.gnu.org>

	PR fortran/89174
	* trans-expr.c (gfc_find_and_cut_at_last_class_ref): Add is_mold
	to garguments. If we are dealing with a MOLD, call
	gfc_expr_to_initialize().
	* trans-stmt.c (gfc_trans_allocate): For MOLD, pass is_mold=true
	to gfc_find_and_cut_at_last_class_ref.
	* trans.h (gfc_find_and_cut_at_last_class_ref): Add optional
	argument is_mold with default false.

2019-02-24  Thomas Koenig  <tkoenig@gcc.gnu.org>

	PR fortran/89174
	* gfortran.dg/allocate_with_mold_3.f90: New test.

From-SVN: r269179

-mfpmath=sse is needed to enable SSE for FP math in 32-bit.

	PR target/87007
	* gcc.target/i386/pr87007-1.c: Compile with -mfpmath=sse.
	* gcc.target/i386/pr87007-2.c: Likewise.

From-SVN: r269178

2019-02-24  Harald Anlauf  <anlauf@gmx.de>

	PR fortran/89266
	PR fortran/88326
	* target-memory.c (gfc_element_size): Return false if element size
	cannot be determined; element size is returned separately.
	(gfc_target_expr_size): Return false if expression size cannot be
	determined; expression size is returned separately.
	* target-memory.h: Adjust prototypes.
	* check.c (gfc_calculate_transfer_sizes): Adjust references to
	gfc_target_expr_size, gfc_element_size.
	* arith.c (hollerith2representation): Likewise.
	* class.c (find_intrinsic_vtab): Likewise.
	* simplify.c (gfc_simplify_sizeof): Likewise.

	PR fortran/89266
	PR fortran/88326
	* gfortran.dg/pr89266.f90: New test.
	* gfortran.dg/pr88326.f90: New test.

From-SVN: r269177

	PR rtl-optimization/89445
	* simplify-rtx.c (simplify_ternary_operation): Don't use
	simplify_merge_mask on operands that may trap.
	* rtlanal.c (may_trap_p_1): Use FLOAT_MODE_P instead of
	SCALAR_FLOAT_MODE_P checks.  For integral division by zero, if
	second operand is CONST_VECTOR, check if any element could be zero.
	Don't expect traps for VEC_{MERGE,SELECT,CONCAT,DUPLICATE} unless
	their operands can trap.

	* gcc.target/i386/avx512f-pr89445.c: New test.

From-SVN: r269176

	PR libstdc++/89416
	* include/bits/alloc_traits.h (__is_alloc_insertable_impl): Make
	copy and move members public.

From-SVN: r269175

From-SVN: r269173

	* generate_libstdcxx_web_docs: Improve error output.

From-SVN: r269169

	* include/std/type_traits (__underlying_type_impl): New helper to
	make underlying_type SFINAE-friendly.
	(underlying_type): Derive from __underlying_type_impl.
	* testsuite/20_util/underlying_type/requirements/typedefs-3.cc: New
	test.

From-SVN: r269168

builtin-sprintf-10.c: Cast remaining wchar_t to wint_t to avoid a bogus -Wformat warning in ILP32...

gcc/testsuite/ChangeLog:
	* gcc.dg/tree-ssa/builtin-sprintf-10.c: Cast remaining
	wchar_t to wint_t to avoid a bogus -Wformat warning in
	ILP32 (bug 77970).

From-SVN: r269167

gcc/ChangeLog:
	* gimple-ssa-sprintf.c (target_strtol): Rename...
	(target_strtohwi): ...to this.  Handle values up to HOST_WIDE_INT_MAX.
	(parse_directive): Adjust to name change.  Use HOST_WIDE_INT_MAX to
	check for range error.

From-SVN: r269166

	PR testsuite/89476
	* gfortran.dg/ISO_Fortran_binding_5.c: Include
	"../../../libgfortran/ISO_Fortran_binding.h".
	* gfortran.dg/ISO_Fortran_binding_6.c: Likewise.

From-SVN: r269165

When -march=native is passed to host_detect_local_cpu to the backend,
it overrides all command lines after it.  That means

$ gcc -march=native -march=skylake-avx512

is the treated as

$ gcc -march=skylake-avx512 -march=native

Prune joined switches with Negative and RejectNegative to allow
-march=skylake-avx512 to override previous -march=native on command-line.

gcc/

	PR driver/69471
	* opts-common.c (prune_options): Also prune joined switches
	with Negative and RejectNegative.
	* config/i386/i386.opt (march=): Add Negative(march=).
	(mtune=): Add Negative(mtune=).
	* doc/options.texi: Document Negative used together with Joined
	and RejectNegative.

gcc/testsuite/

	PR driver/69471
	* gcc.dg/pr69471-1.c: New test.
	* gcc.dg/pr69471-2.c: Likewise.
	* gcc.target/i386/pr69471-3.c: Likewise.

From-SVN: r269164

2019-02-23  Jerry DeLisle <jvdelisle@gcc.gnu.org>

	PR fortran/84387
	* trans-io.c (transfer_expr): Do not return if there are no
	components to the derived type or class.

	* gfortran.dg/dtio_34.f90: New test.

From-SVN: r269161

	PR c++/89419
	* g++.dg/cpp1y/lambda-generic-89419.C: New test.

From-SVN: r269159

	* pt.c (maybe_instantiate_noexcept): Set up the list of local
	specializations.  Set current_class_{ptr,ref}.

	* g++.dg/cpp0x/noexcept34.C: New test.
	* g++.dg/cpp0x/noexcept35.C: New test.

From-SVN: r269158

2019-02-23  Paul Thomas  <pault@gcc.gnu.org>

	PR fortran/88117
	* resolve.c (deferred_op_assign): Return if the lhs expression
	has the pointer attribute.
	* trans-expr.c (gfc_trans_assignment_1): Do not fix the string
	length if the lhs expression has the pointer attribute.

2019-02-23  Paul Thomas  <pault@gcc.gnu.org>

	PR fortran/88117
	* gfortran.dg/deferred_character_32.f90 : New test

From-SVN: r269157

2019-02-23  Paul Thomas  <pault@gcc.gnu.org>

	PR fortran/89385
	PR fortran/89366
	* decl.c (gfc_verify_c_interop_param): Restriction on string
	length being one is lifted for F2018.
	* trans-expr.c (gfc_conv_gfc_desc_to_cfi_desc): For scalar
	characters with intent in, make a temporary and copy the result
	of the expression evaluation into it.
	(gfc_conv_procedure_call): Set a flag for character formal args
	having a character length that is not unity. If the procedure
	is bind C, call gfc_conv_gfc_desc_to_cfi_desc in this case.
	Also, extend bind C calls to unconditionally convert both
	pointers and allocatable expressions.

2019-02-23  Paul Thomas  <pault@gcc.gnu.org>

	PR fortran/89385
	* gfortran.dg/ISO_Fortran_binding_1.f90 : Correct test for
	previously incorrect lbound for allocatable expressions. Also
	correct stop values to avoid repetition.
	* gfortran.dg/ISO_Fortran_binding_5.f90 : New test
	* gfortran.dg/ISO_Fortran_binding_5.c : Support previous test.

	PR fortran/89366
	* gfortran.dg/ISO_Fortran_binding_6.f90 : New test
	* gfortran.dg/ISO_Fortran_binding_6.c : Support previous test.
	* gfortran.dg/pr32599.f03 : Set standard to F2008.

2019-02-23  Paul Thomas  <pault@gcc.gnu.org>

	PR fortran/89385
	PR fortran/89366
	* runtime/ISO_Fortran_binding.c (cfi_desc_to_gfc_desc) : In the
	interchange between character and derived, the character type
	was being set incorrectly.
	(gfc_desc_to_cfi_desc) : Eliminate the interchange of types in
	this function. Do not add the kind and length information to
	the type field of structures. Lbounds were incorrectly being
	set to zero for allocatable and pointer descriptors. Should
	have been non-pointer, non-allocatables that received this
	treatment.

From-SVN: r269156

	PR libstdc++/89446
	* include/bits/char_traits.h (__constant_char_array): Check index is
	in range before dereferencing.
	(char_traits<char>::compare, char_traits<char>::find)
	(char_traits<char8_t>::compare, char_traits<char8_t>::find): Return
	immediately if n is zero.
	(char_traits<wchar_t>::compare, char_traits<wchar_t>::find): Likewise.
	Remove workarounds for PR 67026.
	* testsuite/21_strings/basic_string_view/operators/char/89446.cc:
	New test.
	* testsuite/21_strings/basic_string_view/operators/wchar_t/89446.cc:
	New test.

From-SVN: r269148

gcc/cp/ChangeLog:
	PR c++/89390
	* parser.c (cp_parser_unqualified_id): Capture and use locations
	for destructors.

gcc/testsuite/ChangeLog:
	PR c++/89390
	* g++.dg/diagnostic/pr89390.C: Update expected location of error,
	renaming to a multicharacter name, so that start != finish.  Add
	tests for dtor locations.

From-SVN: r269145

From-SVN: r269142

	PR middle-end/88074
	* simplify.c (norm2_do_sqrt, gfc_simplify_norm2): Use
	mpfr_number_p && !mpfr_zero_p instead of mpfr_regular_p.
	(norm2_add_squared): Likewise.  Use mp_exp_t rather than mpfr_exp_t.

Co-Authored-By: Jakub Jelinek <jakub@redhat.com>

From-SVN: r269139

2019-02-22  Paolo Carlini  <paolo.carlini@oracle.com>

	PR c++/84676
	* g++.dg/cpp0x/pr84676.C: New.

From-SVN: r269138

builtin-sprintf-10.c: Cast wchar_t to wint_t to avoid a bogus -Wformat warning in ILP32 (bug 77970).

gcc/testsuite/ChangeLog:

	* gcc.dg/tree-ssa/builtin-sprintf-10.c: Cast wchar_t to wint_t
	to avoid a bogus -Wformat warning in ILP32 (bug 77970).

From-SVN: r269137