Test FAILS: sse2-cvtpd2dq-1, sse2-cvtpd2ps, sse2-cvttpd2dq on powerpc64
(big-endian).
_mm_cvtpd_epi32, _mm_cvtpd_ps, _mm_cvttpd_epi32: Type conversion from
vector doubleword type to vector word type leaves the results in even
lanes in big endian mode.
Test FAILS: sse-cvtss2si-1, sse-cvtss2si-2, sse-movmskb-1 on powerpc
(32-bit big-endian).
Incorrect type for interpreting the result from mfvsrd instruction leads
to incorrect results. Also, mfvsrd instruction only works as expected in
64-bit mode or for 32-bit quantities in 32-bit mode. A more general,
if slower, solution is needed for 32-bit mode.
2019-02-25 Paul A. Clarke <pc@us.ibm.com>
[gcc]
* config/rs6000/emmintrin.h (_mm_cvtpd_epi32): Fix big endian.
(_mm_cvtpd_ps): Likewise.
(_mm_cvttpd_epi32): Likewise.
PR target/89338
* config/rs6000/xmmintrin.h (_mm_cvtss_f32): Fix type mismatch.
(_mm_cvt_ss2si): Fix type mismatch and 32-bit.
PR target/89339
* config/rs6000/xmmintrin.h (_mm_movemask_pi8): Fix 32-bit.
From-SVN: r269195
