1. 04 Feb, 2016 21 commits
    • This patch fixes an exponential issue in ccmp.c. · e0b059b1
      This patch fixes an exponential issue in ccmp.c.  When deciding which ccmp
      expansion to use, the tree nodes gs0 and gs1 are fully expanded twice.  If
      they contain more CCMP opportunities, their subtrees are also expanded twice.
      When the trees are complex the expansion takes exponential time and memory.
      As a workaround in GCC6 compute the cost of the first expansion early, and
      only try the alternative expansion if the cost is low enough.  This rarely
      affects real code, eg. SPECINT2006 has identical codesize.
      
      2016-02-04  Wilco Dijkstra  <wdijkstr@arm.com>
      
          gcc/
      	PR target/69619
      	* ccmp.c (expand_ccmp_expr_1): Avoid evaluating gs0/gs1
      	twice when complex.
      
          gcc/testsuite/
      	PR target/69619
      	* gcc.dg/pr69619.c: Add new test.
      
      From-SVN: r233145
      Wilco Dijkstra committed
    • gcc: invoke: delete -mno-fma4 docs · 56f3bb38
      We don't document the -mno-xxx variants for other flags here, and the
      paragraph here specifically says "Each has a corresponding -mno- option
      to disable use of these instructions".  Drop the -mno-fma4 line.
      
      From-SVN: r233144
      Mike Frysinger committed
    • PR 69577: Invalid RA of destination subregs · 2692b5c8
      In PR 69577 we have:
      
            A: (set (reg:V2TI X) ...)
            B: (set (subreg:TI (reg:V2TI X) 0) ...)
      
      X gets allocated to an AVX register, as usual for V2TI.  The problem is
      that the movti for B doesn't then preserve the other half of X, even
      though the subreg semantics are supposed to guarantee that.
      
      If instead the same value had been set by:
      
            A': (set (subreg:TI (reg:V2TI X) 16) ...)
            B: (set (subreg:TI (reg:V2TI X) 0) ...)
      
      the subreg in A' would have prevented the use of AVX registers for X,
      since you can't directly access the high part.
      
      IMO these are really the same thing.  An alternative way to view it
      is that the original sequence is equivalent to:
      
            A: (set (reg:V2TI X) ...)
            B1: (set (subreg:TI (reg:V2TI X) 0) ...)
            B2: (set (subreg:TI (reg:V2TI X) 16) (subreg:TI (reg:V2TI X) 16))
      
      in which B2 is a no-op and therefore implicit.  The handling ought
      to be the same regardless of whether there is an rtl insn that
      explicitly assigns to (subreg:TI (reg:V2TI X) 16).
      
      This patch implements that idea.  Hopefully the comments explain
      what's going on.
      
      Tested on x86_64-linux-gnu, aarch64-linux-gnu and arm-linux-gnueabihf.
      
      gcc/
      	PR rtl-optimization/69577
      	* reginfo.c (record_subregs_of_mode): Add a partial_def parameter.
      	(find_subregs_of_mode): Update accordingly.  Iterate over partial
      	definitions.
      
      gcc/testsuite/
      	PR rtl-optimization/69577
      	* gcc.target/i386/pr69577.c: New test.
      
      From-SVN: r233143
      Richard Sandiford committed
    • [ARM] Remove neon_reinterpret, use casts · 1d108634
      	* config/arm/arm-protos.h (neon_reinterpret): Remove.
      	* config/arm/arm.c (neon_reinterpret): Remove.
      	* config/arm/arm_neon_builtins.def (vreinterpretv8qi, vreinterpretv4hi,
      	vreinterpretv2si, vreinterpretv2sf, vreinterpretdi, vreinterpretv16qi,
      	vreinterpretv8hi, vreinterpretv4si, vreinterpretv4sf, vreinterpretv2di,
      	vreinterpretti): Remove.
      	* config/arm/neon.md (neon_vreinterpretv8qi<mode>,
      	neon_vreinterpretv4hi<mode>, neon_vreinterpretv2si<mode>,
      	neon_vreinterpretv2sf<mode>, neon_vreinterpretdi<mode>,
      	neon_vreinterpretti<mode>, neon_vreinterpretv16qi<mode>,
      	neon_vreinterpretv8hi<mode>, neon_vreinterpretv4si<mode>,
      	neon_vreinterpretv4sf<mode>, neon_vreinterpretv2di<mode>): Remove.
      	* config/arm/arm_neon.h (vreinterpret_p8_p16, vreinterpret_p8_f32,
      	vreinterpret_p8_p64, vreinterpret_p8_s64, vreinterpret_p8_u64,
      	vreinterpret_p8_s8, vreinterpret_p8_s16, vreinterpret_p8_s32,
      	vreinterpret_p8_u8, vreinterpret_p8_u16, vreinterpret_p8_u32,
      	vreinterpret_p16_p8, vreinterpret_p16_f32, vreinterpret_p16_p64,
      	vreinterpret_p16_s64, vreinterpret_p16_u64, vreinterpret_p16_s8,
      	vreinterpret_p16_s16, vreinterpret_p16_s32, vreinterpret_p16_u8,
      	vreinterpret_p16_u16, vreinterpret_p16_u32, vreinterpret_f32_p8,
      	vreinterpret_f32_p16, vreinterpret_f32_p64, vreinterpret_f32_s64,
      	vreinterpret_f32_u64, vreinterpret_f32_s8, vreinterpret_f32_s16,
      	vreinterpret_f32_s32, vreinterpret_f32_u8, vreinterpret_f32_u16,
      	vreinterpret_f32_u32, vreinterpret_p64_p8, vreinterpret_p64_p16,
      	vreinterpret_p64_f32, vreinterpret_p64_s64, vreinterpret_p64_u64,
      	vreinterpret_p64_s8, vreinterpret_p64_s16, vreinterpret_p64_s32,
      	vreinterpret_p64_u8, vreinterpret_p64_u16, vreinterpret_p64_u32,
      	vreinterpret_s64_p8, vreinterpret_s64_p16, vreinterpret_s64_f32,
      	vreinterpret_s64_p64, vreinterpret_s64_u64, vreinterpret_s64_s8,
      	vreinterpret_s64_s16, vreinterpret_s64_s32, vreinterpret_s64_u8,
      	vreinterpret_s64_u16, vreinterpret_s64_u32, vreinterpret_u64_p8,
      	vreinterpret_u64_p16, vreinterpret_u64_f32, vreinterpret_u64_p64,
      	vreinterpret_u64_s64, vreinterpret_u64_s8, vreinterpret_u64_s16,
      	vreinterpret_u64_s32, vreinterpret_u64_u8, vreinterpret_u64_u16,
      	vreinterpret_u64_u32, vreinterpret_s8_p8, vreinterpret_s8_p16,
      	vreinterpret_s8_f32, vreinterpret_s8_p64, vreinterpret_s8_s64,
      	vreinterpret_s8_u64, vreinterpret_s8_s16, vreinterpret_s8_s32,
      	vreinterpret_s8_u8, vreinterpret_s8_u16, vreinterpret_s8_u32,
      	vreinterpret_s16_p8, vreinterpret_s16_p16, vreinterpret_s16_f32,
      	vreinterpret_s16_p64, vreinterpret_s16_s64, vreinterpret_s16_u64,
      	vreinterpret_s16_s8, vreinterpret_s16_s32, vreinterpret_s16_u8,
      	vreinterpret_s16_u16, vreinterpret_s16_u32, vreinterpret_s32_p8,
      	vreinterpret_s32_p16, vreinterpret_s32_f32, vreinterpret_s32_p64,
      	vreinterpret_s32_s64, vreinterpret_s32_u64, vreinterpret_s32_s8,
      	vreinterpret_s32_s16, vreinterpret_s32_u8, vreinterpret_s32_u16,
      	vreinterpret_s32_u32, vreinterpret_u8_p8, vreinterpret_u8_p16,
      	vreinterpret_u8_f32, vreinterpret_u8_p64, vreinterpret_u8_s64,
      	vreinterpret_u8_u64, vreinterpret_u8_s8, vreinterpret_u8_s16,
      	vreinterpret_u8_s32, vreinterpret_u8_u16, vreinterpret_u8_u32,
      	vreinterpret_u16_p8, vreinterpret_u16_p16, vreinterpret_u16_f32,
      	vreinterpret_u16_p64, vreinterpret_u16_s64, vreinterpret_u16_u64,
      	vreinterpret_u16_s8, vreinterpret_u16_s16, vreinterpret_u16_s32,
      	vreinterpret_u16_u8, vreinterpret_u16_u32, vreinterpret_u32_p8,
      	vreinterpret_u32_p16, vreinterpret_u32_f32, vreinterpret_u32_p64,
      	vreinterpret_u32_s64, vreinterpret_u32_u64, vreinterpret_u32_s8,
      	vreinterpret_u32_s16, vreinterpret_u32_s32, vreinterpret_u32_u8,
      	vreinterpret_u32_u16, vreinterpretq_p8_p16, vreinterpretq_p8_f32,
      	vreinterpretq_p8_p64, vreinterpretq_p8_p128, vreinterpretq_p8_s64,
      	vreinterpretq_p8_u64, vreinterpretq_p8_s8, vreinterpretq_p8_s16,
      	vreinterpretq_p8_s32, vreinterpretq_p8_u8, vreinterpretq_p8_u16,
      	vreinterpretq_p8_u32, vreinterpretq_p16_p8, vreinterpretq_p16_f32,
      	vreinterpretq_p16_p64, vreinterpretq_p16_p128, vreinterpretq_p16_s64,
      	vreinterpretq_p16_u64, vreinterpretq_p16_s8, vreinterpretq_p16_s16,
      	vreinterpretq_p16_s32, vreinterpretq_p16_u8, vreinterpretq_p16_u16,
      	vreinterpretq_p16_u32, vreinterpretq_f32_p8, vreinterpretq_f32_p16,
      	vreinterpretq_f32_p64, vreinterpretq_f32_p128, vreinterpretq_f32_s64,
      	vreinterpretq_f32_u64, vreinterpretq_f32_s8, vreinterpretq_f32_s16,
      	vreinterpretq_f32_s32, vreinterpretq_f32_u8, vreinterpretq_f32_u16,
      	vreinterpretq_f32_u32, vreinterpretq_p64_p8, vreinterpretq_p64_p16,
      	vreinterpretq_p64_f32, vreinterpretq_p64_p128, vreinterpretq_p64_s64,
      	vreinterpretq_p64_u64, vreinterpretq_p64_s8, vreinterpretq_p64_s16,
      	vreinterpretq_p64_s32, vreinterpretq_p64_u8, vreinterpretq_p64_u16,
      	vreinterpretq_p64_u32, vreinterpretq_p128_p8, vreinterpretq_p128_p16,
      	vreinterpretq_p128_f32, vreinterpretq_p128_p64, vreinterpretq_p128_s64,
      	vreinterpretq_p128_u64, vreinterpretq_p128_s8, vreinterpretq_p128_s16,
      	vreinterpretq_p128_s32, vreinterpretq_p128_u8, vreinterpretq_p128_u16,
      	vreinterpretq_p128_u32, vreinterpretq_s64_p8, vreinterpretq_s64_p16,
      	vreinterpretq_s64_f32, vreinterpretq_s64_p64, vreinterpretq_s64_p128,
      	vreinterpretq_s64_u64, vreinterpretq_s64_s8, vreinterpretq_s64_s16,
      	vreinterpretq_s64_s32, vreinterpretq_s64_u8, vreinterpretq_s64_u16,
      	vreinterpretq_s64_u32, vreinterpretq_u64_p8, vreinterpretq_u64_p16,
      	vreinterpretq_u64_f32, vreinterpretq_u64_p64, vreinterpretq_u64_p128,
      	vreinterpretq_u64_s64, vreinterpretq_u64_s8, vreinterpretq_u64_s16,
      	vreinterpretq_u64_s32, vreinterpretq_u64_u8, vreinterpretq_u64_u16,
      	vreinterpretq_u64_u32, vreinterpretq_s8_p8, vreinterpretq_s8_p16,
      	vreinterpretq_s8_f32, vreinterpretq_s8_p64, vreinterpretq_s8_p128,
      	vreinterpretq_s8_s64, vreinterpretq_s8_u64, vreinterpretq_s8_s16,
      	vreinterpretq_s8_s32, vreinterpretq_s8_u8, vreinterpretq_s8_u16,
      	vreinterpretq_s8_u32, vreinterpretq_s16_p8, vreinterpretq_s16_p16,
      	vreinterpretq_s16_f32, vreinterpretq_s16_p64, vreinterpretq_s16_p128,
      	vreinterpretq_s16_s64, vreinterpretq_s16_u64, vreinterpretq_s16_s8,
      	vreinterpretq_s16_s32, vreinterpretq_s16_u8, vreinterpretq_s16_u16,
      	vreinterpretq_s16_u32, vreinterpretq_s32_p8, vreinterpretq_s32_p16,
      	vreinterpretq_s32_f16, vreinterpretq_s32_f32, vreinterpretq_s32_p64,
      	vreinterpretq_s32_p128, vreinterpretq_s32_s64, vreinterpretq_s32_u64,
      	vreinterpretq_s32_s8, vreinterpretq_s32_s16, vreinterpretq_s32_u8,
      	vreinterpretq_s32_u16, vreinterpretq_s32_u32, vreinterpretq_u8_p8,
      	vreinterpretq_u8_p16, vreinterpretq_u8_f32, vreinterpretq_u8_p64,
      	vreinterpretq_u8_p128, vreinterpretq_u8_s64, vreinterpretq_u8_u64,
      	vreinterpretq_u8_s8, vreinterpretq_u8_s16, vreinterpretq_u8_s32,
      	vreinterpretq_u8_u16, vreinterpretq_u8_u32, vreinterpretq_u16_p8,
      	vreinterpretq_u16_p16, vreinterpretq_u16_f32, vreinterpretq_u16_p64,
      	vreinterpretq_u16_p128, vreinterpretq_u16_s64, vreinterpretq_u16_u64,
      	vreinterpretq_u16_s8, vreinterpretq_u16_s16, vreinterpretq_u16_s32,
      	vreinterpretq_u16_u8, vreinterpretq_u16_u32, vreinterpretq_u32_p8,
      	vreinterpretq_u32_p16, vreinterpretq_u32_f32, vreinterpretq_u32_p64,
      	vreinterpretq_u32_p128, vreinterpretq_u32_s64, vreinterpretq_u32_u64,
      	vreinterpretq_u32_s8, vreinterpretq_u32_s16, vreinterpretq_u32_s32,
      	vreinterpretq_u32_u8, vreinterpretq_u32_u16): Rewrite using casts.
      
      From-SVN: r233142
      Alan Lawrence committed
    • Update gcc .po files. · d44cb386
      	* be.po, da.po, de.po, el.po, es.po, fi.po, fr.po, hr.po, id.po,
      	ja.po, nl.po, ru.po, sr.po, sv.po, tr.po, uk.po, vi.po, zh_CN.po,
      	zh_TW.po: Update.
      
      From-SVN: r233141
      Joseph Myers committed
    • Update cpplib .po files. · ed84c4aa
      	* be.po, ca.po, da.po, de.po, el.po, eo.po, es.po, fi.po, fr.po,
      	id.po, ja.po, nl.po, pr_BR.po, ru.po, sr.po, sv.po, tr.po, uk.po,
      	vi.po, zh_CN.po, zh_TW.po: Update.
      
      From-SVN: r233140
      Joseph Myers committed
    • re PR sanitizer/69276 (Address sanitizer does not handle heap overflow) · 7db337c2
      Fix PR sanitizer/69276
      
      	* g++.dg/asan/pr69276.C: New test.
      	PR sanitizer/PR69276
      	* asan.c (has_stmt_been_instrumented_p): Instrument gimple calls
      	that are gimple_store_p.
      	(maybe_instrument_call): Likewise.
      
      From-SVN: r233137
      Martin Liska committed
    • aarch64.c (aarch64_legitimize_address): Force register scaling out of memory… · 60d27907
      aarch64.c (aarch64_legitimize_address): Force register scaling out of memory reference and comment why.
      
      
      	* config/aarch64/aarch64.c (aarch64_legitimize_address): Force
      	register scaling out of memory reference and comment why.
      
      From-SVN: r233136
      Bin Cheng committed
    • class.c (find_flexarrays): Don't declare dom variable. · d1243d27
      	* class.c (find_flexarrays): Don't declare dom variable.
      	(diagnose_flexarray): Likewise.
      
      From-SVN: r233135
      Jakub Jelinek committed
    • [ARM][4/4] Adjust gcc.target/arm/wmul-[123].c tests · cc9c0829
      	PR target/65932
      	PR target/67714
      	* gcc.target/arm/wmul-3.c: Simplify test to generate just
      	a single smulbb instruction.
      	* gcc.target/amr/wmul-1.c: Add -mtune=cortex-a9 to dg-options.
      	* gcc.target/amr/wmul-2.c: Likewise.
      
      From-SVN: r233134
      Kyrylo Tkachov committed
    • [cse][3/4] Don't overwrite original rtx when folding source of set · 625d55af
      	PR target/65932
      	PR target/67714
      	* cse.c (cse_insn): Pass NULL to fold_rtx when initially
      	folding the source of a SET.
      
      From-SVN: r233133
      Kyrylo Tkachov committed
    • [ARM][2/4] Fix operand costing logic for SMUL[TB][TB] · 9fec9595
      	PR target/65932
      	PR target/67714
      	* config/arm/arm.c (arm_new_rtx_costs, MULT case): Properly extract
      	the operands of the SIGN_EXTENDs from a SMUL[TB][TB] rtx.
      
      From-SVN: r233132
      Kyrylo Tkachov committed
    • [ARM][1/4] PR target/65932: Add testcase · eb9feb52
      	PR target/65932
      	PR target/67714
      	* gcc.c-torture/execute/pr67714.c: New test.
      
      From-SVN: r233131
      Kyrylo Tkachov committed
    • [ARM] PR target/65932: stop changing signedness in PROMOTE_MODE · 8644f49f
      2016-02-04  Jim Wilson  <jim.wilson@linaro.org>
      
      	PR target/65932
      	PR target/67714
      	* config/arm/arm.h (PROMOTE_MODE): Don't set UNSIGNEDP for QImode and
      	HImode.
      
      From-SVN: r233130
      Jim Wilson committed
    • arm-c.c (arm_reset_previous_fndecl): Style fix and typo. · e8449dec
      2016-02-04  Christian Bruel  <christian.bruel@st.com>
      
      	* config/arm/arm-c.c (arm_reset_previous_fndecl): Style fix and typo.
      	* config/arm/arm.c (arm_set_current_function): Likewise.
      
      From-SVN: r233129
      Christian Bruel committed
    • re PR target/69454 (ix86_expand_prologue internal compiler error: Segmentation fault) · 61f727fe
      	PR target/69454
      	* config/i386/i386.c (convert_scalars_to_vector): Remove
      	stack alignment fixes.
      	(ix86_option_override_internal): Disable TARGET_STV if stack
      	might not be aligned enough.
      	(ix86_minimum_alignment): Assert that TARGET_STV is false.
      
      	* gcc.target/i386/pr69454-1.c: New test.
      	* gcc.target/i386/pr69454-2.c: New test.
      
      From-SVN: r233128
      Jakub Jelinek committed
    • Disable auto prefetcher for -march=znver1. · 07d88205
      2016-02-04  Victoria Stepanyan  <victoria.stepanyan@amd.com>
      
              * gcc/config/i386/x86-tune.def: Disable default prefetching
              for -march=znver1.
      
      From-SVN: r233127
      Victoria Stepanyan committed
    • PR c++/69251 - [6 Regression] ICE in unify_array_domain on a flexible array · 05dd97db
      PR c++/69251 - [6 Regression] ICE in unify_array_domain on a flexible array
                     member
      PR c++/69253 - [6 Regression] ICE in cxx_incomplete_type_diagnostic initializing
                     a flexible array member with empty string
      PR c++/69290 - [6 Regression] ICE on invalid initialization of a flexible array
                     member
      PR c++/69277 - [6 Regression] ICE mangling a flexible array member
      PR c++/69349 - template substitution error for flexible array members
      
      gcc/testsuite/ChangeLog:
      2016-02-03  Martin Sebor  <msebor@redhat.com>
      
      	PR c++/69251
      	PR c++/69253
      	PR c++/69290
      	PR c++/69277
      	PR c++/69349
      	* g++.dg/ext/flexarray-mangle-2.C: New test.
      	* g++.dg/ext/flexarray-mangle.C: New test.
      	* g++.dg/ext/flexarray-subst.C: New test.
      	* g++.dg/ext/flexary11.C: New test.
      	* g++.dg/ext/flexary12.C: New test.
      	* g++.dg/ext/flexary13.C: New test.
      	* g++.dg/ext/flexary14.C: New test.
      	* g++.dg/other/dump-ada-spec-2.C: Adjust.
      
      gcc/cp/ChangeLog:
      2016-02-03  Martain Sebor  <msebor@redhat.com>
      
      	PR c++/69251
      	PR c++/69253
      	PR c++/69290
      	PR c++/69277
      	PR c++/69349
      	* class.c (walk_subobject_offsets): Avoid testing the upper bound
      	of a flexible array member for equality to null.
      	(find_flexarrays): Remove spurious whitespace introduced in r231665.
      	(diagnose_flexarrays): Avoid checking the upper bound of arrays.
      	(check_flexarrays): Same.
      	* decl.c (compute_array_index_type): Avoid special case for flexible
      	array members.
      	(grokdeclarator): Avoid calling compute_array_index_type for flexible
      	array members.
      	* error.c (dump_type_suffix): Revert changes introduced in r231665
      	and rendered unnecessary by the changes above.
      	* pt.c (tsubst):  Same.
      	* tree.c (build_ctor_subob_ref): Handle flexible array members.
      	* typeck2.c (digest_init_r): Revert changes introduced in r231665.
      	(process_init_constructor_array): Same.
      	(process_init_constructor_record): Same.
      
      From-SVN: r233126
      Martin Sebor committed
    • Define check_union_passing6 only for CHECK_FLOAT128 · dac2fc29
      	* gcc.target/i386/iamcu/test_passing_unions.c (check_union_passing6):
      	Define only if CHECK_FLOAT128 is defined.
      	(main): Properly initialize u5.
      
      From-SVN: r233124
      H.J. Lu committed
    • re PR target/69461 (ICE in lra_set_insn_recog_data, at lra.c:964) · 5a01e0c7
      2016-02-03  Michael Meissner  <meissner@linux.vnet.ibm.com>
      	    Vladimir Makarov  <vmakarov@redhat.com>
      
      	PR target/69461
      	* config/rs6000/rs6000.c (rs6000_legitimate_address_p): Fix thinko
      	in validating fused toc addresses.
      
      
      Co-Authored-By: Vladimir Makarov <vmakarov@redhat.com>
      
      From-SVN: r233120
      Michael Meissner committed
    • Daily bump. · 20279ed0
      From-SVN: r233119
      GCC Administrator committed
  2. 03 Feb, 2016 16 commits
  3. 02 Feb, 2016 3 commits