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  1. 20 Mar, 2017 2 commits
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  5. 18 Mar, 2017 10 commits
  7. 17 Mar, 2017 19 commits
  9. 16 Mar, 2017 6 commits
    • stabilize store merging · 50b6d676 
      Don't let pointer randomization change the order in which we process
store chains.  This may cause SSA_NAMEs to be released in different
order, and if they're reused later, they may cause differences in SSA
partitioning, leading to differences in expand, and ultimately to
different code.

bootstrap-debug-lean (-fcompare-debug) on i686-linux-gnu has failed in
haifa-sched.c since r245196 exposed the latent ordering problem in
store merging.  In this case, the IR differences (different SSA names
selected for copies in out-of-SSA, resulting in some off-by-one
differences in pseudos) were not significant enough to be visible in
the compiler output.


for  gcc/ChangeLog

	* gimple-ssa-store-merging.c (struct imm_store_chain_info):
	Add linked-list forward and backlinks.  Insert on
	construction, remove on destruction.
	(class pass_store_merging): Add m_stores_head field.
	(pass_store_merging::terminate_and_process_all_chains):
	Iterate over m_stores_head list.
	(pass_store_merging::terminate_all_aliasing_chains):
	Likewise.
	(pass_store_merging::execute): Check for debug stmts first.
	Push new chains onto the m_stores_head stack.

From-SVN: r246213
      Alexandre Oliva committed
    • * decl.c (start_enum): std::byte aliases anything. · 2e92d7ad 
      From-SVN: r246212
      Jason Merrill committed
    • * init.c (cpp_init_builtins): Update __cplusplus for C++17. · 85e653c9 
      From-SVN: r246211
      Jason Merrill committed
    • re PR c++/79797 (ICE with NSDMI, this pointer and constexpr) · fbd603c4 
      	PR c++/79797
	* constexpr.c (lookup_placeholder): Tweak.

From-SVN: r246210
      Jason Merrill committed
    • re PR target/71294 (ICE in gen_add2_insn, at optabs.c:4442 on powerpc64le-linux) · 207f3423 
      [gcc]
2017-03-16  Michael Meissner  <meissner@linux.vnet.ibm.com>

	PR target/71294
	* config/rs6000/vsx.md (vsx_splat_<mode>, VSX_D iterator): Allow a
	SPLAT operation on ISA 2.07 64-bit systems that have direct move,
	but no MTVSRDD support, by doing MTVSRD and XXPERMDI.

[gcc/testsuite]
2017-03-16  Michael Meissner  <meissner@linux.vnet.ibm.com>

	PR target/71294
	* g++.dg/pr71294.C: New test.

From-SVN: r246209
      Michael Meissner committed
    • re PR tree-optimization/71437 (Performance regression after r235817) · c8755022 
      	PR tree-optimization/71437
	* tree-ssa-dom.c (dom_opt_dom_walker): Remove thread_across_edge
	member function.  Implementation moved into after_dom_children
	member function and into the threader's thread_outgoing_edges
	function.
	(dom_opt_dom_walker::after_dom_children): Simplify by moving
	some code into new thread_outgoing_edges.
	* tree-ssa-threadedge.c (thread_across_edge): Make static and simplify
	definition.  Simplify marker handling (do it here).   Assume we always
	have the available expression and the const/copies tables.
	(thread_outgoing_edges): New function extracted from tree-ssa-dom.c
	and tree-vrp.c
	* tree-ssa-threadedge.h (thread_outgoing_edges): Declare.
	* tree-vrp.c (equiv_stack): No longer file scoped.
	(vrp_dom_walker): New class.
	(vrp_dom_walker::before_dom_children): New member function.
	(vrp_dom_walker::after_dom_children): Likewise.
	(identify_jump_threads):  Setup domwalker.  Use it rather than
	walking edges in a random order by hand.  Simplify setup/finalization.
	(finalize_jump_threads): Remove.
	(vrp_finalize): Do not call identify_jump_threads here.
	(execute_vrp): Do it here instead and call thread_through_all_blocks
	here too.

From-SVN: r246208
      Jeff Law committed