RISC-V documentation cleanups

A recent mailing list post about install.texi cleanup suggested I take a
look at ours, and there were a few problems:

 * No table of contents entries
 * Not alphabetically ordered
 * Missing a note about requiring binutils-2.28

gcc/ChangeLog:

2017-03-17  Palmer Dabbelt  <palmer@dabbelt.com

        * doc/install.texi (Specific) <riscv32-*-elf>: Add riscv32-*-elf,
        riscv32-*-linux, riscv64-*-elf, riscv64-*-linux to the table of
        contents.
        <riscv64-*-elf>: Re-arrange section
        <riscv32-*-elf>: Add a note about requiring binutils 2.28.
        <riscv32-*-linux>: Likewise.
        <riscv64-*-elf>: Likewise
        <riscv64-*-linux>: Likewise.

From-SVN: r246243

gcc/ChangeLog

+2017-03-17  Palmer Dabbelt  <palmer@dabbelt.com
+
+	* doc/install.texi (Specific) <riscv32-*-elf>: Add riscv32-*-elf,
+	riscv32-*-linux, riscv64-*-elf, riscv64-*-linux to the table of
+	contents.
+	<riscv64-*-elf>: Re-arrange section
+	<riscv32-*-elf>: Add a note about requiring binutils 2.28.
+	<riscv32-*-linux>: Likewise.
+	<riscv64-*-elf>: Likewise
+	<riscv64-*-linux>: Likewise.
+
 2017-03-17  Richard Earnshaw  <rearnsha@arm.com>
 
 	PR target/80052

gcc/doc/install.texi

@@ -3211,6 +3211,14 @@ information have to.
 @item
 @uref{#powerpcle-x-eabi,,powerpcle-*-eabi}
 @item
+@uref{#riscv32-x-elf,,riscv32-*-elf}
+@item
+@uref{#riscv32-x-linux,,riscv32-*-linux}
+@item
+@uref{#riscv64-x-elf,,riscv64-*-elf}
+@item
+@uref{#riscv64-x-linux,,riscv64-*-linux}
+@item
 @uref{#s390-x-linux,,s390-*-linux*}
 @item
 @uref{#s390x-x-linux,,s390x-*-linux*}
@@ -4286,21 +4294,27 @@ This configuration is intended for embedded systems.
 @heading riscv32-*-elf
 The RISC-V RV32 instruction set.
 This configuration is intended for embedded systems.
+This (and all other RISC-V) targets are supported upstream as of the
+binutils 2.28 release.
 
 @html
 <hr />
 @end html
-@anchor{riscv64-x-elf}
-@heading riscv64-*-elf
-The RISC-V RV64 instruction set.
-This configuration is intended for embedded systems.
+@anchor{riscv32-x-linux}
+@heading riscv32-*-linux
+The RISC-V RV32 instruction set running GNU/Linux.
+This (and all other RISC-V) targets are supported upstream as of the
+binutils 2.28 release.
 
 @html
 <hr />
 @end html
-@anchor{riscv32-x-linux}
-@heading riscv32-*-linux
-The RISC-V RV32 instruction set running GNU/Linux.
+@anchor{riscv64-x-elf}
+@heading riscv64-*-elf
+The RISC-V RV64 instruction set.
+This configuration is intended for embedded systems.
+This (and all other RISC-V) targets are supported upstream as of the
+binutils 2.28 release.
 
 @html
 <hr />
@@ -4308,6 +4322,8 @@ The RISC-V RV32 instruction set running GNU/Linux.
 @anchor{riscv64-x-linux}
 @heading riscv64-*-linux
 The RISC-V RV64 instruction set running GNU/Linux.
+This (and all other RISC-V) targets are supported upstream as of the
+binutils 2.28 release.
 
 @html
 <hr />