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  1. 18 Dec, 2019 26 commits
  3. 17 Dec, 2019 14 commits
    • PR c++/61339 - add warning for mismatch between struct and class · e8f1ade2 
      gcc/c-family/ChangeLog:

	PR c++/61339
	* c.opt (-Wmismatched-tags, -Wredundant-tags): New options.

gcc/cp/ChangeLog:

	PR c++/61339
	* parser.c (cp_parser_maybe_warn_enum_key): New function.
	(class_decl_loc_t): New class.
	(cp_parser_elaborated_type_specifier): Call
	cp_parser_maybe_warn_enum_key.
	(cp_parser_class_head): Call cp_parser_check_class_key.
	(cp_parser_check_class_key): Add arguments.  Call class_decl_loc_t::add.
	(c_parse_file): Call class_decl_loc_t::diag_mismatched_tags.

gcc/testsuite/ChangeLog:

	PR c++/61339
	* g++.dg/warn/Wmismatched-tags.C: New test.
	* g++.dg/warn/Wredundant-tags.C: New test.
	* g++.dg/pch/Wmismatched-tags.C: New test.
	* g++.dg/pch/Wmismatched-tags.Hs: New test header.

gcc/ChangeLog:

	PR c++/61339
	* doc/invoke.texi (-Wmismatched-tags, -Wredundant-tags): Document
	new C++ options.

From-SVN: r279480
      Martin Sebor committed
    • Generate PADDI to add large constants if -mcpu=future. · 54ba911f 
      2019-12-12  Michael Meissner  <meissner@linux.ibm.com>

	* config/rs6000/predicates.md (add_operand): Allow eI constants.
	* config/rs6000/rs6000.md (add<mode>3): Add alternative to
	generate PADDI for 34-bit constants if -mcpu=future.

From-SVN: r279476
      Michael Meissner committed
    • Use PLI to load up 32-bit SImode constants if -mcpu=future. · ef759fd1 
      2019-12-17  Michael Meissner  <meissner@linux.ibm.com>

	* config/rs6000/rs6000.md (movsi_internal1): Add alternative to
	use PLI to load up 32-bit constants if -mcpu=future.

From-SVN: r279475
      Michael Meissner committed
    • Use PLI to load up large constants if -mcpu=future. · a50e0388 
      2019-12-17  Michael Meissner  <meissner@linux.ibm.com>

	* config/rs6000/rs6000.c (num_insns_constant_gpr): Return 1 if the
	constant can be loaded with PLI if -mcpu=future.
	* config/rs6000/rs6000.md (movdi_internal64): Add alternative to
	use PLI to load up 34-bit constants if -mcpu=future.

From-SVN: r279474
      Michael Meissner committed
    • PR c++/79592 - missing explanation of invalid constexpr. · 4f05d85a 
      We changed months back to use the pre-generic form for constexpr evaluation,
but explain_invalid_constexpr_fn was still using DECL_SAVED_TREE.  This
mostly works, but misses some issues due to folding.  So with this patch we
save the pre-generic form of constexpr functions even when we know they
can't produce a constant result.

	* constexpr.c (register_constexpr_fundef): Do store the body of a
	template instantiation that is not potentially constant.
	(explain_invalid_constexpr_fn): Look it up.
	(cxx_eval_call_expression): Check fundef->result.

From-SVN: r279473
      Jason Merrill committed
    • PR c++/92576 - redeclaration of variable template. · 9c7b2b0b 
      The variable templates patch way back when forgot to add handling here.  The
simplest answer seems to be recursing to the underlying declaration.

	* decl.c (redeclaration_error_message): Recurse for variable
	templates.

From-SVN: r279472
      Jason Merrill committed
    • * name-lookup.c (get_std_name_hint): Add std::byte. · 490a091f 
      From-SVN: r279471
      Jason Merrill committed
    • re PR c++/59655 (incorrect diagnostic on templatized function with lambda parameter) · 775670d7 
      	PR c++/59655
	* pt.c (push_tinst_level_loc): If limit_bad_template_recursion,
	set TREE_NO_WARNING on tldcl.
	* decl2.c (no_linkage_error): Treat templates with TREE_NO_WARNING
	as defined during error recovery.

	* g++.dg/cpp0x/diag3.C: New test.

From-SVN: r279470
      Jakub Jelinek committed
    • re PR target/92841 (Optimize -fstack-protector-strong code generation a bit) · 7c32b0d5 
      	PR target/92841
	* config/i386/i386.md (@stack_protect_set_1_<mode>,
	@stack_protect_test_1_<mode>): Use output_asm_insn.
	(*stack_protect_set_2_<mode>, *stack_protect_set_3): New define_insns
	and corresponding define_peephole2s.

	* gcc.target/i386/pr92841.c: New test.

From-SVN: r279468
      Jakub Jelinek committed
    • Revert "Fix vector testcases for amdgcn." · 7ec85098 
      Apologies everyone. :-(

From-SVN: r279466
      Andrew Stubbs committed
    • Fix vector testcases for amdgcn. · 62064ec0 
      2019-12-17  Andrew Stubbs  <ams@codesourcery.com>

	gcc/testsuite/
	* gcc.dg/vect/pr65947-8.c: Change pass conditions for amdgcn.
	* gcc.dg/vect/vect-multitypes-11.c: Ensure that main isn't vectorized.
	* gcc.dg/vect/vect-multitypes-12.c: Likewise.

From-SVN: r279465
      Andrew Stubbs committed
    • symtab.c (symtab_node::get_partitioning_class): Aliases of external symbols are external. · 634c5bca 
      	* symtab.c (symtab_node::get_partitioning_class): Aliases of external
	symbols are external.

From-SVN: r279464
      Jan Hubicka committed
    • [ARM] Add support for -mpure-code in thumb-1 (v6m) · e24f6408 
      This patch extends support for -mpure-code to all thumb-1 processors,
by removing the need for MOVT.

Symbol addresses are built using upper8_15, upper0_7, lower8_15 and
lower0_7 relocations, and constants are built using sequences of
movs/adds and lsls instructions.

The extension of the *thumb1_movhf pattern uses always the same size
(6) although it can emit a shorter sequence when possible. This is
similar to what *arm32_movhf already does.

CASE_VECTOR_PC_RELATIVE is now false with -mpure-code, to avoid
generating invalid assembly code with differences from symbols from
two different sections (the difference cannot be computed by the
assembler).

Tests pr45701-[12].c needed a small adjustment to avoid matching
upper8_15 when looking for the r8 register.

Test no-literal-pool.c is augmented with __fp16, so it now uses
-mfp16-format=ieee.

Test thumb1-Os-mult.c generates an inline code sequence with
-mpure-code and computes the multiplication by using a sequence of
add/shift rather than using the multiply instruction, so we skip it in
presence of -mpure-code.

With -mcpu=cortex-m0, the pure-code/no-literal-pool.c fails because
code like:
static char *p = "Hello World";
char *
testchar ()
{
  return p + 4;
}

generates 2 indirections (I removed non-essential directives/code)
          .section        .rodata
	  .LC0:
	  .ascii  "Hello World\000"
	  .data
	  p:
	  .word   .LC0
	  .section        .rodata
	  .LC2:
	  .word   p
	  .section .text,"0x20000006",%progbits
	  testchar:
	  push    {r7, lr}
	  add     r7, sp, #0
	  movs    r3, #:upper8_15:#.LC2
	  lsls    r3, #8
	  adds    r3, #:upper0_7:#.LC2
	  lsls    r3, #8
	  adds    r3, #:lower8_15:#.LC2
	  lsls    r3, #8
	  adds    r3, #:lower0_7:#.LC2
	  ldr     r3, [r3]
	  ldr     r3, [r3]
	  adds    r3, r3, #4
	  movs    r0, r3
	  mov     sp, r7
	  @ sp needed
	  pop     {r7, pc}

By contrast, when using -mcpu=cortex-m4, the code looks like:
        .section        .rodata
	.LC0:
	.ascii  "Hello World\000"
	.data
	p:
	.word   .LC0
	testchar:
	push    {r7}
	add     r7, sp, #0
	movw    r3, #:lower16:p
	movt    r3, #:upper16:p
	ldr     r3, [r3]
	adds    r3, r3, #4
	mov     r0, r3
	mov     sp, r7
	pop     {r7}
	bx      lr

I haven't found yet how to make code for cortex-m0 apply upper/lower
relocations to "p" instead of .LC2. The current code looks functional,
but could be improved.

2019-10-18  Christophe Lyon  <christophe.lyon@linaro.org>

	gcc/
	* config/arm/arm-protos.h (thumb1_gen_const_int): Add new prototype.
	* config/arm/arm.c (arm_option_check_internal): Remove restriction
	on MOVT for -mpure-code.
	(thumb1_gen_const_int): New function.
	(thumb1_legitimate_address_p): Support -mpure-code.
	(thumb1_rtx_costs): Likewise.
	(thumb1_size_rtx_costs): Likewise.
	(arm_thumb1_mi_thunk): Likewise.
	* config/arm/arm.h (CASE_VECTOR_PC_RELATIVE): Likewise.
	* config/arm/thumb1.md (thumb1_movsi_symbol_ref): New.
	(*thumb1_movhf): Support -mpure-code.

	gcc/testsuite/
	* gcc.target/arm/pr45701-1.c: Adjust for -mpure-code.
	* gcc.target/arm/pr45701-2.c: Likewise.
	* gcc.target/arm/pure-code/no-literal-pool.c: Add tests for
	__fp16.
	* gcc.target/arm/pure-code/pure-code.exp: Remove thumb2 and movt
	conditions.
	* gcc.target/arm/thumb1-Os-mult.c: Skip if -mpure-code is used.

From-SVN: r279463
      Christophe Lyon committed
    • Add myself to write after approval. · 6226f592 
      2019-12-17  Mihail Ionescu  <mihail.ionescu@arm.com>

	* MAINTAINERS (write_after_approval): Add myself.

From-SVN: r279461
      Mihail Ionescu committed