* gcc.dg/localalias-2.c: Guard by require-alias.
	* gcc.dg/globalalias-2.c: Likewise.

From-SVN: r211926

	* varpool.c (dump_varpool_node): Dump used_by_single_function.
	* tree-pass.h (make_pass_ipa_single_use): New pass.
	* cgraph.h (used_by_single_function): New flag.
	* lto-cgraph.c (lto_output_varpool_node, input_varpool_node): Stream
	it.
	* passes.def (pass_ipa_single_use): Scedule.
	* ipa.c (BOTTOM): New macro.
	(meet): New function
	(propagate_single_user): New function.
	(ipa_single_use): New function.
	(pass_data_ipa_single_use): New pass.
	(pass_ipa_single_use): New pass.
	(pass_ipa_single_use::gate): New gate.
	(make_pass_ipa_single_use): New function.

From-SVN: r211925

From-SVN: r211924

	* include/experimental/any (any_v1): Rename namespace to
	fundamentals_v1. Change string returned by bad_any_cast::what().
	* include/experimental/optional (fundamentals_v1): Add namespace.
	* include/experimental/string_view (fundamentals_v1): Likewise.
	* testsuite/experimental/any/typedefs.cc: New.
	* testsuite/experimental/optional/typedefs.cc: New.
	* testsuite/experimental/string_view/typedefs.cc: New.

From-SVN: r211920

        PR target/39284
        * passes.def (peephole2): Move peephole2 pass before
        before sched2 pass.
        * config/i386/i386.md (peehole2): Combine memories
        and indirect jumps.

From-SVN: r211919

From-SVN: r211918

2014-06-23  Andrew Pinski  <apinski@cavium.com>

	* gcc.c-torture/compile/20140723-1.c: New testcase.

From-SVN: r211917

This reverts commit ed8c02da028fb10d25a682e1838ba8b23a2c34ff.

From-SVN: r211915

2014-06-23  Bernd Edlinger  <bernd.edlinger@hotmail.de>

        Fix include path for in-tree cloog.
        * config/cloog.m4 (CLOOG_INIT_FLAGS): Remove bogus include path.
        * configure: Regenerate.

P.S: moved a few ChangeLog entries to gcc/ChangeLog

From-SVN: r211913

2014-06-23  Paolo Carlini  <paolo.carlini@oracle.com>

	* sanitizer_common/sanitizer_common_interceptors.inc:
	Cherry pick upstream r211008.

From-SVN: r211912

2014-06-23  Paul Gortmaker  <paul.gortmaker@windriver.com>

        * gcc.c (set_multilib_dir): Fix typo.

From-SVN: r211911

	PR c/61553
	* c-c++-common/pr61553.c (foo): Add dg-error.

From-SVN: r211910

re PR libstdc++/61532 (make_signed and make_unsigned wchar_t have started failing in the libstdc++ testsuite.)

	PR libstdc++/61532
	* testsuite/20_util/make_signed/requirements/typedefs-1.cc: Do not
	apply the signed specifier to wchar_t.
	* testsuite/20_util/make_signed/requirements/typedefs-2.cc: Likewise.
	* testsuite/20_util/make_unsigned/requirements/typedefs-1.cc: Check
	cv-qualifier and size.
	* testsuite/20_util/make_unsigned/requirements/typedefs-2.cc:
	Likewise.

From-SVN: r211909

gcc/fortran/
2014-06-23  Tobias Burnus  <burnus@net-b.de>

        * trans-decl.c (gfc_trans_deferred_vars): Fix handling of
        explicit-size arrays with -fcoarray=lib.

gcc/testsuite/
2014-06-23  Tobias Burnus  <burnus@net-b.de>

        * gfortran.dg/coarray_32.f90: New.

From-SVN: r211907

/cp
2014-06-23  Paolo Carlini  <paolo.carlini@oracle.com>

	DR 577
	PR c++/33101
	* decl.c (grokparms): Accept a single parameter of type 'void'.

/testsuite
2014-06-23  Paolo Carlini  <paolo.carlini@oracle.com>

	DR 577
	PR c++/33101
	* g++.dg/other/void1.C: Adjust.
	* g++.dg/other/void3.C: Likewise.

From-SVN: r211906

	PR c/61553
	* c-common.c (get_atomic_generic_size): Don't segfault if the
	type doesn't have a size.

	* c-c++-common/pr61553.c: New test.

Co-Authored-By: Andrew MacLeod <amacleod@redhat.com>

From-SVN: r211905

2014-06-23  Richard Biener  <rguenther@suse.de>

	* tree-ssa-loop.c (gate_loop): New function.
	(pass_tree_loop::gate): Call it.
	(pass_data_tree_no_loop, pass_tree_no_loop,
	make_pass_tree_no_loop): New.
	* tree-vectorizer.c: Include tree-scalar-evolution.c
	(pass_slp_vectorize::execute): Initialize loops and SCEV if
	required.
	(pass_slp_vectorize::clone): New method.
	* timevar.def (TV_TREE_NOLOOP): New.
	* tree-pass.h (make_pass_tree_no_loop): Declare.
	* passes.def (pass_tree_no_loop): New pass group with
	SLP vectorizer.

	* g++.dg/vect/slp-pr50413.cc: Scan and cleanup appropriate SLP dumps.
	* g++.dg/vect/slp-pr50819.cc: Likewise.
	* g++.dg/vect/slp-pr56812.cc: Likewise.
	* gcc.dg/vect/bb-slp-1.c: Likewise.
	* gcc.dg/vect/bb-slp-10.c: Likewise.
	* gcc.dg/vect/bb-slp-11.c: Likewise.
	* gcc.dg/vect/bb-slp-13.c: Likewise.
	* gcc.dg/vect/bb-slp-14.c: Likewise.
	* gcc.dg/vect/bb-slp-15.c: Likewise.
	* gcc.dg/vect/bb-slp-16.c: Likewise.
	* gcc.dg/vect/bb-slp-17.c: Likewise.
	* gcc.dg/vect/bb-slp-18.c: Likewise.
	* gcc.dg/vect/bb-slp-19.c: Likewise.
	* gcc.dg/vect/bb-slp-2.c: Likewise.
	* gcc.dg/vect/bb-slp-20.c: Likewise.
	* gcc.dg/vect/bb-slp-21.c: Likewise.
	* gcc.dg/vect/bb-slp-22.c: Likewise.
	* gcc.dg/vect/bb-slp-23.c: Likewise.
	* gcc.dg/vect/bb-slp-24.c: Likewise.
	* gcc.dg/vect/bb-slp-25.c: Likewise.
	* gcc.dg/vect/bb-slp-26.c: Likewise.
	* gcc.dg/vect/bb-slp-27.c: Likewise.
	* gcc.dg/vect/bb-slp-28.c: Likewise.
	* gcc.dg/vect/bb-slp-29.c: Likewise.
	* gcc.dg/vect/bb-slp-3.c: Likewise.
	* gcc.dg/vect/bb-slp-30.c: Likewise.
	* gcc.dg/vect/bb-slp-31.c: Likewise.
	* gcc.dg/vect/bb-slp-32.c: Likewise.
	* gcc.dg/vect/bb-slp-4.c: Likewise.
	* gcc.dg/vect/bb-slp-5.c: Likewise.
	* gcc.dg/vect/bb-slp-6.c: Likewise.
	* gcc.dg/vect/bb-slp-7.c: Likewise.
	* gcc.dg/vect/bb-slp-8.c: Likewise.
	* gcc.dg/vect/bb-slp-8a.c: Likewise.
	* gcc.dg/vect/bb-slp-8b.c: Likewise.
	* gcc.dg/vect/bb-slp-9.c: Likewise.
	* gcc.dg/vect/bb-slp-cond-1.c: Likewise.
	* gcc.dg/vect/bb-slp-pattern-1.c: Likewise.
	* gcc.dg/vect/bb-slp-pattern-2.c: Likewise.
	* gcc.dg/vect/fast-math-bb-slp-call-1.c: Likewise.
	* gcc.dg/vect/fast-math-bb-slp-call-2.c: Likewise.
	* gcc.dg/vect/fast-math-bb-slp-call-3.c: Likewise.
	* gcc.dg/vect/no-tree-reassoc-bb-slp-12.c: Likewise.
	* gcc.dg/vect/no-tree-sra-bb-slp-pr50730.c: Likewise.
	* gcc.dg/vect/pr26359.c: Likewise.
	* gcc.dg/vect/costmodel/ppc/costmodel-bb-slp-9a.c: Likewise.

From-SVN: r211904

c-typeck.c (parser_build_binary_op): Don't call warn_logical_not_parentheses if the RHS is TRUTH_NOT_EXPR.

	* c-typeck.c (parser_build_binary_op): Don't call
	warn_logical_not_parentheses if the RHS is TRUTH_NOT_EXPR.

	* c-c++-common/pr49706-2.c: New test.

From-SVN: r211902

	PR target/61570
	* config/i386/driver-i386.c (host_detect_local_cpu): Set arch
	to x86-64 if a 32-bit processor supports SSE2 and 64-bit.

From-SVN: r211901

	PR libgcc/61585
	* unwind-seh.c (_Unwind_GetGR): Check for proper
	index range.
	(_Unwind_SetGR): Likewise.

From-SVN: r211900

gcc/

	* config/aarch64/aarch64.md (addsi3_aarch64): Set "simd" attr to
	"yes" where needed.

From-SVN: r211899

gcc/
	PR bootstrap/61583
	* tree-vrp.c (remove_range_assertions): Do not set is_unreachable
	to zero on debug statements.
gcc/testsuite/
	* gcc.dg/pr61583.c: New.

From-SVN: r211897

gcc/ChangeLog:
 	PR target/60825
	* config/aarch64/aarch64-builtins.c (aarch64_types_unop_qualifiers):
	Ignore third operand if present by marking qualifier_internal.

	* config/aarch64/aarch64-simd-builtins.def (abs): Comment.

	* config/aarch64/arm_neon.h (int64x1_t, uint64x1_t): Typedef to GCC
	vector extension.
	(aarch64_vget_lane_s64, aarch64_vdup_lane_s64,
	arch64_vdupq_lane_s64, aarch64_vdupq_lane_u64): Remove macro.
	(vqadd_s64, vqadd_u64, vqsub_s64, vqsub_u64, vqneg_s64, vqabs_s64,
	vcreate_s64, vcreate_u64, vreinterpret_s64_f64, vreinterpret_u64_f64,
	vcombine_u64, vbsl_s64, vbsl_u64, vceq_s64, vceq_u64, vceqz_s64,
	vceqz_u64, vcge_s64, vcge_u64, vcgez_s64, vcgt_s64, vcgt_u64,
	vcgtz_s64, vcle_s64, vcle_u64, vclez_s64, vclt_s64, vclt_u64,
	vcltz_s64, vdup_n_s64, vdup_n_u64, vld1_s64, vld1_u64, vmov_n_s64,
	vmov_n_u64, vqdmlals_lane_s32, vqdmlsls_lane_s32,
	vqdmulls_lane_s32, vqrshl_s64, vqrshl_u64, vqrshl_u64, vqshl_s64,
	vqshl_u64, vqshl_n_s64, vqshl_n_u64, vqshl_n_s64, vqshl_n_u64,
	vqshlu_n_s64, vrshl_s64, vrshl_u64, vrshr_n_s64, vrshr_n_u64,
	vrsra_n_s64, vrsra_n_u64, vshl_n_s64, vshl_n_u64, vshl_s64,
	vshl_u64, vshr_n_s64, vshr_n_u64, vsli_n_s64, vsli_n_u64,
	vsqadd_u64, vsra_n_s64, vsra_n_u64, vsri_n_s64, vsri_n_u64,
	vst1_s64, vst1_u64, vtst_s64, vtst_u64, vuqadd_s64): Wrap existing
	logic in GCC vector extensions
	
	(vpaddd_s64, vaddd_s64, vaddd_u64, vceqd_s64, vceqd_u64, vceqzd_s64
	vceqzd_u64, vcged_s64, vcged_u64, vcgezd_s64, vcgtd_s64, vcgtd_u64,
	vcgtzd_s64, vcled_s64, vcled_u64, vclezd_s64, vcltd_s64, vcltd_u64,
	vcltzd_s64, vqdmlals_s32, vqdmlsls_s32, vqmovnd_s64, vqmovnd_u64
	vqmovund_s64, vqrshld_s64, vqrshld_u64, vqrshrnd_n_s64,
	vqrshrnd_n_u64, vqrshrund_n_s64, vqshld_s64, vqshld_u64,
	vqshld_n_u64, vqshrnd_n_s64, vqshrnd_n_u64, vqshrund_n_s64,
	vrshld_u64, vrshrd_n_u64, vrsrad_n_u64, vshld_n_u64, vshld_s64,
	vshld_u64, vslid_n_u64, vsqaddd_u64, vsrad_n_u64, vsrid_n_u64,
	vsubd_s64, vsubd_u64, vtstd_s64, vtstd_u64): Fix type signature.

	(vabs_s64): Use GCC vector extensions; call __builtin_aarch64_absdi.

	(vget_high_s64, vget_high_u64): Reimplement with GCC vector
	extensions.

	(__GET_LOW, vget_low_u64): Wrap result using vcreate_u64.
	(vget_low_s64): Use __GET_LOW macro.
	(vget_lane_s64, vget_lane_u64, vdupq_lane_s64, vdupq_lane_u64): Use
	gcc vector extensions, add call to __builtin_aarch64_lane_boundsi.
	(vdup_lane_s64, vdup_lane_u64,): Add __builtin_aarch64_lane_bound_si.
	(vdupd_lane_s64, vdupd_lane_u64): Fix type signature, add
	__builtin_aarch64_lane_boundsi, use GCC vector extensions.

	(vcombine_s64): Use GCC vector extensions; remove cast.
	(vqaddd_s64, vqaddd_u64, vqdmulls_s32, vqshld_n_s64, vqshlud_n_s64,
	vqsubd_s64, vqsubd_u64, vrshld_s64, vrshrd_n_s64, vrsrad_n_s64,
	vshld_n_s64, vshrd_n_s64, vslid_n_s64, vsrad_n_s64, vsrid_n_s64):
	Fix type signature; remove cast.

gcc/testsuite/ChangeLog:
	* g++.dg/abi/mangle-neon-aarch64.C (f22, f23): New tests of 
	[u]int64x1_t.

	* gcc.target/aarch64/aapcs64/func-ret-64x1_1.c: Add {u,}int64x1 cases.
	* gcc.target/aarch64/aapcs64/test_64x1_1.c: Likewise.

	* gcc.target/aarch64/scalar_intrinsics.c (test_vaddd_u64,
	test_vaddd_s64, test_vceqd_s64, test_vceqzd_s64, test_vcged_s64,
	test_vcled_s64, test_vcgezd_s64, test_vcged_u64, test_vcgtd_s64,
	test_vcltd_s64, test_vcgtzd_s64, test_vcgtd_u64, test_vclezd_s64,
	test_vcltzd_s64, test_vqaddd_u64, test_vqaddd_s64, test_vqdmlals_s32,
	test_vqdmlsls_s32, test_vqdmulls_s32, test_vuqaddd_s64,
	test_vsqaddd_u64, test_vqmovund_s64, test_vqmovnd_s64,
	test_vqmovnd_u64, test_vsubd_u64, test_vsubd_s64, test_vqsubd_u64,
	test_vqsubd_s64, test_vshld_s64, test_vshld_u64, test_vrshld_s64,
	test_vrshld_u64, test_vshrd_n_s64, test_vshrd_n_u64, test_vsrad_n_s64,
	test_vsrad_n_u64, test_vrshrd_n_s64, test_vrshrd_n_u64,
	test_vrsrad_n_s64, test_vrsrad_n_u64, test_vqrshld_s64,
	test_vqrshld_u64, test_vqshlud_n_s64, test_vqshld_s64, test_vqshld_u64,
	test_vqshld_n_u64, test_vqshrund_n_s64, test_vqrshrund_n_s64,
	test_vqshrnd_n_s64, test_vqshrnd_n_u64, test_vqrshrnd_n_s64,
	test_vqrshrnd_n_u64, test_vshld_n_s64, test_vshdl_n_u64,
	test_vslid_n_s64, test_vslid_n_u64, test_vsrid_n_s64,
	test_vsrid_n_u64): Fix signature to match intrinsic.
	
	(test_vabs_s64): Remove.
	(test_vaddd_s64_2, test_vsubd_s64_2): Use force_simd.

	(test_vdupd_lane_s64): Rename to...
	(test_vdupd_laneq_s64): ...and remove a call to force_simd.

	(test_vdupd_lane_u64): Rename to...
	(test_vdupd_laneq_u64): ...and remove a call to force_simd.

	(test_vtst_s64): Rename to...
	(test_vtstd_s64): ...and change int64x1_t to int64_t.

	(test_vtst_u64): Rename to...
	(test_vtstd_u64): ...and change uint64x1_t to uint64_t.

	* gcc.target/aarch64/singleton_intrinsics_1.c: New file.
	* gcc.target/aarch64/vdup_lane_1.c, gcc.target/aarch64/vdup_lane_2.c:
	Remove out-of-bounds tests.
	* gcc.target/aarch64/vneg_s.c (INDEX*, RUN_TEST): Remove INDEX macro.

From-SVN: r211894

gcc/ChangeLog:
	PR target/60825
	* config/aarch64/aarch64.c (aarch64_simd_mangle_map): Add entry for
	V1DFmode.
	* config/aarch64/aarch64-builtins.c (aarch64_simd_builtin_type_mode):
	add V1DFmode
	(BUILTIN_VD1): New.
	(BUILTIN_VD_RE): Remove.
	(aarch64_init_simd_builtins): Add V1DF to modes/modenames.
	(aarch64_fold_builtin): Update reinterpret patterns, df becomes v1df.
	* config/aarch64/aarch64-simd-builtins.def (create): Make a v1df
	variant but not df.
	(vreinterpretv1df*, vreinterpret*v1df): New.
	(vreinterpretdf*, vreinterpret*df): Remove.
	* config/aarch64/aarch64-simd.md (aarch64_create, aarch64_reinterpret*):
	Generate V1DFmode pattern not DFmode.
	* config/aarch64/iterators.md (VD_RE): Include V1DF, remove DF.
	(VD1): New.
	* config/aarch64/arm_neon.h (float64x1_t): typedef with gcc extensions.
	(vcreate_f64): Remove cast, use v1df builtin.
	(vcombine_f64): Remove cast, get elements with gcc vector extensions.
	(vget_low_f64, vabs_f64, vceq_f64, vceqz_f64, vcge_f64, vgfez_f64,
	vcgt_f64, vcgtz_f64, vcle_f64, vclez_f64, vclt_f64, vcltz_f64,
	vdup_n_f64, vdupq_lane_f64, vld1_f64, vld2_f64, vld3_f64, vld4_f64,
	vmov_n_f64, vst1_f64): Use gcc vector extensions.
	(vget_lane_f64, vdupd_lane_f64, vmulq_lane_f64, ): Use gcc extensions,
	add range check using __builtin_aarch64_im_lane_boundsi.
	(vfma_lane_f64, vfmad_lane_f64, vfma_laneq_f64, vfmaq_lane_f64,
	vfms_lane_f64, vfmsd_lane_f64, vfms_laneq_f64, vfmsq_lane_f64): Fix
	type signature, use gcc vector extensions.
	(vreinterpret_p8_f64, vreinterpret_p16_f64, vreinterpret_f32_f64,
	vreinterpret_f64_f32, vreinterpret_f64_p8, vreinterpret_f64_p16,
	vreinterpret_f64_s8, vreinterpret_f64_s16, vreinterpret_f64_s32,
	vreinterpret_f64_s64, vreinterpret_f64_u8, vreinterpret_f64_u16,
	vreinterpret_f64_u32, vreinterpret_f64_u64, vreinterpret_s8_f64,
	vreinterpret_s16_f64, vreinterpret_s32_f64, vreinterpret_s64_f64,
	vreinterpret_u8_f64, vreinterpret_u16_f64, vreinterpret_u32_f64,
	vreinterpret_u64_f64): Use v1df builtin not df.

gcc/testsuite/ChangeLog:
	* g++.dg/abi/mangle-neon-aarch64.C: Also test mangling of float64x1_t.
	* gcc.target/aarch64/aapcs/test_64x1_1.c: New test.
	* gcc.target/aarch64/aapcs/func-ret-64x1_1.c: New test.
	* gcc.target/aarch64/simd/ext_f64_1.c (main): Compare vector elements.
	* gcc.target/aarch64/vadd_f64.c: Rewrite with macro to use vector types.
	* gcc.target/aarch64/vsub_f64.c: Likewise.
	* gcc.target/aarch64/vdiv_f.c (INDEX*, RUN_TEST): Remove indexing scheme
	as now the same for all variants.
	* gcc.target/aarch64/vrnd_f64_1.c (compare_f64): Return float64_t not
	float64x1_t.

From-SVN: r211892

	* include/bits/parse_numbers.h (_Number_help): Fix divide-by-zero.
	* include/std/chrono (_Checked_integral_constant): Allow zero.
	* testsuite/20_util/duration/literals/values.cc: Test non-positive
	values and digit separators.

From-SVN: r211890

gcc/

	* config/aarch64/aarch64.md (*addsi3_aarch64): Add alternative in
	vector registers.

gcc/testsuite/

	* gcc.target/aarch64/scalar_shift_1.c: Fix expected assembler.

From-SVN: r211887

	* lto-cgraph.c (lto_output_node, input_node): Set/get init/fini priority
	directly.

From-SVN: r211886

2014-06-23  Zhenqiang Chen  <zhenqiang.chen@linaro.org>

	* loop-invariant.c (pre_check_invariant_p): New function.
	(find_invariant_insn): Call pre_check_invariant_p.

From-SVN: r211885

From-SVN: r211884

PR target/61565

* compare-elim.c (struct comparison): Add eh_note.
(find_comparison_dom_walker::before_dom_children): Don't eliminate
a redundant comparison in a different EH region.  Purge EH edges if
necessary.

From-SVN: r211881

All instructions that are "var_shift" for some alternative have the shift
amount as operands[2].

This patch introduces an attribute "maybe_var_shift".  If that is set to
"yes", the default value of "var_shift" is set based on the operands[2]
value.

With that, we can merge the var_shift yes/no cases everywhere.  Do so.

Also change some more "i" to "n".

From-SVN: r211880

From-SVN: r211879

This uses the rotl* extended mnemonics instead of the rlw*nm and rld*cl
mnemonics, because they are shorter and more importantly they look the
same for 32-bit and 64-bit.

From-SVN: r211878

From-SVN: r211877

For this create a new mode_attr "hH".

Also change "i" constraints on the shift amount to "n", which better
describes what it really is (GCC takes the integer value of these
operands and does arithmetic on them; symbolic constants will not work
here).

Also merge the "dot" insns with the corresponding splitters.  To do
this, don't allow the dot insns for CBE non-microcode mode at all
(it previously would just split it back always).

From-SVN: r211876

Nothing will ever generate RTL matching this alternative.  Maybe long
ago this was needed, but not anymore.

From-SVN: r211875

gcc/
	* config/mips/mips.c (mips_move_to_gpr_cost): Remove mode argument.
	(mips_move_from_gpr_cost): Likewise.
	(mips_register_move_cost): Update accordingly.
	(mips_secondary_reload_class): Remove name of in_p.

From-SVN: r211874

2014-06-22  Marc Glisse  <marc.glisse@inria.fr>

	PR target/61503
	* config/i386/i386.md (x86_64_shrd, x86_shrd,
	ix86_rotr<dwi>3_doubleword): Replace ashiftrt with lshiftrt.

From-SVN: r211873

From-SVN: r211872

	* gcc.dg/localalias.c: Fix broken commit.
	* gcc.dg/globalalias.c: Likewise.

From-SVN: r211869