PR/60825 Make {int,uint}64x1_t in arm_neon.h a proper vector type

gcc/ChangeLog:
 	PR target/60825
	* config/aarch64/aarch64-builtins.c (aarch64_types_unop_qualifiers):
	Ignore third operand if present by marking qualifier_internal.

	* config/aarch64/aarch64-simd-builtins.def (abs): Comment.

	* config/aarch64/arm_neon.h (int64x1_t, uint64x1_t): Typedef to GCC
	vector extension.
	(aarch64_vget_lane_s64, aarch64_vdup_lane_s64,
	arch64_vdupq_lane_s64, aarch64_vdupq_lane_u64): Remove macro.
	(vqadd_s64, vqadd_u64, vqsub_s64, vqsub_u64, vqneg_s64, vqabs_s64,
	vcreate_s64, vcreate_u64, vreinterpret_s64_f64, vreinterpret_u64_f64,
	vcombine_u64, vbsl_s64, vbsl_u64, vceq_s64, vceq_u64, vceqz_s64,
	vceqz_u64, vcge_s64, vcge_u64, vcgez_s64, vcgt_s64, vcgt_u64,
	vcgtz_s64, vcle_s64, vcle_u64, vclez_s64, vclt_s64, vclt_u64,
	vcltz_s64, vdup_n_s64, vdup_n_u64, vld1_s64, vld1_u64, vmov_n_s64,
	vmov_n_u64, vqdmlals_lane_s32, vqdmlsls_lane_s32,
	vqdmulls_lane_s32, vqrshl_s64, vqrshl_u64, vqrshl_u64, vqshl_s64,
	vqshl_u64, vqshl_n_s64, vqshl_n_u64, vqshl_n_s64, vqshl_n_u64,
	vqshlu_n_s64, vrshl_s64, vrshl_u64, vrshr_n_s64, vrshr_n_u64,
	vrsra_n_s64, vrsra_n_u64, vshl_n_s64, vshl_n_u64, vshl_s64,
	vshl_u64, vshr_n_s64, vshr_n_u64, vsli_n_s64, vsli_n_u64,
	vsqadd_u64, vsra_n_s64, vsra_n_u64, vsri_n_s64, vsri_n_u64,
	vst1_s64, vst1_u64, vtst_s64, vtst_u64, vuqadd_s64): Wrap existing
	logic in GCC vector extensions
	
	(vpaddd_s64, vaddd_s64, vaddd_u64, vceqd_s64, vceqd_u64, vceqzd_s64
	vceqzd_u64, vcged_s64, vcged_u64, vcgezd_s64, vcgtd_s64, vcgtd_u64,
	vcgtzd_s64, vcled_s64, vcled_u64, vclezd_s64, vcltd_s64, vcltd_u64,
	vcltzd_s64, vqdmlals_s32, vqdmlsls_s32, vqmovnd_s64, vqmovnd_u64
	vqmovund_s64, vqrshld_s64, vqrshld_u64, vqrshrnd_n_s64,
	vqrshrnd_n_u64, vqrshrund_n_s64, vqshld_s64, vqshld_u64,
	vqshld_n_u64, vqshrnd_n_s64, vqshrnd_n_u64, vqshrund_n_s64,
	vrshld_u64, vrshrd_n_u64, vrsrad_n_u64, vshld_n_u64, vshld_s64,
	vshld_u64, vslid_n_u64, vsqaddd_u64, vsrad_n_u64, vsrid_n_u64,
	vsubd_s64, vsubd_u64, vtstd_s64, vtstd_u64): Fix type signature.

	(vabs_s64): Use GCC vector extensions; call __builtin_aarch64_absdi.

	(vget_high_s64, vget_high_u64): Reimplement with GCC vector
	extensions.

	(__GET_LOW, vget_low_u64): Wrap result using vcreate_u64.
	(vget_low_s64): Use __GET_LOW macro.
	(vget_lane_s64, vget_lane_u64, vdupq_lane_s64, vdupq_lane_u64): Use
	gcc vector extensions, add call to __builtin_aarch64_lane_boundsi.
	(vdup_lane_s64, vdup_lane_u64,): Add __builtin_aarch64_lane_bound_si.
	(vdupd_lane_s64, vdupd_lane_u64): Fix type signature, add
	__builtin_aarch64_lane_boundsi, use GCC vector extensions.

	(vcombine_s64): Use GCC vector extensions; remove cast.
	(vqaddd_s64, vqaddd_u64, vqdmulls_s32, vqshld_n_s64, vqshlud_n_s64,
	vqsubd_s64, vqsubd_u64, vrshld_s64, vrshrd_n_s64, vrsrad_n_s64,
	vshld_n_s64, vshrd_n_s64, vslid_n_s64, vsrad_n_s64, vsrid_n_s64):
	Fix type signature; remove cast.

gcc/testsuite/ChangeLog:
	* g++.dg/abi/mangle-neon-aarch64.C (f22, f23): New tests of 
	[u]int64x1_t.

	* gcc.target/aarch64/aapcs64/func-ret-64x1_1.c: Add {u,}int64x1 cases.
	* gcc.target/aarch64/aapcs64/test_64x1_1.c: Likewise.

	* gcc.target/aarch64/scalar_intrinsics.c (test_vaddd_u64,
	test_vaddd_s64, test_vceqd_s64, test_vceqzd_s64, test_vcged_s64,
	test_vcled_s64, test_vcgezd_s64, test_vcged_u64, test_vcgtd_s64,
	test_vcltd_s64, test_vcgtzd_s64, test_vcgtd_u64, test_vclezd_s64,
	test_vcltzd_s64, test_vqaddd_u64, test_vqaddd_s64, test_vqdmlals_s32,
	test_vqdmlsls_s32, test_vqdmulls_s32, test_vuqaddd_s64,
	test_vsqaddd_u64, test_vqmovund_s64, test_vqmovnd_s64,
	test_vqmovnd_u64, test_vsubd_u64, test_vsubd_s64, test_vqsubd_u64,
	test_vqsubd_s64, test_vshld_s64, test_vshld_u64, test_vrshld_s64,
	test_vrshld_u64, test_vshrd_n_s64, test_vshrd_n_u64, test_vsrad_n_s64,
	test_vsrad_n_u64, test_vrshrd_n_s64, test_vrshrd_n_u64,
	test_vrsrad_n_s64, test_vrsrad_n_u64, test_vqrshld_s64,
	test_vqrshld_u64, test_vqshlud_n_s64, test_vqshld_s64, test_vqshld_u64,
	test_vqshld_n_u64, test_vqshrund_n_s64, test_vqrshrund_n_s64,
	test_vqshrnd_n_s64, test_vqshrnd_n_u64, test_vqrshrnd_n_s64,
	test_vqrshrnd_n_u64, test_vshld_n_s64, test_vshdl_n_u64,
	test_vslid_n_s64, test_vslid_n_u64, test_vsrid_n_s64,
	test_vsrid_n_u64): Fix signature to match intrinsic.
	
	(test_vabs_s64): Remove.
	(test_vaddd_s64_2, test_vsubd_s64_2): Use force_simd.

	(test_vdupd_lane_s64): Rename to...
	(test_vdupd_laneq_s64): ...and remove a call to force_simd.

	(test_vdupd_lane_u64): Rename to...
	(test_vdupd_laneq_u64): ...and remove a call to force_simd.

	(test_vtst_s64): Rename to...
	(test_vtstd_s64): ...and change int64x1_t to int64_t.

	(test_vtst_u64): Rename to...
	(test_vtstd_u64): ...and change uint64x1_t to uint64_t.

	* gcc.target/aarch64/singleton_intrinsics_1.c: New file.
	* gcc.target/aarch64/vdup_lane_1.c, gcc.target/aarch64/vdup_lane_2.c:
	Remove out-of-bounds tests.
	* gcc.target/aarch64/vneg_s.c (INDEX*, RUN_TEST): Remove INDEX macro.

From-SVN: r211894

gcc/ChangeLog

 2014-06-19  Alan Lawrence  <alan.lawrence@arm.com>
 
 	PR target/60825
+	* config/aarch64/aarch64-builtins.c (aarch64_types_unop_qualifiers):
+	Ignore third operand if present by marking qualifier_internal.
+
+	* config/aarch64/aarch64-simd-builtins.def (abs): Comment.
+
+	* config/aarch64/arm_neon.h (int64x1_t, uint64x1_t): Typedef to GCC
+	vector extension.
+	(aarch64_vget_lane_s64, aarch64_vdup_lane_s64,
+	arch64_vdupq_lane_s64, aarch64_vdupq_lane_u64): Remove macro.
+	(vqadd_s64, vqadd_u64, vqsub_s64, vqsub_u64, vqneg_s64, vqabs_s64,
+	vcreate_s64, vcreate_u64, vreinterpret_s64_f64, vreinterpret_u64_f64,
+	vcombine_u64, vbsl_s64, vbsl_u64, vceq_s64, vceq_u64, vceqz_s64,
+	vceqz_u64, vcge_s64, vcge_u64, vcgez_s64, vcgt_s64, vcgt_u64,
+	vcgtz_s64, vcle_s64, vcle_u64, vclez_s64, vclt_s64, vclt_u64,
+	vcltz_s64, vdup_n_s64, vdup_n_u64, vld1_s64, vld1_u64, vmov_n_s64,
+	vmov_n_u64, vqdmlals_lane_s32, vqdmlsls_lane_s32,
+	vqdmulls_lane_s32, vqrshl_s64, vqrshl_u64, vqrshl_u64, vqshl_s64,
+	vqshl_u64, vqshl_n_s64, vqshl_n_u64, vqshl_n_s64, vqshl_n_u64,
+	vqshlu_n_s64, vrshl_s64, vrshl_u64, vrshr_n_s64, vrshr_n_u64,
+	vrsra_n_s64, vrsra_n_u64, vshl_n_s64, vshl_n_u64, vshl_s64,
+	vshl_u64, vshr_n_s64, vshr_n_u64, vsli_n_s64, vsli_n_u64,
+	vsqadd_u64, vsra_n_s64, vsra_n_u64, vsri_n_s64, vsri_n_u64,
+	vst1_s64, vst1_u64, vtst_s64, vtst_u64, vuqadd_s64): Wrap existing
+	logic in GCC vector extensions
+	
+	(vpaddd_s64, vaddd_s64, vaddd_u64, vceqd_s64, vceqd_u64, vceqzd_s64
+	vceqzd_u64, vcged_s64, vcged_u64, vcgezd_s64, vcgtd_s64, vcgtd_u64,
+	vcgtzd_s64, vcled_s64, vcled_u64, vclezd_s64, vcltd_s64, vcltd_u64,
+	vcltzd_s64, vqdmlals_s32, vqdmlsls_s32, vqmovnd_s64, vqmovnd_u64
+	vqmovund_s64, vqrshld_s64, vqrshld_u64, vqrshrnd_n_s64,
+	vqrshrnd_n_u64, vqrshrund_n_s64, vqshld_s64, vqshld_u64,
+	vqshld_n_u64, vqshrnd_n_s64, vqshrnd_n_u64, vqshrund_n_s64,
+	vrshld_u64, vrshrd_n_u64, vrsrad_n_u64, vshld_n_u64, vshld_s64,
+	vshld_u64, vslid_n_u64, vsqaddd_u64, vsrad_n_u64, vsrid_n_u64,
+	vsubd_s64, vsubd_u64, vtstd_s64, vtstd_u64): Fix type signature.
+
+	(vabs_s64): Use GCC vector extensions; call __builtin_aarch64_absdi.
+
+	(vget_high_s64, vget_high_u64): Reimplement with GCC vector
+	extensions.
+
+	(__GET_LOW, vget_low_u64): Wrap result using vcreate_u64.
+	(vget_low_s64): Use __GET_LOW macro.
+	(vget_lane_s64, vget_lane_u64, vdupq_lane_s64, vdupq_lane_u64): Use
+	gcc vector extensions, add call to __builtin_aarch64_lane_boundsi.
+	(vdup_lane_s64, vdup_lane_u64,): Add __builtin_aarch64_lane_bound_si.
+	(vdupd_lane_s64, vdupd_lane_u64): Fix type signature, add
+	__builtin_aarch64_lane_boundsi, use GCC vector extensions.
+
+	(vcombine_s64): Use GCC vector extensions; remove cast.
+	(vqaddd_s64, vqaddd_u64, vqdmulls_s32, vqshld_n_s64, vqshlud_n_s64,
+	vqsubd_s64, vqsubd_u64, vrshld_s64, vrshrd_n_s64, vrsrad_n_s64,
+	vshld_n_s64, vshrd_n_s64, vslid_n_s64, vsrad_n_s64, vsrid_n_s64):
+	Fix type signature; remove cast.
+
+2014-06-19  Alan Lawrence  <alan.lawrence@arm.com>
+
+	PR target/60825
 	* config/aarch64/aarch64.c (aarch64_simd_mangle_map): Add entry for
 	V1DFmode.
 	* config/aarch64/aarch64-builtins.c (aarch64_simd_builtin_type_mode):

gcc/config/aarch64/aarch64-builtins.c

@@ -140,9 +140,11 @@ typedef struct
   enum aarch64_type_qualifiers *qualifiers;
 } aarch64_simd_builtin_datum;
 
+/*  The qualifier_internal allows generation of a unary builtin from
+    a pattern with a third pseudo-operand such as a match_scratch.  */
 static enum aarch64_type_qualifiers
 aarch64_types_unop_qualifiers[SIMD_MAX_BUILTIN_ARGS]
-  = { qualifier_none, qualifier_none };
+  = { qualifier_none, qualifier_none, qualifier_internal };
 #define TYPES_UNOP (aarch64_types_unop_qualifiers)
 static enum aarch64_type_qualifiers
 aarch64_types_unopu_qualifiers[SIMD_MAX_BUILTIN_ARGS]

gcc/config/aarch64/aarch64-simd-builtins.def

@@ -365,6 +365,8 @@
   BUILTIN_VDQF (UNOP, frecpe, 0)
   BUILTIN_VDQF (BINOP, frecps, 0)
 
+  /* Implemented by a mixture of abs2 patterns.  Note the DImode builtin is
+     only ever used for the int64x1_t intrinsic, there is no scalar version.  */
   BUILTIN_VALLDI (UNOP, abs, 2)
 
   VAR1 (UNOP, vec_unpacks_hi_, 10, v4sf)

gcc/config/aarch64/aarch64.c

@@ -7358,6 +7358,8 @@ static aarch64_simd_mangle_map_entry aarch64_simd_mangle_map[] = {
   { V2SImode,  "__builtin_aarch64_simd_si",     "11__Int32x2_t" },
   { V2SImode,  "__builtin_aarch64_simd_usi",    "12__Uint32x2_t" },
   { V2SFmode,  "__builtin_aarch64_simd_sf",     "13__Float32x2_t" },
+  { DImode,    "__builtin_aarch64_simd_di",     "11__Int64x1_t" },
+  { DImode,    "__builtin_aarch64_simd_udi",    "12__Uint64x1_t" },
   { V1DFmode,  "__builtin_aarch64_simd_df",	"13__Float64x1_t" },
   { V8QImode,  "__builtin_aarch64_simd_poly8",  "11__Poly8x8_t" },
   { V4HImode,  "__builtin_aarch64_simd_poly16", "12__Poly16x4_t" },

gcc/testsuite/ChangeLog

 2014-06-19  Alan Lawrence  <alan.lawrence@arm.com>
 
+	* g++.dg/abi/mangle-neon-aarch64.C (f22, f23): New tests of 
+	[u]int64x1_t.
+
+	* gcc.target/aarch64/aapcs64/func-ret-64x1_1.c: Add {u,}int64x1 cases.
+	* gcc.target/aarch64/aapcs64/test_64x1_1.c: Likewise.
+
+	* gcc.target/aarch64/scalar_intrinsics.c (test_vaddd_u64,
+	test_vaddd_s64, test_vceqd_s64, test_vceqzd_s64, test_vcged_s64,
+	test_vcled_s64, test_vcgezd_s64, test_vcged_u64, test_vcgtd_s64,
+	test_vcltd_s64, test_vcgtzd_s64, test_vcgtd_u64, test_vclezd_s64,
+	test_vcltzd_s64, test_vqaddd_u64, test_vqaddd_s64, test_vqdmlals_s32,
+	test_vqdmlsls_s32, test_vqdmulls_s32, test_vuqaddd_s64,
+	test_vsqaddd_u64, test_vqmovund_s64, test_vqmovnd_s64,
+	test_vqmovnd_u64, test_vsubd_u64, test_vsubd_s64, test_vqsubd_u64,
+	test_vqsubd_s64, test_vshld_s64, test_vshld_u64, test_vrshld_s64,
+	test_vrshld_u64, test_vshrd_n_s64, test_vshrd_n_u64, test_vsrad_n_s64,
+	test_vsrad_n_u64, test_vrshrd_n_s64, test_vrshrd_n_u64,
+	test_vrsrad_n_s64, test_vrsrad_n_u64, test_vqrshld_s64,
+	test_vqrshld_u64, test_vqshlud_n_s64, test_vqshld_s64, test_vqshld_u64,
+	test_vqshld_n_u64, test_vqshrund_n_s64, test_vqrshrund_n_s64,
+	test_vqshrnd_n_s64, test_vqshrnd_n_u64, test_vqrshrnd_n_s64,
+	test_vqrshrnd_n_u64, test_vshld_n_s64, test_vshdl_n_u64,
+	test_vslid_n_s64, test_vslid_n_u64, test_vsrid_n_s64,
+	test_vsrid_n_u64): Fix signature to match intrinsic.
+	
+	(test_vabs_s64): Remove.
+	(test_vaddd_s64_2, test_vsubd_s64_2): Use force_simd.
+
+	(test_vdupd_lane_s64): Rename to...
+	(test_vdupd_laneq_s64): ...and remove a call to force_simd.
+
+	(test_vdupd_lane_u64): Rename to...
+	(test_vdupd_laneq_u64): ...and remove a call to force_simd.
+
+	(test_vtst_s64): Rename to...
+	(test_vtstd_s64): ...and change int64x1_t to int64_t.
+
+	(test_vtst_u64): Rename to...
+	(test_vtstd_u64): ...and change uint64x1_t to uint64_t.
+
+	* gcc.target/aarch64/singleton_intrinsics_1.c: New file.
+	* gcc.target/aarch64/vdup_lane_1.c, gcc.target/aarch64/vdup_lane_2.c:
+	Remove out-of-bounds tests.
+	* gcc.target/aarch64/vneg_s.c (INDEX*, RUN_TEST): Remove INDEX macro.
+
+2014-06-19  Alan Lawrence  <alan.lawrence@arm.com>
+
 	* g++.dg/abi/mangle-neon-aarch64.C: Also test mangling of float64x1_t.
 	* gcc.target/aarch64/aapcs/test_64x1_1.c: New test.
 	* gcc.target/aarch64/aapcs/func-ret-64x1_1.c: New test.

gcc/testsuite/g++.dg/abi/mangle-neon-aarch64.C

@@ -8,9 +8,11 @@
 void f0 (int8x8_t a) {}
 void f1 (int16x4_t a) {}
 void f2 (int32x2_t a) {}
+void f22 (int64x1_t a) {}
 void f3 (uint8x8_t a) {}
 void f4 (uint16x4_t a) {}
 void f5 (uint32x2_t a) {}
+void f23 (uint64x1_t a) {}
 void f6 (float32x2_t a) {}
 void f7 (poly8x8_t a) {}
 void f8 (poly16x4_t a) {}
@@ -35,9 +37,11 @@ void g1 (int8x16_t, int8x16_t) {}
 // { dg-final { scan-assembler "_Z2f010__Int8x8_t:" } }
 // { dg-final { scan-assembler "_Z2f111__Int16x4_t:" } }
 // { dg-final { scan-assembler "_Z2f211__Int32x2_t:" } }
+// { dg-final { scan-assembler "_Z3f2211__Int64x1_t:" } }
 // { dg-final { scan-assembler "_Z2f311__Uint8x8_t:" } }
 // { dg-final { scan-assembler "_Z2f412__Uint16x4_t:" } }
 // { dg-final { scan-assembler "_Z2f512__Uint32x2_t:" } }
+// { dg-final { scan-assembler "_Z3f2312__Uint64x1_t:" } }
 // { dg-final { scan-assembler "_Z2f613__Float32x2_t:" } }
 // { dg-final { scan-assembler "_Z2f711__Poly8x8_t:" } }
 // { dg-final { scan-assembler "_Z2f812__Poly16x4_t:" } }

gcc/testsuite/gcc.target/aarch64/aapcs64/func-ret-64x1_1.c

@@ -11,5 +11,7 @@
 #include "abitest-2.h"
 #else
 FUNC_VAL_CHECK ( 0, float64x1_t, (float64x1_t) {123456.789}, D0, flat)
+FUNC_VAL_CHECK ( 1, int64x1_t, (int64x1_t) {0xdeadbeefcafebabeLL}, D0, flat)
+FUNC_VAL_CHECK ( 2, uint64x1_t, (uint64x1_t) {0xaaaabbbbccccddddULL}, D0, flat)
 #endif
 

gcc/testsuite/gcc.target/aarch64/aapcs64/test_64x1_1.c

@@ -12,5 +12,9 @@
 #else
 ARG (float64x1_t, (float64x1_t) {123456.789}, D0)
 ARG (float64_t, 987654.321, D1)
-LAST_ARG (float64x1_t, (float64x1_t) {13579.2468}, D2)
+ARG (float64x1_t, (float64x1_t) {13579.2468}, D2)
+ARG (int64x1_t, (int64x1_t) {0xcafebabe0cabfaffLL}, D3)
+ARG (uint64_t, 0xdeadbeefdeafbeeb, X0)
+ARG (int64_t, 0x0123456789abcdef, X1)
+LAST_ARG (uint64x1_t, (uint64x1_t) {0xaaaabbbbccccddddULL}, D4)
 #endif

gcc/testsuite/gcc.target/aarch64/simd/ext_s64.x

@@ -9,7 +9,7 @@ main (int argc, char **argv)
   int64_t arr2[] = {1};
   int64x1_t in2 = vld1_s64 (arr2);
   int64x1_t actual = vext_s64 (in1, in2, 0);
-  if (actual != in1)
+  if (actual[0] != in1[0])
     abort ();
 
   return 0;

gcc/testsuite/gcc.target/aarch64/simd/ext_u64.x

@@ -9,7 +9,7 @@ main (int argc, char **argv)
   uint64_t arr2[] = {1};
   uint64x1_t in2 = vld1_u64 (arr2);
   uint64x1_t actual = vext_u64 (in1, in2, 0);
-  if (actual != in1)
+  if (actual[0] != in1[0])
     abort ();
 
   return 0;

gcc/testsuite/gcc.target/aarch64/singleton_intrinsics_1.c

+/* { dg-do assemble } */
+/* { dg-options "-O2 -dp" } */
+
+/* Test the [u]int64x1_t intrinsics.  */
+
+#include <arm_neon.h>
+
+/* { dg-final { scan-assembler-times "\\tadd\\td\[0-9\]+" 2 } } */
+
+uint64x1_t
+test_vadd_u64 (uint64x1_t a, uint64x1_t b)
+{
+  return vadd_u64 (a, b);
+}
+
+int64x1_t
+test_vadd_s64 (int64x1_t a, int64x1_t b)
+{
+  return vadd_s64 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "\\tabs\\td\[0-9\]+, d\[0-9\]+" 1 } } */
+
+int64x1_t
+test_vabs_s64 (int64x1_t a)
+{
+  return vabs_s64 (a);
+}
+
+/* { dg-final { scan-assembler-times "\\tcmeq\\td\[0-9\]+, d\[0-9\]+, d\[0-9\]+" 1 } } */
+
+uint64x1_t
+test_vceq_s64 (int64x1_t a, int64x1_t b)
+{
+  return vceq_s64 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "\\tcmeq\\td\[0-9\]+, d\[0-9\]+, #?0" 1 } } */
+
+uint64x1_t
+test_vceqz_s64 (int64x1_t a)
+{
+  return vceqz_s64 (a);
+}
+
+/* { dg-final { scan-assembler-times "\\tcmge\\td\[0-9\]+, d\[0-9\]+, d\[0-9\]+" 2 } } */
+
+uint64x1_t
+test_vcge_s64 (int64x1_t a, int64x1_t b)
+{
+  return vcge_s64 (a, b);
+}
+
+uint64x1_t
+test_vcle_s64 (int64x1_t a, int64x1_t b)
+{
+  return vcle_s64 (a, b);
+}
+
+/* Idiom recognition will cause this testcase not to generate
+   the expected cmge instruction, so do not check for it.  */
+
+uint64x1_t
+test_vcgez_s64 (int64x1_t a)
+{
+  return vcgez_s64 (a);
+}
+
+/* { dg-final { scan-assembler-times "\\tcmhs\\td\[0-9\]+, d\[0-9\]+, d\[0-9\]+" 1 } } */
+
+uint64x1_t
+test_vcge_u64 (uint64x1_t a, uint64x1_t b)
+{
+  return vcge_u64 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "\\tcmgt\\td\[0-9\]+, d\[0-9\]+, d\[0-9\]+" 2 } } */
+
+uint64x1_t
+test_vcgt_s64 (int64x1_t a, int64x1_t b)
+{
+  return vcgt_s64 (a, b);
+}
+
+uint64x1_t
+test_vclt_s64 (int64x1_t a, int64x1_t b)
+{
+  return vclt_s64 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "\\tcmgt\\td\[0-9\]+, d\[0-9\]+, #?0" 1 } } */
+
+uint64x1_t
+test_vcgtz_s64 (int64x1_t a)
+{
+  return vcgtz_s64 (a);
+}
+
+/* { dg-final { scan-assembler-times "\\tcmhi\\td\[0-9\]+, d\[0-9\]+, d\[0-9\]+" 1 } } */
+
+uint64x1_t
+test_vcgt_u64 (uint64x1_t a, uint64x1_t b)
+{
+  return vcgt_u64 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "\\tcmle\\td\[0-9\]+, d\[0-9\]+, #?0" 1 } } */
+
+uint64x1_t
+test_vclez_s64 (int64x1_t a)
+{
+  return vclez_s64 (a);
+}
+
+/* Compiling with "-dp" outputs the name of each .md pattern into the assembler.
+   This is what we look for here.  */
+/* { dg-final { scan-assembler-times "aarch64_get_lanev2di" 2 } } */
+
+int64x1_t
+test_vdup_laneq_s64 (int64x2_t a)
+{
+  return vdup_laneq_s64 (a, 1);
+}
+
+uint64x1_t
+test_vdup_laneq_u64 (uint64x2_t a)
+{
+  return vdup_laneq_u64 (a, 1);
+}
+
+/* { dg-final { scan-assembler-times "\\tcmtst\\td\[0-9\]+, d\[0-9\]+, d\[0-9\]+" 2 } } */
+
+uint64x1_t
+test_vtst_s64 (int64x1_t a, int64x1_t b)
+{
+  return vtst_s64 (a, b);
+}
+
+uint64x1_t
+test_vtst_u64 (uint64x1_t a, uint64x1_t b)
+{
+  return vtst_u64 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "\\tuqadd\\td\[0-9\]+" 1 } } */
+
+uint64x1_t
+test_vqadd_u64 (uint64x1_t a, uint64x1_t b)
+{
+  return vqadd_u64 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqadd\\td\[0-9\]+" 1 } } */
+
+int64x1_t
+test_vqadd_s64 (int64x1_t a, int64x1_t b)
+{
+  return vqadd_s64 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "\\tsuqadd\\td\[0-9\]+" 1 } } */
+
+int64x1_t
+test_vuqadd_s64 (int64x1_t a, uint64x1_t b)
+{
+  return vuqadd_s64 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "\\tusqadd\\td\[0-9\]+" 1 } } */
+
+uint64x1_t
+test_vsqadd_u64 (uint64x1_t a, int64x1_t b)
+{
+  return vsqadd_u64 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "\\tsub\\td\[0-9\]+" 2 } } */
+
+uint64x1_t
+test_vsub_u64 (uint64x1_t a, uint64x1_t b)
+{
+  return vsub_u64 (a, b);
+}
+
+int64x1_t
+test_vsub_s64 (int64x1_t a, int64x1_t b)
+{
+  return vsub_s64 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "\\tuqsub\\td\[0-9\]+" 1 } } */
+
+uint64x1_t
+test_vqsub_u64 (uint64x1_t a, uint64x1_t b)
+{
+  return vqsub_u64 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqsub\\td\[0-9\]+" 1 } } */
+
+int64x1_t
+test_vqsub_s64 (int64x1_t a, int64x1_t b)
+{
+  return vqsub_s64 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "\\tsshl\\td\[0-9\]+" 1 } } */
+
+int64x1_t
+test_vshl_s64 (int64x1_t a, int64x1_t b)
+{
+  return vshl_s64 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "\\tushl\\td\[0-9\]+" 1 } } */
+
+uint64x1_t
+test_vshl_u64 (uint64x1_t a, int64x1_t b)
+{
+  return vshl_u64 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "\\tsrshl\\td\[0-9\]+" 1 } } */
+
+int64x1_t
+test_vrshl_s64 (int64x1_t a, int64x1_t b)
+{
+  return vrshl_s64 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "\\turshl\\td\[0-9\]+" 1 } } */
+
+uint64x1_t
+test_vrshl_u64 (uint64x1_t a, int64x1_t b)
+{
+  return vrshl_u64 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "\\tsshr\\td\[0-9\]+" 3 } } */
+/* Idiom recognition compiles vcltz and vcgez to sshr rather than cmlt/cmge.  */
+
+int64x1_t
+test_vshr_n_s64 (int64x1_t a)
+{
+  return vshr_n_s64 (a, 5);
+}
+
+uint64x1_t
+test_vcltz_s64 (int64x1_t a)
+{
+  return vcltz_s64 (a);
+}
+
+/* { dg-final { scan-assembler-times "\\tushr\\td\[0-9\]+" 1 } } */
+
+uint64x1_t
+test_vshr_n_u64 (uint64x1_t a)
+{
+  return vshr_n_u64 (a, 3);
+}
+
+/* { dg-final { scan-assembler-times "\\tssra\\td\[0-9\]+" 1 } } */
+
+int64x1_t
+test_vsra_n_s64 (int64x1_t a, int64x1_t b)
+{
+  return vsra_n_s64 (a, b, 2);
+}
+
+/* { dg-final { scan-assembler-times "\\tusra\\td\[0-9\]+" 1 } } */
+
+uint64x1_t
+test_vsra_n_u64 (uint64x1_t a, uint64x1_t b)
+{
+  return vsra_n_u64 (a, b, 5);
+}
+
+/* { dg-final { scan-assembler-times "\\tsrshr\\td\[0-9\]+" 1 } } */
+
+int64x1_t
+test_vrshr_n_s64 (int64x1_t a)
+{
+  return vrshr_n_s64 (a, 5);
+}
+
+/* { dg-final { scan-assembler-times "\\turshr\\td\[0-9\]+" 1 } } */
+
+uint64x1_t
+test_vrshr_n_u64 (uint64x1_t a)
+{
+  return vrshr_n_u64 (a, 3);
+}
+
+/* { dg-final { scan-assembler-times "\\tsrsra\\td\[0-9\]+" 1 } } */
+
+int64x1_t
+test_vrsra_n_s64 (int64x1_t a, int64x1_t b)
+{
+  return vrsra_n_s64 (a, b, 3);
+}
+
+/* { dg-final { scan-assembler-times "\\tsrsra\\td\[0-9\]+" 1 } } */
+
+uint64x1_t
+test_vrsra_n_u64 (uint64x1_t a, uint64x1_t b)
+{
+  return vrsra_n_u64 (a, b, 4);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqrshl\\td\[0-9\]+" 1 } } */
+
+int64x1_t
+test_vqrshl_s64 (int64x1_t a, int64x1_t b)
+{
+  return vqrshl_s64 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "\\tuqrshl\\td\[0-9\]+" 1 } } */
+
+uint64x1_t
+test_vqrshl_u64 (uint64x1_t a, int64x1_t b)
+{
+  return vqrshl_u64 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqshlu\\td\[0-9\]+" 1 } } */
+
+uint64x1_t
+test_vqshlu_n_s64 (int64x1_t a)
+{
+  return vqshlu_n_s64 (a, 6);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqshl\\td\[0-9\]+" 2 } } */
+
+int64x1_t
+test_vqshl_s64 (int64x1_t a, int64x1_t b)
+{
+  return vqshl_s64 (a, b);
+}
+
+int64x1_t
+test_vqshl_n_s64 (int64x1_t a)
+{
+  return vqshl_n_s64 (a, 5);
+}
+
+/* { dg-final { scan-assembler-times "\\tuqshl\\td\[0-9\]+" 2 } } */
+
+uint64x1_t
+test_vqshl_u64 (uint64x1_t a, int64x1_t b)
+{
+  return vqshl_u64 (a, b);
+}
+
+uint64x1_t
+test_vqshl_n_u64 (uint64x1_t a)
+{
+  return vqshl_n_u64 (a, 5);
+}
+
+/* { dg-final { scan-assembler-times "\\tshl\\td\[0-9\]+" 2 } } */
+
+int64x1_t
+test_vshl_n_s64 (int64x1_t a)
+{
+  return vshl_n_s64 (a, 9);
+}
+
+uint64x1_t
+test_vshl_n_u64 (uint64x1_t a)
+{
+  return vshl_n_u64 (a, 9);
+}
+
+/* { dg-final { scan-assembler-times "\\tsli\\td\[0-9\]+" 2 } } */
+
+int64x1_t
+test_vsli_n_s64 (int64x1_t a, int64x1_t b)
+{
+  return vsli_n_s64 (a, b, 9);
+}
+
+uint64x1_t
+test_vsli_n_u64 (uint64x1_t a, uint64x1_t b)
+{
+  return vsli_n_u64 (a, b, 9);
+}
+
+/* { dg-final { scan-assembler-times "\\tsri\\td\[0-9\]+" 2 } } */
+
+int64x1_t
+test_vsri_n_s64 (int64x1_t a, int64x1_t b)
+{
+  return vsri_n_s64 (a, b, 9);
+}
+
+uint64x1_t
+test_vsri_n_u64 (uint64x1_t a, uint64x1_t b)
+{
+  return vsri_n_u64 (a, b, 9);
+}

gcc/testsuite/gcc.target/aarch64/vdup_lane_1.c

@@ -304,12 +304,6 @@ wrap_vdup_lane_s64_0 (int64x1_t a)
   return vdup_lane_s64 (a, 0);
 }
 
-int64x1_t __attribute__ ((noinline))
-wrap_vdup_lane_s64_1 (int64x1_t a)
-{
-  return vdup_lane_s64 (a, 1);
-}
-
 int __attribute__ ((noinline))
 test_vdup_lane_s64 ()
 {
@@ -325,12 +319,6 @@ test_vdup_lane_s64 ()
   if (c[0] != d[0])
     return 1;
 
-  c[0] = 1;
-  a = vld1_s64 (c);
-  b = wrap_vdup_lane_s64_1 (a);
-  vst1_s64 (d, b);
-  if (c[0] != d[0])
-    return 1;
   return 0;
 }
 
@@ -340,12 +328,6 @@ wrap_vdupq_lane_s64_0 (int64x1_t a)
   return vdupq_lane_s64 (a, 0);
 }
 
-int64x2_t __attribute__ ((noinline))
-wrap_vdupq_lane_s64_1 (int64x1_t a)
-{
-  return vdupq_lane_s64 (a, 1);
-}
-
 int __attribute__ ((noinline))
 test_vdupq_lane_s64 ()
 {
@@ -362,14 +344,6 @@ test_vdupq_lane_s64 ()
   for (i = 0; i < 2; i++)
     if (c[0] != d[i])
       return 1;
-
-  c[0] = 1;
-  a = vld1_s64 (c);
-  b = wrap_vdupq_lane_s64_1 (a);
-  vst1q_s64 (d, b);
-  for (i = 0; i < 2; i++)
-    if (c[0] != d[i])
-      return 1;
   return 0;
 }
 

gcc/testsuite/gcc.target/aarch64/vdup_lane_2.c

@@ -278,9 +278,9 @@ test_vdupd_lane_u64 ()
 }
 
 int64_t __attribute__ ((noinline))
-wrap_vdupd_lane_s64_0 (uint64x1_t dummy, int64x1_t a)
+wrap_vdupd_lane_s64_0 (int64x1_t dummy, int64x1_t a)
 {
-  return vdupd_lane_u64 (a, 0);
+  return vdupd_lane_s64 (a, 0);
 }
 
 int __attribute__ ((noinline))

gcc/testsuite/gcc.target/aarch64/vneg_s.c

@@ -5,7 +5,10 @@
 #include <arm_neon.h>
 #include <limits.h>
 
-/* Used to force a variable to a SIMD register.  */
+/* Used to force a variable to a SIMD register.  Also acts as a stronger
+   inhibitor of optimization than the below - necessary for int64x1_t
+   because more of the implementation is in terms of gcc vector extensions
+   (which support constant propagation) than for other types.  */
 #define force_simd(V1)   asm volatile ("mov %d0, %1.d[0]"	\
 	   : "=w"(V1)						\
 	   : "w"(V1)						\
@@ -38,14 +41,6 @@ extern void abort (void);
 #define DATA_TYPE_32 float
 #define DATA_TYPE_64 double
 #define DATA_TYPE(data_len) DATA_TYPE_##data_len
-#define INDEX64_8 [i]
-#define INDEX64_16 [i]
-#define INDEX64_32 [i]
-#define INDEX64_64
-#define INDEX128_8 [i]
-#define INDEX128_16 [i]
-#define INDEX128_32 [i]
-#define INDEX128_64 [i]
 
 #define FORCE_SIMD_INST64_8(data)
 #define FORCE_SIMD_INST64_16(data)
@@ -56,8 +51,6 @@ extern void abort (void);
 #define FORCE_SIMD_INST128_32(data)
 #define FORCE_SIMD_INST128_64(data)
 
-#define INDEX(reg_len, data_len) \
-  CONCAT1 (INDEX, reg_len##_##data_len)
 #define FORCE_SIMD_INST(reg_len, data_len, data) \
   CONCAT1 (FORCE_SIMD_INST, reg_len##_##data_len) (data)
 #define LOAD_INST(reg_len, data_len) \
@@ -77,8 +70,7 @@ extern void abort (void);
     for (i = 0; i < n; i++)						\
       {									\
         INHIB_OPTIMIZATION;						\
-	if (a INDEX (reg_len, data_len)					\
-	    != b INDEX (reg_len, data_len))				\
+	if (a[i] != b[i])						\
 	  return 1;							\
       }									\
   }