gcc/
	* lra-constraints.c (valid_address_p): Move earlier in file.
	(address_eliminator): New structure.
	(satisfies_memory_constraint_p): New function.
	(satisfies_address_constraint_p): Likewise.
	(process_alt_operands, process_address, curr_insn_transform): Use them.

From-SVN: r211242

gcc/
	* lra-int.h (lra_static_insn_data): Make operand_alternative a
	const pointer.
	(target_lra_int, default_target_lra_int, this_target_lra_int)
	(op_alt_data): Delete.
	* lra.h (lra_init): Delete.
	* lra.c (default_target_lra_int, this_target_lra_int): Delete.
	(init_insn_code_data_once): Remove op_alt_data handling.
	(finish_insn_code_data_once): Likewise.
	(init_op_alt_data): Delete.
	(get_static_insn_data): Initialize operand_alternative to null.
	(free_insn_recog_data): Cast operand_alternative before freeing it.
	(setup_operand_alternative): Take the operand_alternative as
	parameter and assume it isn't already cached in the static
	insn data.
	(lra_set_insn_recog_data): Update accordingly.
	(lra_init): Delete.
	* ira.c (ira_init): Don't call lra_init.
	* target-globals.h (this_target_lra_int): Declare.
	(target_globals): Remove lra_int.
	(restore_target_globals): Update accordingly.
	* target-globals.c: Don't include lra-int.h.
	(default_target_globals, save_target_globals): Remove lra_int.

From-SVN: r211241

gcc/
	* recog.h (operand_alternative): Convert reg_class, reject,
	matched and matches into bitfields.
	(preprocess_constraints): New overload.
	(preprocess_insn_constraints): New function.
	(preprocess_constraints): Take the insn as parameter.
	(recog_op_alt): Change into a pointer.
	(target_recog): Add x_op_alt.
	* recog.c (asm_op_alt): New variable.
	(recog_op_alt): Change into a pointer.
	(preprocess_constraints): New overload, replacing the old function
	definition with one that doesn't use global state.
	(preprocess_insn_constraints): New function.
	(preprocess_constraints): Use them.  Take the insn as parameter.
	Use asm_op_alt for asms.
	(recog_init): Free existing x_op_alt entries.
	* ira-lives.c (check_and_make_def_conflict): Make operand_alternative
	pointer const.
	(make_early_clobber_and_input_conflicts): Likewise.
	(process_bb_node_lives): Pass the insn to process_constraints.
	* reg-stack.c (check_asm_stack_operands): Likewise.
	(subst_asm_stack_regs): Likewise.
	* regcprop.c (copyprop_hardreg_forward_1): Likewise.
	* regrename.c (build_def_use): Likewise.
	* sched-deps.c (sched_analyze_insn): Likewise.
	* sel-sched.c (get_reg_class, implicit_clobber_conflict_p): Likewise.
	* config/arm/arm.c (xscale_sched_adjust_cost): Likewise.
	(note_invalid_constants): Likewise.
	* config/i386/i386.c (ix86_legitimate_combined_insn): Likewise.
	(ix86_legitimate_combined_insn): Make operand_alternative pointer
	const.

From-SVN: r211240

gcc/
	* recog.c (preprocess_constraints): Don't skip disabled alternatives.
	* ira-lives.c (check_and_make_def_conflict): Check for disabled
	alternatives.
	(make_early_clobber_and_input_conflicts): Likewise.
	* config/i386/i386.c (ix86_legitimate_combined_insn): Likewise.

From-SVN: r211239

gcc/
	* recog.h (alternative_class): New function.
	(which_op_alt): Return a const recog_op_alt.
	* reg-stack.c (check_asm_stack_operands): Update type accordingly.
	(subst_asm_stack_regs): Likewise.
	* config/arm/arm.c (note_invalid_constants): Likewise.
	* regcprop.c (copyprop_hardreg_forward_1): Likewise.  Don't modify
	the operand_alternative; use alternative class instead.
	* sel-sched.c (get_reg_class): Likewise.
	* regrename.c (build_def_use): Likewise.
	(hide_operands, restore_operands, record_out_operands): Update type
	accordingly.

From-SVN: r211238

gcc/
	* recog.h (recog_op_alt): Convert to a flat array.
	(which_op_alt): New function.
	* recog.c (recog_op_alt): Convert to a flat array.
	(preprocess_constraints): Update accordingly, grouping all
	operands of the same alternative together, rather than the
	other way around.
	* ira-lives.c (check_and_make_def_conflict): Likewise.
	(make_early_clobber_and_input_conflicts): Likewise.
	* config/i386/i386.c (ix86_legitimate_combined_insn): Likewise.
	* reg-stack.c (check_asm_stack_operands): Use which_op_alt.
	(subst_asm_stack_regs): Likewise.
	* regcprop.c (copyprop_hardreg_forward_1): Likewise.
	* regrename.c (hide_operands, record_out_operands): Likewise.
	(build_def_use): Likewise.
	* sel-sched.c (get_reg_class): Likewise.
	* config/arm/arm.c (note_invalid_constants): Likewise.

From-SVN: r211237

re PR c++/51253 ([C++11][DR 1030] Evaluation order (sequenced-before relation) among initializer-clauses in braced-init-list)

	PR c++/51253
	PR c++/61382
gcc/
	* gimplify.c (gimplify_arg): Non-static.
	* gimplify.h: Declare it.
gcc/cp/
	* cp-gimplify.c (cp_gimplify_expr): Handle CALL_EXPR_LIST_INIT_P here.
	* semantics.c (simplify_aggr_init_expr): Not here, just copy it.

From-SVN: r211235

2014-06-04  Richard Biener  <rguenther@suse.de>

	* tree.h (may_be_aliased): Trust TREE_ADDRESSABLE from
	TREE_PUBLIC and DECL_EXTERNAL decls.

From-SVN: r211233

2014-06-04  Matthew Fortune  <matthew.fortune@imgtec.com>

gcc/
	* regcprop.c (copyprop_hardreg_forward_1): Account for 
	HARD_REGNO_CALL_PART_CLOBBERED.

From-SVN: r211230

2014-06-04  Richard Biener  <rguenther@suse.de>

	* configure.ac: Check whether the underlying type of int64_t
	is long or long long.
	* configure: Regenerate.
	* config.in: Likewise.
	* hwint.h (HOST_WIDE_INT): Match the underlying type of int64_t.
	(HOST_WIDE_INT_PRINT_*): Define in terms of PRI*64.

From-SVN: r211228

2014-06-04  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/60098
	* tree-ssa-dse.c (dse_possible_dead_store_p): Walk until
	we hit a kill.
	(dse_optimize_stmt): Simplify, now that we found a kill
	earlier.

	* gcc.dg/tree-ssa/ssa-dse-15.c: New testcase.

From-SVN: r211224

2014-06-04  Richard Biener  <rguenther@suse.de>

	* tree-ssa-alias.c (stmt_may_clobber_ref_p): Improve handling
	of accesses with non-invariant address.

	* gcc.dg/tree-ssa/ssa-dse-16.c: New testcase.

From-SVN: r211223

	* cgraph.h (cgraph_make_wrapper): New function introduced.
	* cgraphunit.c (cgraph_make_wrapper): The function implementation.
	* ipa-inline.h (inline_analyze_function): The function is global.
	* ipa-inline-analysis.c (inline_analyze_function): Likewise.

From-SVN: r211222

gcc/c/
	PR c/58942
	* c-array-notation.c (fix_builtin_array_notation_fn): Handle the case
	with a pointer.

gcc/cp/
	PR c/58942
	* cp-array-notation.c (expand_sec_reduce_builtin): Handle the case
	with a pointer.

gcc/testsuite/
	PR c/58942
	* c-c++-common/cilk-plus/AN/pr58942.c: Check for correct handling of
	the case with a pointer.

From-SVN: r211220

	* tree.h (private_lookup_attribute_starting): New function.
	(lookup_attribute_starting): Likewise.
	* tree.c (private_lookup_attribute_starting): Likewise.

From-SVN: r211219

	* cgraph.h (expand_thunk): New argument added.
	(address_taken_from_non_vtable_p): New global function.
	* ipa-visibility.c (address_taken_from_non_vtable_p): Likewise.
	* cgraphclones.c (duplicate_thunk_for_node): Argument added to call.
	* cgraphunit.c (analyze_function): Likewise.
	(assemble_thunks_and_aliases): Argument added to call.
	(expand_thunk): New argument forces to produce GIMPLE thunk.

From-SVN: r211218

	* coverage.h (coverage_compute_cfg_checksum): Argument added.
	* coverage.c (coverage_compute_cfg_checksum): Likewise.
	* profile.c (branch_prob): Likewise.

From-SVN: r211217

2014-06-04  Martin Jambor  <mjambor@suse.cz>

	PR ipa/61340
	* ipa-pure-const.c (propagate_pure_const): Add unreachable default
	handler for switch on an ipa_ref_use enum.
	* ipa-reference.c (analyze_function): Likewise.

From-SVN: r211216

2014-06-04  Thomas Preud'homme  <thomas.preudhomme@arm.com>

	* MAINTAINERS (Write After Approval): Add myself.

From-SVN: r211215

	* recog.c (peep2_attempt): Copy SIBLING_CALL_P flag
	from old call-instruction.

From-SVN: r211213

	PR c/30020
	* c-common.c (check_case_bounds): Add location parameter.
	Use it.
	(c_add_case_label): Pass loc to check_case_bounds.

	* c-c++-common/pr30020.c: New test.

From-SVN: r211212

	(aarch64_legitimize_reload_address): Support full addressing modes
	for vector modes.
	* config/aarch64/aarch64.md (mov<mode>, movmisalign<mode>)
	(*aarch64_simd_mov<mode>, *aarch64_simd_mov<mode>): Relax predicates.

From-SVN: r211211

From-SVN: r211210

2014-06-03  Andrew Pinski  <apinski@cavium.com>

	* config/aarch64/aarch64.c (aarch64_if_then_else_costs): Allow non comparisons
	for OP0.

2014-06-03  Andrew Pinski  <apinski@cavium.com>

	* gcc.c-torture/compile/20140528-1.c: New testcase.

From-SVN: r211206

2014-06-03  Andrew Pinski  <apinski@cavium.com>

	* config/aarch64/aarch64.c (aarch64_if_then_else_costs): New function.
	(aarch64_rtx_costs): Use aarch64_if_then_else_costs.

From-SVN: r211205

        * config/i386/i386.c (ix86_function_value_regno_p): Disallow DX_REG
        for 64-bit ms-abi.

From-SVN: r211204

2014-06-03  Dehao Chen  <dehao@google.com>

	* tree-cfg.c (gimple_merge_blocks): Only reset count when BBs are in
	the same loop.
	* gcc.dg/tree-prof/merge_block.c: New test.

From-SVN: r211202

	* g++.dg/ext/mv14.C (dg-options): Add -march=x86-64.
	* g++.dg/ext/mv15.C (dg-options): Ditto.

From-SVN: r211196

gcc/cp
2014-06-03  Paolo Carlini  <paolo.carlini@oracle.com>

	DR 1423
	PR c++/52174
	* call.c (standard_conversion): Convert nullptr to bool only
	in case of direct-initialization.
	(convert_like_real): Provide informative error message.

gcc/testsuite
2014-06-03  Paolo Carlini  <paolo.carlini@oracle.com>

	DR 1423
	PR c++/52174
	* g++.dg/cpp0x/nullptr31.C: New.
	* g++.dg/cpp0x/sfinae-nullptr1.C: Likewise.
	* g++.dg/cpp0x/nullptr17.C: Update.

libstdc++-v3
2014-06-03  Paolo Carlini  <paolo.carlini@oracle.com>

	DR 1423
	PR c++/52174
	* testsuite/20_util/is_assignable/value.cc: Update.

From-SVN: r211195

	PR c/60439
	* doc/invoke.texi: Document -Wswitch-bool.
	* function.c (stack_protect_epilogue): Cast controlling expression of
	the switch to int.
	* gengtype.c (walk_type): Generate switch expression with its
	controlling expression cast to int.
c/
	* c-parser.c (c_parser_switch_statement): Pass explicit_cast_p to
	c_start_case.
	* c-tree.h (c_start_case): Update.
	* c-typeck.c (c_start_case): Add new boolean parameter.  Warn if
	switch condition has boolean value.
cp/
	* semantics.c (finish_switch_cond): Warn if switch condition has
	boolean value.
c-family/
	* c.opt (Wswitch-bool): New option.
testsuite/
	* c-c++-common/pr60439.c: New test.
	* g++.dg/eh/scope1.C (f4): Add dg-warning.

From-SVN: r211194

	* config/avr/avr-mcus.def: Add new avr25 devices attiny441, attiny828
	and attiny841.
	* config/avr/avr-tables.opt: Regenerate.
	* config/avr/t-multilib: Regenerate.
	* doc/avr-mmcu.texi: Regenerate.

	* config/avr/avr-mcus.def (ata6616c): Add new avr25 device.
	(ata6617c, ata664251): Add new avr35 devices.
	(ata6612c): Add new avr4 device.
	(ata6613c, ata6614q): Add new avr5 devices.
	* config/avr/avr-tables.opt: Regenerate.
	* config/avr/t-multilib: Regenerate.
	* doc/avr-mmcu.texi: Regenerate.

From-SVN: r211189

	PR c++/60992
	* pt.c (tsubst_copy) [VAR_DECL]: Try lookup first.  Add a new
	variable to local_specializations.

From-SVN: r211188

	* gcc/config/aarch64/aarch64-builtins.c
	(aarch64_types_binop_ssu_qualifiers): New static data.
	(TYPES_BINOP_SSU): Define.
	* gcc/config/aarch64/aarch64-simd-builtins.def (suqadd, ushl, urshl,
	urshr_n, ushll_n): Use appropriate unsigned qualifiers.
	* gcc/config/aarch64/arm_neon.h (vrshl_u8, vrshl_u16, vrshl_u32,
	vrshl_u64, vrshlq_u8, vrshlq_u16, vrshlq_u32, vrshlq_u64, vrshld_u64,
	vrshr_n_u8, vrshr_n_u16, vrshr_n_u32, vrshr_n_u64, vrshrq_n_u8,
	vrshrq_n_u16, vrshrq_n_u32, vrshrq_n_u64, vrshrd_n_u64, vshll_n_u8,
	vshll_n_u16, vshll_n_u32, vuqadd_s8, vuqadd_s16, vuqadd_s32,
	vuqadd_s64, vuqaddq_s8, vuqaddq_s16, vuqaddq_s32, vuqaddq_s64,
	vuqaddb_s8, vuqaddh_s16, vuqadds_s32, vuqaddd_s64): Add signedness
	suffix to builtin function name, remove cast.
	(vshl_s8, vshl_s16, vshl_s32, vshl_s64, vshl_u8, vshl_u16, vshl_u32,
	vshl_u64, vshlq_s8, vshlq_s16, vshlq_s32, vshlq_s64, vshlq_u8,
	vshlq_u16, vshlq_u32, vshlq_u64, vshld_s64, vshld_u64): Remove cast.

From-SVN: r211186

	* gcc/config/aarch64/aarch64-builtins.c
	(aarch64_types_binop_uus_qualifiers,
	aarch64_types_shift_to_unsigned_qualifiers,
	aarch64_types_unsigned_shiftacc_qualifiers): Define.
	* gcc/config/aarch64/aarch64-simd-builtins.def (uqshl, uqrshl, uqadd,
	uqsub, usqadd, usra_n, ursra_n, uqshrn_n, uqrshrn_n, usri_n, usli_n,
	sqshlu_n, uqshl_n): Update qualifiers.
	* gcc/config/aarch64/arm_neon.h (vqadd_u8, vqadd_u16, vqadd_u32,
	vqadd_u64, vqaddq_u8, vqaddq_u16, vqaddq_u32, vqaddq_u64, vqsub_u8,
	vqsub_u16, vqsub_u32, vqsub_u64, vqsubq_u8, vqsubq_u16, vqsubq_u32,
	vqsubq_u64, vqaddb_u8, vqaddh_u16, vqadds_u32, vqaddd_u64, vqrshl_u8,
	vqrshl_u16, vqrshl_u32, vqrshl_u64, vqrshlq_u8, vqrshlq_u16,
	vqrshlq_u32, vqrshlq_u64, vqrshlb_u8, vqrshlh_u16, vqrshls_u32,
	vqrshld_u64, vqrshrn_n_u16, vqrshrn_n_u32, vqrshrn_n_u64,
	vqrshrnh_n_u16, vqrshrns_n_u32, vqrshrnd_n_u64, vqshl_u8, vqshl_u16,
	vqshl_u32, vqshl_u64, vqshlq_u8, vqshlq_u16, vqshlq_u32, vqshlq_u64,
	vqshlb_u8, vqshlh_u16, vqshls_u32, vqshld_u64, vqshl_n_u8, vqshl_n_u16,
	vqshl_n_u32, vqshl_n_u64, vqshlq_n_u8, vqshlq_n_u16, vqshlq_n_u32,
	vqshlq_n_u64, vqshlb_n_u8, vqshlh_n_u16, vqshls_n_u32, vqshld_n_u64,
	vqshlu_n_s8, vqshlu_n_s16, vqshlu_n_s32, vqshlu_n_s64, vqshluq_n_s8,
	vqshluq_n_s16, vqshluq_n_s32, vqshluq_n_s64, vqshlub_n_s8,
	vqshluh_n_s16, vqshlus_n_s32, vqshlud_n_s64, vqshrn_n_u16,
	vqshrn_n_u32, vqshrn_n_u64, vqshrnh_n_u16, vqshrns_n_u32,
	vqshrnd_n_u64, vqsubb_u8, vqsubh_u16, vqsubs_u32, vqsubd_u64,
	vrsra_n_u8, vrsra_n_u16, vrsra_n_u32, vrsra_n_u64, vrsraq_n_u8,
	vrsraq_n_u16, vrsraq_n_u32, vrsraq_n_u64, vrsrad_n_u64, vsli_n_u8,
	vsli_n_u16, vsli_n_u32,vsli_n_u64, vsliq_n_u8, vsliq_n_u16,
	vsliq_n_u32, vsliq_n_u64, vslid_n_u64, vsqadd_u8, vsqadd_u16,
	vsqadd_u32, vsqadd_u64, vsqaddq_u8, vsqaddq_u16, vsqaddq_u32,
	vsqaddq_u64, vsqaddb_u8, vsqaddh_u16, vsqadds_u32, vsqaddd_u64,
	vsra_n_u8, vsra_n_u16, vsra_n_u32, vsra_n_u64, vsraq_n_u8,
	vsraq_n_u16, vsraq_n_u32, vsraq_n_u64, vsrad_n_u64, vsri_n_u8,
	vsri_n_u16, vsri_n_u32, vsri_n_u64, vsriq_n_u8, vsriq_n_u16,
	vsriq_n_u32, vsriq_n_u64, vsrid_n_u64): Remove casts.

From-SVN: r211185

2014-06-03  Teresa Johnson  <tejohnson@google.com>

	* tree-sra.c (modify_function): Record caller nodes after rebuild.

From-SVN: r211180

	PR c++/60848
	* call.c (is_std_init_list): Check CLASSTYPE_TEMPLATE_INFO.

From-SVN: r211179

	PR c++/61020
	* varpool.c (ctor_for_folding): Handle uninitialized vtables.

From-SVN: r211178

(part 2, fix ICE at -O0)

	* config/aarch64/aarch64.c (aarch64_evpc_ext): allow and handle
	location == 0.

From-SVN: r211177

        * config/aarch64/aarch64-simd.md (aarch64_rev<REVERSE:rev-op><mode>):
        New pattern.
        * config/aarch64/aarch64.c (aarch64_evpc_rev): New function.
        (aarch64_expand_vec_perm_const_1): Add call to aarch64_evpc_rev.
        * config/aarch64/iterators.md (REVERSE): New iterator.
        (UNSPEC_REV64, UNSPEC_REV32, UNSPEC_REV16): New enum elements.
        (rev_op): New int_attribute.
        * config/aarch64/arm_neon.h (vrev16_p8, vrev16_s8, vrev16_u8,
        vrev16q_p8, vrev16q_s8, vrev16q_u8, vrev32_p8, vrev32_p16, vrev32_s8,
        vrev32_s16, vrev32_u8, vrev32_u16, vrev32q_p8, vrev32q_p16, vrev32q_s8,
        vrev32q_s16, vrev32q_u8, vrev32q_u16, vrev64_f32, vrev64_p8,
        vrev64_p16, vrev64_s8, vrev64_s16, vrev64_s32, vrev64_u8, vrev64_u16,
        vrev64_u32, vrev64q_f32, vrev64q_p8, vrev64q_p16, vrev64q_s8,
        vrev64q_s16, vrev64q_s32, vrev64q_u8, vrev64q_u16, vrev64q_u32):
        Replace temporary __asm__ with __builtin_shuffle.

From-SVN: r211174

2014-06-03  Andrew Bennett  <andrew.bennett@imgtec.com> 

	* config/mips/mips-cpus.def: Add mips32r3, mips32r5, mips64r3 and
	mips64r5.
	* config/mips/mips-tables.opt: Regenerate.
	* config/mips/mips.c (mips_compute_frame_info): Changed if statement
	to use mips_isa_rev rather than ISA_MIPS32R2.
	* config/mips/mips.h (ISA_MIPS32R3): New define.
	(ISA_MIPS32R5): New define.
	(ISA_MIPS64R3): New define.
	(ISA_MIPS64R5): New define.
	(TARGET_CPU_CPP_BUILTINS): Added support for ISA_MIPS32R3, ISA_MIPS32R5,
	ISA_MIPS64R3 and ISA_MIPS64R5.
	(MIPS_ISA_LEVEL_SPEC): Added support for mips32r3, mips32r5, mips64r3
	and mips64r5.
	(MIPS_ISA_SYNCI_SPEC): Likewise.
	(ISA_HAS_64BIT_REGS): Added ISA_MIPS64R3 and ISA_MIPS64R5.
	(LINK_SPEC): Added mips32r3 and mips32r5.
	* config/mips/t-isa3264 (MULTILIB_MATCHES): Map mips32r3 and mips32r5
	to mips32r2; and mips64r3 and mips64r5 to mips64r2.
	* config/mips/t-mti-elf (MULTILIB_MATCHES): Likewise.
	* config/mips/t-mti-linux (MULTILIB_MATCHES): Likewise.
	* config/mips/t-sde (MULTILIB_MATCHES): Likewise.
	* config/mips/t-sdemtk (MULTILIB_MATCHES): New define.
	* doc/invoke.texi: Document mips32r3, mips32r5, mips64r3 and mips64r5.

From-SVN: r211173