The problem here was g:23b88fda was not a complete fix
for supporting tranditional TLS on ILP32.

So the problem here is a couple of things, first __tls_get_addr
call will return a C pointer value so we need to use ptr_mode
when we are creating the call.  Then we need to convert
back that register to the correct mode, either zero extending
it or just creating a move instruction.
Also symbol_ref can either be in SImode or DImode.  So we need to
allow both modes.

Built and tested on aarch64-linux-gnu with no regressions.
Also built a full toolchain (including glibc) defaulting to traditional
TLS that targets ilp32 and lp64.

ChangeLog:
PR target/93119
* config/aarch64/aarch64.md (tlsgd_small_<mode>): Have operand 0
as PTR mode. Have operand 1 as being modeless, it can be P mode.
(*tlsgd_small_<mode>): Likewise.
* config/aarch64/aarch64.c (aarch64_load_symref_appropriately)
<case SYMBOL_SMALL_TLSGD>: Call gen_tlsgd_small_* with a ptr_mode
register.  Convert that register back to dest using convert_mode.

Bug 93348 reports an ICE on certain cases of casts of expressions that
may appear only in unevaluated parts of integer constant expressions,
arising from the generation of nested C_MAYBE_CONST_EXPRs.  This patch
fixes it by adding a call to remove_c_maybe_const_expr in the
integer-operands case, as is done in other similar cases.

Bootstrapped with no regressions for x86_64-pc-linux-gnu.

	PR c/93348
gcc/c:
	* c-typeck.c (build_c_cast): Call remove_c_maybe_const_expr on
	argument with integer operands.

gcc/testsuite:
	* gcc.c-torture/compile/pr93348-1.c: New test.

PR analyzer/93352 reports a qsort failure
  "comparator not anti-symmetric: -2147483648, -2147483648)"
within the analyzer on code involving an array access of [0x7fffffff + 1].

The issue is that array_region (which uses int for keys into known
values in the array) uses subtraction to implement int_cmp for sorting
the keys, which isn't going to work for boundary values.

Potentially a wider type should be used, but for now this patch fixes
the ICE by using explicit comparisons rather than subtraction to
implement the qsort callback.

gcc/analyzer/ChangeLog:
	PR analyzer/93352
	* region-model.cc (int_cmp): Rename to...
	(array_region::key_cmp): ...this, using key_t rather than int.
	Rewrite in terms of comparisons rather than subtraction to
	ensure qsort is anti-symmetric when handling extreme values.
	(array_region::walk_for_canonicalization): Update for above
	renaming.
	* region-model.h (array_region::key_cmp): New decl.

gcc/testsuite/ChangeLog:
	PR analyzer/93352
	* gcc.dg/analyzer/pr93352.c: New test.

This is a longstanding issue with lots of duplicates; people are not
interested in a -Wconversion warning about mychar += 1.  So now that warning
depends on -Warith-conversion; otherwise we only warn if operands of the
arithmetic have conversion issues.

	* c.opt (-Warith-conversion): New.
	* c-warn.c (conversion_warning): Recurse for operands of
	operators.  Only warn about the whole expression with
	-Warith-conversion.

It seemed strange to me to warn about sign conversion in
unsafe_conversion_p, when other warnings are in conversion_warning, and the
latter function is the only place that asks the former function to warn.
This change is also necessary for my -Warith-conversion patch.

	* c-common.c (unsafe_conversion_p): Don't warn, return UNSAFE_SIGN.
	* c-warn.c (conversion_warning): Warn about UNSAFE_SIGN.

Found with an rtl checking enabled build and check.  This triggered failures
in the gcc.target/riscv/save-restore* tests.  We are using XINT to access an
XWINT value; INTVAL is the preferred solution.

	gcc/
	* config/riscv/riscv-sr.c (riscv_sr_match_prologue): Use INTVAL
	instead of XINT.

	* gcc.target/cris/asm-v8.S, gcc.target/cris/inasm-v8.c,
	gcc.target/cris/sync-1.c: Apply effective_target_march_option.

Oops.  A few stragglers, same as recent update: differing
-march=... options is an error, noticed with e.g.
"make check RUNTESTFLAGS=--target_board=cris-sim/arch=v10"

Since GNU2 TLS address from glibc run-time is in ptr_mode, we should do
GNU2 TLS address computation in ptr_mode and zero-extend result to Pmode.

gcc/

	PR target/93319
	* config/i386/i386.c (ix86_tls_module_base): Replace Pmode
	with ptr_mode.
	(legitimize_tls_address): Do GNU2 TLS address computation in
	ptr_mode and zero-extend result to Pmode.
	*  config/i386/i386.md (@tls_dynamic_gnu2_64_<mode>): Replace
	:P with :PTR and Pmode with ptr_mode.
	(*tls_dynamic_gnu2_lea_64_<mode>): Likewise.
	(*tls_dynamic_gnu2_call_64_<mode>): Likewise.
	(*tls_dynamic_gnu2_combine_64_<mode>): Likewise.

gcc/testsuite/

	PR target/93319
	* gcc.target/i386/pr93319-1a.c: Don't include <stdio.h>.
	(test1): Replace printf with __builtin_printf.

For normal captures we usually look through them within unevaluated context,
but that doesn't work here; trying to take the sizeof of the array in the
enclosing scope tries and fails to evaluate a SAVE_EXPR from the enclosing
scope.

	* lambda.c (is_lambda_ignored_entity): Don't look past VLA capture.

We were failing to handle VLA capture in tsubst_lambda_expr; initially
building a DECLTYPE_TYPE for the capture and then tsubsting it doesn't give
the special VLA handling.  So with this patch we call add_capture again for
VLAs.

	* pt.c (tsubst_lambda_expr): Repeat add_capture for VLAs.

gcc/cp
2020-01-21  Iain Sandoe  <iain@sandoe.co.uk>
    Bin Cheng  <bin.cheng@linux.alibaba.com>

* coroutines.cc (coro_promise_type_found_p): Check for NULL return
from complete_type_or_else.
(register_param_uses): Likewise.
(build_co_await): Do not try to use complete_type_or_else for void
types, otherwise for incomplete types, check for NULL return from
complete_type_or_else.

gcc/testsuite
2020-01-21  Bin Cheng  <bin.linux@linux.alibaba.com>

* g++.dg/coroutines/co-await-void_type.C: New test.

As mentioned in the PR, during combine rtx_costs can be called sometimes
even on RTL that has not been validated yet and so can contain even operands
that aren't valid in any instruction.

2020-01-21  Jakub Jelinek  <jakub@redhat.com>

	PR target/93333
	* config/riscv/riscv.c (riscv_rtx_costs) <case ZERO_EXTRACT>: Verify
	the last two operands are CONST_INT_P before using them as such.

	* gcc.c-torture/compile/pr93333.c: New test.

I observed this testcase was failing on nios2-elf.  The more general
regexp was copied from other tests using dg-output.

2020-01-21  Sandra Loosemore  <sandra@codesourcery.com>

	gcc/testsuite/
	* g++.dg/coroutines/torture/mid-suspend-destruction-0.C: Generalize
	line terminators in patterns.

I'd used mode-based element types in the SVE ACLE implementation, but
it turns out that they don't correspond to the <stdint.h> types used by
ILP32 newlib.  GCC already knows what the correct <stdint.h> types are,
I just wasn't using the right interface to find them.

A consequence of this is that ILP32 newlib code needs to cast "int *"
pointers to "int32_t *" before passing them to s32 loads and stores,
since int32_t is defined as "long int" rather than "int".  That matches
the normal C++ overloading behaviour for this target, where passing
"int *" to:

    void f(int32_t *);
    void f(int64_t *);

would be ambiguous.  It also matches the corresponding <arm_neon.h>
behaviour.

2020-01-21  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
	* config/aarch64/aarch64-sve-builtins.def: Use get_typenode_from_name
	to get the integer element types.

gcc/testsuite/
	* gcc.target/aarch64/sve/acle/general-c/load_1.c (f1): Cast to
	int32_t * rather than int *.
	* gcc.target/aarch64/sve/acle/general-c/load_2.c (f1): Likewise.
	* gcc.target/aarch64/sve/acle/general-c/load_gather_sv_1.c
	(f1): Likewise.
	* gcc.target/aarch64/sve/acle/general-c/load_gather_sv_2.c
	(f1): Likewise.
	* gcc.target/aarch64/sve/acle/general-c/load_gather_sv_restricted_1.c
	(f1): Likewise.
	* gcc.target/aarch64/sve/acle/general-c/load_replicate_1.c
	(f1): Likewise.
	* gcc.target/aarch64/sve/acle/general-c/store_1.c (f1): Likewise.
	* gcc.target/aarch64/sve/acle/general-c/store_2.c (f1): Likewise.
	* gcc.target/aarch64/sve/acle/general-c/store_scatter_index_1.c
	(f1): Likewise.
	* gcc.target/aarch64/sve/acle/general-c/store_scatter_offset_2.c
	(f1): Likewise.
	* gcc.target/aarch64/sve/acle/general-c/store_scatter_offset_restricted_1.c
	(f1): Likewise.

This long-overdue patch promotes SImode pointers to DImode addresses,
avoiding various ICEs in the existing tests.

2020-01-21  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
	* config/aarch64/aarch64-sve-builtins.h
	(function_expander::convert_to_pmode): Declare.
	* config/aarch64/aarch64-sve-builtins.cc
	(function_expander::convert_to_pmode): New function.
	(function_expander::get_contiguous_base): Use it.
	(function_expander::prepare_gather_address_operands): Likewise.
	* config/aarch64/aarch64-sve-builtins-sve2.cc
	(svwhilerw_svwhilewr_impl::expand): Likewise.

This is a workaround that emits a BTI after the function label if that
is followed by a patch area. We try to remove the BTI that follows the
patch area (this may fail e.g. if the first instruction is a PACIASP).

So before this commit -fpatchable-function-entry=3,1 with bti generates

    .section __patchable_function_entries
    .8byte .LPFE
    .text
  .LPFE:
    nop
  foo:
    nop
    nop
    bti c // or paciasp
    ...

and after this commit

    .section __patchable_function_entries
    .8byte .LPFE
    .text
  .LPFE:
    nop
  foo:
    bti c
    nop
    nop
    // may be paciasp
    ...

and with -fpatchable-function-entry=1 (M=0) the code now is

  foo:
    bti c
    .section __patchable_function_entries
    .8byte .LPFE
    .text
  .LPFE:
    nop
    // may be paciasp
    ...

There is a new bti insn in the middle of the patchable area users need
to be aware of unless M=0 (patch area is after the new bti) or M=N
(patch area is before the label, no new bti). Note: bti is not added to
all functions consistently (it can be turned off per function using a
target attribute or the compiler may detect that the function is never
called indirectly), so if bti is inserted in the middle of a patch area
then user code needs to deal with detecting it.

Tested on aarch64-none-linux-gnu.

gcc/ChangeLog:

	PR target/92424
	* config/aarch64/aarch64.c (aarch64_declare_function_name): Set
	cfun->machine->label_is_assembled.
	(aarch64_print_patchable_function_entry): New.
	(TARGET_ASM_PRINT_PATCHABLE_FUNCTION_ENTRY): Define.
	* config/aarch64/aarch64.h (struct machine_function): New field,
	label_is_assembled.

gcc/testsuite/ChangeLog:

	PR target/92424
	* gcc.target/aarch64/pr92424-1.c: New test.
	* gcc.target/aarch64/pr92424-2.c: New test.
	* gcc.target/aarch64/pr92424-3.c: New test.

gcc/ChangeLog:
	PR ipa/93315
	* ipa-profile.c (ipa_profile): Delete call_sums and set it to
	NULL on exit.

Commit 9ceec73f introduced intrinsics for the AArch64 FP64 matrix
multiply instructions.  These require binutils support for the same
instructions.

This patch adds a DejaGNU test to ensure this binutils support is there
and uses it in the files that need this test.

Testing Done:
Checked on a cross-compiler that:
Tests running for binutils commit e264b5b7a are listed as UNSUPPORTED.
Tests running for binutils commit 26916852e all pass.

gcc/testsuite/ChangeLog:

2020-01-21  Matthew Malcomson  <matthew.malcomson@arm.com>

	* gcc.target/aarch64/sve/acle/asm/ld1ro_f16.c: Use require
	directive.
	* gcc.target/aarch64/sve/acle/asm/ld1ro_f32.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/ld1ro_f64.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/ld1ro_s16.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/ld1ro_s32.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/ld1ro_s64.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/ld1ro_s8.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/ld1ro_u16.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/ld1ro_u32.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/ld1ro_u64.c: Likewise.
	* gcc.target/aarch64/sve/acle/asm/ld1ro_u8.c: Likewise.
	* lib/target-supports.exp: Add assembly requirement directive.

This patch fixes ICE causes by call stmt site hash going out of sync.  For
speculative edges it is assumed to contain a direct call so if we are
removing it hashtable needs to be updated.  I realize that the code is ugly
but I will leave cleanup for next stage1.

Bootstrapped/regtested x86_64-linux. This patch makes it possible to build
Firefox again.

	PR lto/93318
	* cgraph.c (cgraph_edge::resolve_speculation,
	cgraph_edge::redirect_call_stmt_to_callee): Fix update of
	call_stmt_site_hash.

The problem in the PR was that make_temporary_var_for_ref_to_temp ran before
determine_visibility, so when we copied the linkage of the reference
variable it had not yet been restricted by its anonymous namespace context,
so the temporary wrongly ended up with TREE_PUBLIC set.  The natural
solution is to run determine_visibility earlier.  But that needs to happen
after maybe_commonize_var increases the linkage of some local variables, and
on targets without weak symbol support, that function does different things
based on the results of check_initializer, which is what calls
make_temporary_var_for_ref_to_temp.  To break this circular dependency I'm
calling maybe_commonize_var early, and then again later if the target
doesn't support weak symbols.

It also occurred to me that make_temporary_var_for_ref_to_temp wasn't
handling DECL_VISIBILITY at all, and verified that we were doing the wrong
thing.  So I've combined the linkage-copying code from there and two other
places.

	* decl2.c (copy_linkage): Factor out of get_guard.
	* call.c (make_temporary_var_for_ref_to_temp): Use it.
	* decl.c (cp_finish_decomp): Use it.
	(cp_finish_decl): determine_visibility sooner.

	* config/rs6000/rs6000.c (common_mode_defined): Remove
	unused variable.

        PR fortran/93309
        * interface.c (gfc_procedure_use): Also check parent namespace for
        'implict none (external)'.
        * symbol.c (gfc_get_namespace): Don't set has_implicit_none_export
        to parent namespace's setting.

        PR fortran/93309
        * gfortran.dg/external_implicit_none_2.f90: New.

We were actually value-numbering two entities with different type
the same rather than just having the same representation in the
hashtable.  The following fixes that by wrapping the value in a
to be inserted VIEW_CONVERT_EXPR.

2020-01-21  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/92328
	* tree-ssa-sccvn.c (vn_reference_lookup_3): Preserve
	type when value-numbering same-sized store by inserting a
	VIEW_CONVERT_EXPR.
	(eliminate_dom_walker::eliminate_stmt): When eliminating
	a redundant store handle bit-reinterpretation of the same value.

	* gcc.dg/torture/pr92328.c: New testcase.

Reported as PR 93321, prepare_block_for_update with some huge
recusive inlining can go past the stack limit. Transforming this
recursive into worklist improves the stack usage here and we no
longer seg fault for the testcase.  Note the order we walk the siblings
change.

ChangeLog:
	PR tree-opt/93321
	* tree-into-ssa.c (prepare_block_for_update_1): Split out from ...
	(prepare_block_for_update): This.  Use a worklist instead of recursing.

2020-01-21  Mihail-Calin Ionescu  <mihail.ionescu@arm.com>

	* gcc/config/arm/arm.c (clear_operation_p):
	Initialise last_regno, skip first iteration
	based on the first_set value and use ints instead
	of the unnecessary HOST_WIDE_INTs.

The following testcase ICEs, because for TFmode the particular subtraction
pattern (*subtf3) is not enabled with the given options.  Using
expand_simple_binop instead of emitting the subtraction by hand just moves
the ICE one insn later, NEG of ABS is not then recognized, etc., but
ultimately the problem is that when rs6000_emit_cmove is called for floating
point operand mode (and earlier condition ensures that in that case
compare_mode is also floating point), the expander makes sure the
operand mode is SFDF, but for the comparison mode nothing checks it, yet
there is just one *fsel* pattern with 2 separate SFDF iterators.

The following patch fixes it by giving up if compare_mode is not SFmode or
DFmode.

2020-01-21  Jakub Jelinek  <jakub@redhat.com>

	PR target/93073
	* config/rs6000/rs6000.c (rs6000_emit_cmove): If using fsel, punt for
	compare_mode other than SFmode or DFmode.

	* gcc.target/powerpc/pr93073.c: New test.

The HSA/ROCm runtime rejects binaries not built for the exact GPU device
present. So far, the libgomp amdgcn plugin does not verify that the GPU ISA
and the ISA specified at compile time match before handing over the binary to
the runtime.  In case of a mismatch, the user is confronted with an unhelpful
runtime error.

This commit implements a runtime ISA check. In case of an ISA mismatch, the
execution is aborted with a clear error message and a hint at the correct
compilation parameters for the GPU on which the execution has been attempted.

libgomp/
	* plugin/plugin-gcn.c (EF_AMDGPU_MACH): New enum.
	* (EF_AMDGPU_MACH_MASK): New constant.
	* (gcn_isa): New typedef.
	* (gcn_gfx801_s): New constant.
	* (gcn_gfx803_s): New constant.
	* (gcn_gfx900_s): New constant.
	* (gcn_gfx906_s): New constant.
	* (gcn_isa_name_len): New constant.
	* (elf_gcn_isa_field): New function.
	* (isa_hsa_name): New function.
	* (isa_gcc_name): New function.
	* (isa_code): New function.
	* (struct agent_info): Add field "device_isa" and remove field
	"gfx900_p".
	* (GOMP_OFFLOAD_init_device): Adapt agent init to "agent_info"
	field changes, fail if device has unknown ISA.
	* (parse_target_attributes): Replace "gfx900_p" by "device_isa".
	* (isa_matches_agent): New function ...
	* (create_and_finalize_hsa_program): ... used from here to check
	that the GPU ISA and the code-object ISA match.

The patch sets current_function_returns_value flag in templates for
all co_return/co_yield/co_await cases, as well as for ramp function.

gcc/cp/ChangeLog
    * coroutines.cc (finish_co_await_expr): Set return value flag.
    (finish_co_yield_expr, morph_fn_to_coro): Ditto.

gcc/testsuite/ChangeLog
    * g++.dg/coroutines/co-return-warning-1.C: New test.

gcc/ChangeLog

	PR target/93304
	* config/riscv/riscv-protos.h (riscv_hard_regno_rename_ok): New.
	* config/riscv/riscv.c (riscv_hard_regno_rename_ok): New.
	* config/riscv/riscv.h (HARD_REGNO_RENAME_OK): Defined.

gcc/testsuite/ChangeLog

	PR target/93304
	* gcc.target/riscv/pr93304.c: New test.

	* doc/xml/faq.xml: Fix grammar.
	* doc/xml/manual/appendix_contributing.xml: Improve instructions.
	* doc/xml/manual/spine.xml: Update copyright years.
	* doc/html/*: Regenerate.

	* zh_TW.po: Update.

2020-01-20  Andrew Stubbs  <ams@codesourcery.com>

	libgomp/
	* testsuite/libgomp.oacc-c-c++-common/loop-auto-1.c: Skip test on gcn.
	* testsuite/libgomp.oacc-c-c++-common/loop-dim-default.c (main):
	Adjust test dimensions for amdgcn.
	* testsuite/libgomp.oacc-c-c++-common/loop-gwv-1.c (main): Adjust
	gang/worker/vector expectations dynamically.
	* testsuite/libgomp.oacc-c-c++-common/loop-red-gwv-1.c
	(main): Likewise.
	* testsuite/libgomp.oacc-c-c++-common/loop-red-v-1.c (main): Likewise.
	* testsuite/libgomp.oacc-c-c++-common/loop-red-v-2.c (main): Likewise.
	* testsuite/libgomp.oacc-c-c++-common/loop-red-w-1.c (main): Likewise.
	* testsuite/libgomp.oacc-c-c++-common/loop-red-w-2.c (main): Likewise.
	* testsuite/libgomp.oacc-c-c++-common/loop-red-wv-1.c (main): Likewise.
	* testsuite/libgomp.oacc-c-c++-common/loop-v-1.c (main): Likewise.
	* testsuite/libgomp.oacc-c-c++-common/loop-w-1.c (main): Likewise.
	* testsuite/libgomp.oacc-c-c++-common/loop-wv-1.c (main): Likewise.
	* testsuite/libgomp.oacc-c-c++-common/parallel-dims.c
	(acc_gang): Recognise acc_device_radeon.
	(acc_worker): Likewise.
	(acc_vector): Likewise.
	(main): Set expectations for amdgcn.
	* testsuite/libgomp.oacc-c-c++-common/routine-gwv-1.c
	(main): Adjust gang/worker/vector expectations dynamically.
	* testsuite/libgomp.oacc-c-c++-common/routine-v-1.c (main): Likewise.
	* testsuite/libgomp.oacc-c-c++-common/routine-w-1.c (main): Likewise.
	* testsuite/libgomp.oacc-c-c++-common/routine-wv-1.c (main): Likewise.
	* testsuite/libgomp.oacc-c-c++-common/routine-wv-2.c: Set expectations
	for amdgcn.

Testing shows the setting of 32:16 for jump alignment has a significant
codesize cost, however it doesn't make a difference in performance.
So set jump-align to 4 to get 1.6% codesize improvement.

gcc/
	* config/aarch64/aarch64.c (neoversen1_tunings): Set jump_align to 4.

On MIPS, .set noreorder/reorder needs to emitted around
the nop.  The template for the nop instruction uses %(/%) to
do that.  But default_print_patchable_function_entry uses
fprintf rather than output_asm_insn to output the instruction.

This fixes the problem by using output_asm_insn to emit the nop
instruction.

ChangeLog:

PR middle-end/93242
* targhooks.c (default_print_patchable_function_entry): Use
output_asm_insn to emit the nop instruction.

	* g++.dg/warn/Wstringop-overflow-4.C: Adjust test to avoid failures
	due to an aparrent VRP limtation.
	* gcc.dg/Wstringop-overflow-25.c: Same.

2020-01-20  Fangrui Song  <maskray@google.com>

gcc/
	PR middle-end/93194
	* targhooks.c (default_print_patchable_function_entry): Align to
	POINTER_SIZE.

__has_include is funky in that it is macro-like from the POV of #ifdef and
friends, but lexes its parenthesize argument #include-like.  We were
failing the second part of that, because we used a forwarding macro to an
internal name, and hence always lexed the argument in macro-parameter
context.  We componded that by not setting the right flag when lexing, so
it didn't even know.  Mostly users got lucky.

This reimplements the handline.
1) Remove the forwarding, but declare object-like macros that
expand to themselves.  This satisfies the #ifdef requirement

2) Correctly set angled_brackets when lexing the parameter.  This tells
the lexer (a) <...> is a header name and (b) "..." is too (not a string).

3) Remove the in__has_include lexer state, just tell find_file that that's
what's happenning, so it doesn't emit an error.

We lose the (undocumented) ability to #undef __has_include.  That may well
have been an accident of implementation.  There are no tests for it.

We gain __has_include behaviour for all users of the preprocessors -- not
just the C-family ones that defined a forwarding macro.

	libcpp/
	PR preprocessor/80005
	* include/cpplib.h (BT_HAS_ATTRIBUTE): Fix comment.
	* internal.h (struct lexer_state): Delete in__has_include field.
	(struct spec_nodes): Rename n__has_include{,_next}__ fields.
	(_cpp_defined_macro_p): New.
	(_cpp_find_file): Add has_include parm.
	* directives.c (lex_macro_node): Combine defined,
	__has_inline{,_next} checking.
	(do_ifdef, do_ifndef): Use _cpp_defined_macro_p.
	(_cpp_init_directives): Refactor.
	* expr.c (parse_defined): Use _cpp_defined_macro_p.
	(eval_token): Adjust parse_has_include calls.
	(parse_has_include): Add OP parameter.  Reimplement.
	* files.c (_cpp_find_file): Add HAS_INCLUDE parm.  Use it to
	inhibit error message.
	(_cpp_stack_include): Adjust _cpp_find_file call.
	(_cpp_fake_include, _cpp_compare_file_date): Likewise.
	(open_file_failed): Remove in__has_include check.
	(_cpp_has_header): Adjust _cpp_find_file call.
	* identifiers.c (_cpp_init_hashtable): Don't init
	__has_include{,_next} here ...
	* init.c (cpp_init_builtins): ... init them here.  Define as
	macros.
	(cpp_read_main_file): Adjust _cpp_find_file call.
	* pch.c (cpp_read_state): Adjust __has_include{,_next} access.
	* traditional.c (_cpp_scan_out_locgical_line): Likewise.

	gcc/c-family/
	PR preprocessor/80005
	* c-cppbuiltins.c (c_cpp_builtins): Don't define __has_include{,_next}.

	gcc/testsuite/
	PR preprocessor/80005
	* g++.dg/cpp1y/feat-cxx14.C: Adjust.
	* g++.dg/cpp1z/feat-cxx17.C: Adjust.
	* g++.dg/cpp2a/feat-cxx2a.C: Adjust.
	* g++.dg/cpp/pr80005.C: New.

Should've have checked for the existance of a non static integer
using scan-tree-dump instead of scan-tree-dump-not. A cut and paste
error.