Commit e0a5b313 by Kito Cheng

RISC-V: Disallow regrenme if the TO register never used before for interrupt functions

gcc/ChangeLog

	PR target/93304
	* config/riscv/riscv-protos.h (riscv_hard_regno_rename_ok): New.
	* config/riscv/riscv.c (riscv_hard_regno_rename_ok): New.
	* config/riscv/riscv.h (HARD_REGNO_RENAME_OK): Defined.

gcc/testsuite/ChangeLog

	PR target/93304
	* gcc.target/riscv/pr93304.c: New test.
parent 2df76cd6
2020-01-21 Kito Cheng <kito.cheng@sifive.com>
PR target/93304
* config/riscv/riscv-protos.h (riscv_hard_regno_rename_ok): New.
* config/riscv/riscv.c (riscv_hard_regno_rename_ok): New.
* config/riscv/riscv.h (HARD_REGNO_RENAME_OK): Defined.
2020-01-20 Wilco Dijkstra <wdijkstr@arm.com> 2020-01-20 Wilco Dijkstra <wdijkstr@arm.com>
* config/aarch64/aarch64.c (neoversen1_tunings): Set jump_align to 4. * config/aarch64/aarch64.c (neoversen1_tunings): Set jump_align to 4.
......
...@@ -89,4 +89,6 @@ extern void riscv_init_builtins (void); ...@@ -89,4 +89,6 @@ extern void riscv_init_builtins (void);
/* Routines implemented in riscv-common.c. */ /* Routines implemented in riscv-common.c. */
extern std::string riscv_arch_str (); extern std::string riscv_arch_str ();
extern bool riscv_hard_regno_rename_ok (unsigned, unsigned);
#endif /* ! GCC_RISCV_PROTOS_H */ #endif /* ! GCC_RISCV_PROTOS_H */
...@@ -5021,6 +5021,19 @@ riscv_reorg (void) ...@@ -5021,6 +5021,19 @@ riscv_reorg (void)
riscv_remove_unneeded_save_restore_calls (); riscv_remove_unneeded_save_restore_calls ();
} }
/* Return nonzero if register FROM_REGNO can be renamed to register
TO_REGNO. */
bool
riscv_hard_regno_rename_ok (unsigned from_regno ATTRIBUTE_UNUSED,
unsigned to_regno)
{
/* Interrupt functions can only use registers that have already been
saved by the prologue, even if they would normally be
call-clobbered. */
return !cfun->machine->interrupt_handler_p || df_regs_ever_live_p (to_regno);
}
/* Initialize the GCC target structure. */ /* Initialize the GCC target structure. */
#undef TARGET_ASM_ALIGNED_HI_OP #undef TARGET_ASM_ALIGNED_HI_OP
#define TARGET_ASM_ALIGNED_HI_OP "\t.half\t" #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
......
...@@ -926,4 +926,6 @@ extern unsigned riscv_stack_boundary; ...@@ -926,4 +926,6 @@ extern unsigned riscv_stack_boundary;
extern void riscv_remove_unneeded_save_restore_calls (void); extern void riscv_remove_unneeded_save_restore_calls (void);
#define HARD_REGNO_RENAME_OK(FROM, TO) riscv_hard_regno_rename_ok (FROM, TO)
#endif /* ! GCC_RISCV_H */ #endif /* ! GCC_RISCV_H */
2020-01-21 Kito Cheng <kito.cheng@sifive.com>
PR target/93304
* gcc.target/riscv/pr93304.c: New test.
2020-01-20 Martin Sebor <msebor@redhat.com> 2020-01-20 Martin Sebor <msebor@redhat.com>
PR testsuite/92829 PR testsuite/92829
......
/* Verify the regrename won't rename registers to register which never used
before. */
/* { dg-do compile } */
/* { dg-options "-O -frename-registers" } */
static unsigned _t = 0;
void __attribute__ ((interrupt))
foo (void)
{
_t++;
}
/* Register rename will try to use registers from the lower register
regradless of the REG_ALLOC_ORDER.
In theory, t0-t6 should not used in such small program if regrename
not executed incorrectly, because a5-a0 has higher priority in
REG_ALLOC_ORDER. */
/* { dg-final { scan-assembler-not "t\[0-6\]" } } */
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