This rejects lattice changes from one constant to another.

2020-05-11  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/95049
	* tree-ssa-sccvn.c (set_ssa_val_to): Reject lattice transition
	between different constants.

	* gcc.dg/torture/pr95049.c: New testcase.

Loop optimizers expect to be able to insert on the preheader
edge w/o splitting it thus avoid ending up with a preheader
that enters the loop via an EH edge (or an abnormal edge).

2020-05-06  Richard Biener  <rguenther@suse.de>

	PR middle-end/94964
	* cfgloopmanip.c (create_preheader): Require non-complex
	preheader edge for CP_SIMPLE_PREHEADERS.

Now issues an error "Intrinsic procedure 'num_images' not
allowed in PROCEDURE" instead of an ICE.

2020-06-22  Steven G. Kargl  <kargl@gcc.gnu.org>

gcc/fortran/

	PR fortran/95708
	* intrinsic.c (add_functions): Replace CLASS_INQUIRY with
	CLASS_TRANSFORMATIONAL for intrinsic num_images.
	(make_generic): Replace ACTUAL_NO with ACTUAL_YES for
	intrinsic team_number.
	* resolve.c (resolve_fl_procedure): Check pointer ts.u.derived
	exists before using it.

2020-06-22  Mark Eggleston  <markeggleston@gcc.gnu.org>

gcc/testsuite/

	PR fortran/95708
	* gfortran.dg/pr95708.f90: New test.

(cherry picked from commit 647340c92a042e8e6f7d004637f07060dbde49c0)

	* sv.po: Update.

P2113 from the last C++ meeting clarified that we only compare constraints
on functions or function templates that have equivalent template parameters
and function parameters.

I'm not currently implementing the complicated handling of reversed
comparison operators here; thinking about it now, it seems like a lot of
complexity to support a very weird usage.  If I write two similar comparison
operators to be distinguished by their constraints, why would I write one
reversed?  If they're two unrelated operators, they're very unlikely to be
similar enough for the complexity to help.  I've started a discussion on the
committee reflector about changing these rules.

This change breaks some greedy_ops tests in libstdc++ that were relying on
comparing constraints on unrelated templates, which seems pretty clearly
wrong, so I'm removing those tests for now.

gcc/cp/ChangeLog:

	* call.c (joust): Only compare constraints for non-template
	candidates with matching parameters.
	* pt.c (tsubst_pack_expansion): Fix getting a type parameter
	pack.
	(more_specialized_fn): Only compare constraints for candidates with
	matching parameters.

gcc/testsuite/ChangeLog:

	* g++.dg/cpp2a/concepts-return-req1.C: Expect error.
	* g++.dg/cpp2a/concepts-p2113a.C: New test.
	* g++.dg/cpp2a/concepts-p2113b.C: New test.

libstdc++-v3/ChangeLog:

	* testsuite/24_iterators/move_iterator/rel_ops_c++20.cc:
	Remove greedy_ops tests.
	* testsuite/24_iterators/reverse_iterator/rel_ops_c++20.cc:
	Remove greedy_ops tests.

P2002R1, adopted at the February C++ meeting, made several refinements to
the wording for operator<=>.  This implements clarifications in how the
implicit operator== is declared: as a duplicate of the operator<=>, with
only the return type and name changed.  To that end I factored out the
declaration copying from build_clone.  For GCC 10 I'm leaving build_clone
alone, to reduce the chance of non-C++20-mode regressions.

The decl.c changes are a hack to avoid complaining about constraints on a
non-template friend that isn't defined in the class.  In this case the
defaulted comparison operator should be considered defined, but we weren't
setting funcdef_flag properly.  For GCC 11 I fixed it properly.

gcc/cp/ChangeLog:

	* cp-tree.h (copy_fndecl_with_name): Declare.
	* class.c (copy_fndecl_with_name): Copy from build_clone.
	(add_implicitly_declared_members): Add op== to TYPE_FIELDS.
	* method.c (implicitly_declare_fn): Use copy_fndecl_with_name.
	* decl.c (grokfndecl): Add initialized parm.
	(grokdeclarator): Pass it down.

gcc/testsuite/ChangeLog:

	* g++.dg/cpp2a/spaceship-synth9.C: New test.

With submodules and equivalence declarations, name mangling may result in
long internal symbols overflowing internal buffers.  We now check that
we do not exceed the enlarged buffer sizes.

gcc/fortran/
	PR fortran/95707
	* gfortran.h (gfc_common_head): Enlarge buffer.
	* trans-common.c (gfc_sym_mangled_common_id): Enlarge temporary
	buffers, and add check on length on mangled name to prevent
	overflow.

(cherry picked from commit 3345e74299687de6144b87c0632018cafd4ccf3b)

With submodules, name mangling of character pointer declarations produces long
internal symbols that overflowed a static internal buffer.  Adjust the buffer
size.

gcc/fortran/
	PR fortran/95688
	* iresolve.c (gfc_get_string): Enlarge static buffer size.

(cherry picked from commit cd6546ac0e8fb2f4ff2a4bb2db2363ca02bdb7ba)

With submodules and PDTs, name mangling of interfaces may result in long
internal symbols overflowing a previously static internal buffer.  We now
set the buffer size dynamically.

gcc/fortran/
	PR fortran/95687
	* class.c (get_unique_type_string): Return a string with dynamic
	length.
	(get_unique_hashed_string, gfc_hash_value): Use dynamic result
	from get_unique_type_string instead of static buffer.

(cherry picked from commit ac932bfcd21e9523fa2b880ae8138aef79da7f54)

With submodules, name mangling of interfaces may result in long internal
symbols overflowing an internal buffer.  We now check that we do not
exceed the enlarged buffer size.

gcc/fortran/
	PR fortran/95689
	* interface.c (check_sym_interfaces): Enlarge temporary buffer,
	and add check on length on mangled name to prevent overflow.

(cherry picked from commit 62c0c0ea7bfb6f8f6b8d767b05120cafb6823da6)

EQUIVALENCE objects are subject to constraints listed in the Fortran 2018
standard, section 8.10.1.1.  These constraints are to be checked
also for CLASS variables.

gcc/fortran/
	PR fortran/95587
	* match.c (gfc_match_equivalence): Check constraints on
	EQUIVALENCE objects also for CLASS variables.

(cherry picked from commit 5eb947601bdce59f2ff26694327ad173c51c2724)

Don't perform CET run-time check for host when cross compiling.  Instead,
enable CET in cross compiler if possible so that it will run on both CET
and non-CET hosts.

config/

	PR bootstrap/94998
	* cet.m4 (GCC_CET_HOST_FLAGS): Enable CET in cross compiler if
	possible.

libiberty/

	PR bootstrap/94998
	* configure: Regenerated.

lto-plugin/

	PR bootstrap/94998
	* configure: Regenerated.

(cherry picked from commit d17cdc17c90ce77cb90c569322c1f241d3530cec)

The actual issue is that (in the testcase) std::nothrow is not
available.  So update the handling of the get-return-on-alloc-fail
to include the possibility that std::nothrow might not be
available.

gcc/cp/ChangeLog:

	PR c++/95505
	* coroutines.cc (morph_fn_to_coro): Update handling of
	get-return-object-on-allocation-fail and diagnose missing
	std::nothrow.

gcc/testsuite/ChangeLog:

	PR c++/95505
	* g++.dg/coroutines/pr95505.C: New test.

(cherry picked from commit 445d8da5fbd10e32f8ea470bd9ac02faba8fd718)

Current data dependence analysis misses unit distant vector if DRs in
DDR have the same invariant access functions.  This adds the vector as
the constant access function case.

Also fix typo in testcase.

Backport from master.

2020-06-20  Bin Cheng  <bin.cheng@linux.alibaba.com>

gcc/
	PR tree-optimization/94969
	* tree-data-ref.c (constant_access_functions): Rename to...
	(invariant_access_functions): ...this.  Add parameter.  Check for
	invariant access function, rather than constant.
	(build_classic_dist_vector): Call above function.
	* tree-loop-distribution.c (pg_add_dependence_edges): Add comment.

gcc/testsuite/
	PR tree-optimization/94969
	* gcc.dg/tree-ssa/pr94969.c: New test.

2020-06-20  Jakub Jelinek  <jakub@redhat.com>

gcc/testsuite/
	PR tree-optimization/95110
	* gcc.dg/tree-ssa/pr94969.c: Swap scan-tree-dump-not arguments.

Implementing P2085, another refinement to the operator<=> specification from
the Prague meeting.  It was deemed desirable to be able to have a non-inline
defaulted definition of a comparison operator just like you can with other
defaulted functions.

gcc/cp/ChangeLog:

	* method.c (early_check_defaulted_comparison): Allow defaulting
	comparison outside class.  Complain if non-member operator isn't a
	friend.

gcc/testsuite/ChangeLog:

	* g++.dg/cpp2a/spaceship-friend1.C: New test.
	* g++.dg/cpp2a/spaceship-err4.C: Adjust diagnostic.

* Disallow && references.
* Allow empty unions.
* Improve diagnostics for a subobject comparison with
  non-comparison-category type.

gcc/cp/ChangeLog:

	* method.c (early_check_defaulted_comparison): Check for &&.
	(build_comparison_op): Allow empty union.  Diagnose non-category
	type.
	(common_comparison_type): Remove handling for non-category type.

gcc/testsuite/ChangeLog:

	* g++.dg/cpp2a/spaceship-ref1.C: New test.
	* g++.dg/cpp2a/spaceship-synth-neg4.C: New test.
	* g++.dg/cpp2a/spaceship-union1.C: New test.

We were crashing trying to find the CALL_EXPR in the result of a call to a
consteval operator.

gcc/cp/ChangeLog:

	* call.c (build_new_op_1): Don't look for a CALL_EXPR when
	calling a consteval function.

gcc/testsuite/ChangeLog:

	* g++.dg/cpp2a/consteval17.C: New test.

Currently GIMPLE complete unroller(cunroll) is checking
flag_unroll_loops and flag_peel_loops to see if allow size growth.
Beside affects curnoll, flag_unroll_loops also controls RTL unroler.
To have more freedom to control cunroll and RTL unroller, this patch
introduces flag_cunroll_grow_size.  With this patch, we can control
cunroll and RTL unroller indepently. And enable flag_cunroll_grow_size
only if -funroll-loops or -fpeel-loops or -O3 is specified explicitly.

gcc/ChangeLog
2020-06-19  Jiufu Guo  <guojiufu@linux.ibm.com>

	PR target/95018
	* common.opt (flag_cunroll_grow_size): New flag.
	* toplev.c (process_options): Set flag_cunroll_grow_size.
	* tree-ssa-loop-ivcanon.c (pass_complete_unroll::execute):
	Use flag_cunroll_grow_size.
	* config/rs6000/rs6000.c (rs6000_option_override_internal):
	Override flag_cunroll_grow_size.

The same problem also arises for plfs where prefixed_load_p()
doesn't recognize it so we get just lfs in the asm output
with an @pcrel address.

	Backport from master
	2020-06-03  Aaron Sawdey  <acsawdey@linux.ibm.com>

	PR target/95347
	* config/rs6000/rs6000.c (is_stfs_insn): Rename to
	is_lfs_stfs_insn and make it recognize lfs as well.
	(prefixed_store_p): Use is_lfs_stfs_insn().
	(prefixed_load_p): Use is_lfs_stfs_insn() to recognize lfs.

Because reg_to_non_prefixed() only looks at the register being used, it
doesn't get the right answer for stfs, which leads to us not seeing
that it has a PCREL symbol ref.  This patch works around this by
introducing a helper function that inspects the insn to see if it is in
fact a stfs. Then if we use NON_PREFIXED_DEFAULT, address_to_insn_form()
can see that it has the PCREL symbol ref.

	Backport from master
	2020-06-02  Aaron Sawdey  <acsawdey@linux.ibm.com>

	PR target/95347
	* config/rs6000/rs6000.c (prefixed_store_p): Add special case
	for stfs.
	(is_stfs_insn): New helper function.

As the following testcase shows, the exception for the aarch64
vec_pack_trunc_di is not sufficient on x86, the halfvectype
"vectors" have SImode but the x86 vec_pack_trunc_si meant for
the bool bitmasks combines 2x SImode into DImode, while in the
testcase the halfvectype is 1x SImode "vector" with SImode and
result is 2x HImode "vector" with SImode.

Richard Sandiford's reply:
FWIW, since the aarch64 case was only found by inspection and might
not be useful, personally I'd prefer to drop that case after all.

2020-06-18  Jakub Jelinek  <jakub@redhat.com>

	PR target/95713
	* tree-ssa-forwprop.c (simplify_vector_constructor): Don't allow
	scalar mode halfvectype other than vector boolean for
	VEC_PACK_TRUNC_EXPR.

	* gcc.dg/pr95713.c: New test.

(cherry picked from commit 9a875db43cd4210843c480c8df26a1d6624d057d)

Hello,

This patch fixes the MVE ACLE vaddq_m polymorphic variants by modifying the corresponding
intrinsic parameters and vaddq_m polymorphic variant's _Generic case entries in "arm_mve.h"
header file.

2020-06-04  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>

gcc/
	* config/arm/arm_mve.h (__arm_vaddq_m_n_s8): Correct the intrinsic
	arguments.
	(__arm_vaddq_m_n_s32): Likewise.
	(__arm_vaddq_m_n_s16): Likewise.
	(__arm_vaddq_m_n_u8): Likewise.
	(__arm_vaddq_m_n_u32): Likewise.
	(__arm_vaddq_m_n_u16): Likewise.
	(__arm_vaddq_m): Modify polymorphic variant.

gcc/testsuite/
	* gcc.target/arm/mve/intrinsics/mve_vaddq_m.c: New test.

(cherry picked from commit dc39db873670bea8d8e655444387ceaa53a01a79)

This patch modifies the MVE scalar shift RTL patterns. The current patterns
have wrong constraints and predicates due to which the values returned from
MVE scalar shift instructions are overwritten in the code-gen.

example:
$ cat x.c
int32_t  foo(int64_t acc, int shift)
{
  return sqrshrl_sat48 (acc, shift);
}

Code-gen before applying this patch:
$ arm-none-eabi-gcc -march=armv8.1-m.main+mve -mfloat-abi=hard -O2 -S
$  cat x.s
foo:
   push    {r4, r5}
   sqrshrl r0, r1, #48, r2   ----> (a)
   mov     r0, r4  ----> (b)
   pop     {r4, r5}
   bx      lr

Code-gen after applying this patch:
foo:
   sqrshrl r0, r1, #48, r2
   bx      lr

In the current compiler the return value (r0) from sqrshrl (a) is getting
overwritten by the mov statement (b).
This patch fixes above issue.

2020-06-12  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>

gcc/
	* config/arm/mve.md (mve_uqrshll_sat<supf>_di): Correct the predicate
	and constraint of all the operands.
	(mve_sqrshrl_sat<supf>_di): Likewise.
	(mve_uqrshl_si): Likewise.
	(mve_sqrshr_si): Likewise.
	(mve_uqshll_di): Likewise.
	(mve_urshrl_di): Likewise.
	(mve_uqshl_si): Likewise.
	(mve_urshr_si): Likewise.
	(mve_sqshl_si): Likewise.
	(mve_srshr_si): Likewise.
	(mve_srshrl_di): Likewise.
	(mve_sqshll_di): Likewise.
	* config/arm/predicates.md (arm_low_register_operand): Define.

gcc/testsuite/
	* gcc.target/arm/mve/intrinsics/mve_scalar_shifts1.c: New test.
	* gcc.target/arm/mve/intrinsics/mve_scalar_shifts2.c: Likewise.
	* gcc.target/arm/mve/intrinsics/mve_scalar_shifts3.c: Likewise.
	* gcc.target/arm/mve/intrinsics/mve_scalar_shifts4.c: Likewise.

(cherry picked from commit 6af598703f919b56f628c496843cdfe6f0cb8276)

Fix-up for r279858/commit f760c0c7 "Fortran]
OpenMP/OpenACC – fix more issues with OPTIONAL".

With offloading enabled, we then saw:

    PASS: libgomp.fortran/use_device_ptr-optional-3.f90   -O0  (test for excess errors)
    PASS: libgomp.fortran/use_device_ptr-optional-3.f90   -O0  execution test
    PASS: libgomp.fortran/use_device_ptr-optional-3.f90   -O1  (test for excess errors)
    PASS: libgomp.fortran/use_device_ptr-optional-3.f90   -O1  execution test
    FAIL: libgomp.fortran/use_device_ptr-optional-3.f90   -O2  (test for excess errors)
    UNRESOLVED: libgomp.fortran/use_device_ptr-optional-3.f90   -O2  compilation failed to produce executable
    FAIL: libgomp.fortran/use_device_ptr-optional-3.f90   -O3 -fomit-frame-pointer -funroll-loops -fpeel-loops -ftracer -finline-functions  (test for excess errors)
    UNRESOLVED: libgomp.fortran/use_device_ptr-optional-3.f90   -O3 -fomit-frame-pointer -funroll-loops -fpeel-loops -ftracer -finline-functions  compilation failed to produce executable
    FAIL: libgomp.fortran/use_device_ptr-optional-3.f90   -O3 -g  (test for excess errors)
    UNRESOLVED: libgomp.fortran/use_device_ptr-optional-3.f90   -O3 -g  compilation failed to produce executable
    FAIL: libgomp.fortran/use_device_ptr-optional-3.f90   -Os  (test for excess errors)
    UNRESOLVED: libgomp.fortran/use_device_ptr-optional-3.f90   -Os  compilation failed to produce executable

 ... due to:

    /tmp/cciVc43I.o:(.gnu.offload_vars+0x10): undefined reference to `A.12.4064'
    [...]

..., but after the recent PR94848, PR95551 changes, that problem is now gone.

	libgomp/
	PR lto/94848
	* testsuite/libgomp.fortran/use_device_ptr-optional-3.f90: Add
	'dg-do run'.

(cherry picked from commit 5864930754f63e2dcef9606f2514ae20e80f436e)

	libgcc/
	* config.host (md_unwind_header) <i[34567]86-*-gnu*>: Set to
	'i386/gnu-unwind.h'
	* config/i386/gnu-unwind.h: New file.

Signed-off-by: Thomas Schwinge <thomas@codesourcery.com>
(cherry picked from commit 5e2eebc80d6eeca24745c27a925afdb64292ed22)

Made apparent by recent commit dc703151d4f4560e647649506d5b4ceb0ee11e90
"openmp: Implement discovery of implicit declare target to clauses":

    +FAIL: libgomp.c/target-39.c (internal compiler error)
    +FAIL: libgomp.c/target-39.c (test for excess errors)
    +UNRESOLVED: libgomp.c/target-39.c compilation failed to produce executable

This is in a '--enable-offload-targets=[...],hsa' build, with '-foffload=hsa'
enabled (by default).

    during GIMPLE pass: hsagen
    source-gcc/libgomp/testsuite/libgomp.c/target-39.c: In function ‘main._omp_fn.0.hsa.0’:
    source-gcc/libgomp/testsuite/libgomp.c/target-39.c:23:11: internal compiler error: Segmentation fault
       23 |   #pragma omp target map(from:err)
          |           ^~~
    [...]

GDB:

    Program received signal SIGSEGV, Segmentation fault.
    fndecl_built_in_p (node=0x0, name=BUILT_IN_PREFETCH) at [...]/source-gcc/gcc/tree.h:6267
    6267      return (fndecl_built_in_p (node, BUILT_IN_NORMAL)
    (gdb) bt
    #0  fndecl_built_in_p (node=0x0, name=BUILT_IN_PREFETCH) at [...]/source-gcc/gcc/tree.h:6267
    #1  0x0000000000b19739 in gen_hsa_insns_for_call (stmt=stmt@entry=0x7ffff693b200, hbb=hbb@entry=0x2b152c0) at [...]/source-gcc/gcc/hsa-gen.c:5304
    #2  0x0000000000b1aca7 in gen_hsa_insns_for_gimple_stmt (stmt=0x7ffff693b200, hbb=hbb@entry=0x2b152c0) at [...]/source-gcc/gcc/hsa-gen.c:5770
    #3  0x0000000000b1bd21 in gen_body_from_gimple () at [...]/source-gcc/gcc/hsa-gen.c:5999
    #4  0x0000000000b1dbd2 in generate_hsa (kernel=<optimized out>) at [...]/source-gcc/gcc/hsa-gen.c:6596
    #5  0x0000000000b1de66 in (anonymous namespace)::pass_gen_hsail::execute (this=0x2a2aac0) at [...]/source-gcc/gcc/hsa-gen.c:6680
    #6  0x0000000000d06f90 in execute_one_pass (pass=pass@entry=0x2a2aac0) at [...]/source-gcc/gcc/passes.c:2502
    [...]
    (gdb) up
    #1  0x0000000000b19739 in gen_hsa_insns_for_call (stmt=stmt@entry=0x7ffff693b200, hbb=hbb@entry=0x2b152c0) at /home/thomas/tmp/source/gcc/build/track-slim-omp/source-gcc/gcc/hsa-gen.c:5304
    5304          if (fndecl_built_in_p (function_decl, BUILT_IN_PREFETCH))
    (gdb) print function_decl
    $1 = (tree) 0x0
    (gdb) list
    5299      if (!gimple_call_builtin_p (stmt, BUILT_IN_NORMAL))
    5300        {
    5301          tree function_decl = gimple_call_fndecl (stmt);
    5302          /* Prefetch pass can create type-mismatching prefetch builtin calls which
    5303             fail the gimple_call_builtin_p test above.  Handle them here.  */
    5304          if (fndecl_built_in_p (function_decl, BUILT_IN_PREFETCH))
    5305            return;
    5306
    5307          if (function_decl == NULL_TREE)
    5308            {

The problem is present already since 2016-11-23 commit
56b1c60e (r242761) "Merge from HSA branch to
trunk", and the fix obvious enough.

	gcc/
	* hsa-gen.c (gen_hsa_insns_for_call): Move 'function_decl ==
	NULL_TREE' check earlier.
	gcc/testsuite/
	* c-c++-common/gomp/hsa-indirect-call-1.c: New file.

(cherry picked from commit 973bce0fb50bbfd91f47238b82b99935525716ad)

With PDTs (parameterized derived types) and submodules, name mangling
results in variably long internal symbols.  Instead of using a fixed-size
intermediate buffer, which is actually not really needed, just use a
pointer to strings.

2020-06-14  Harald Anlauf  <anlauf@gmx.de>

gcc/fortran/
	PR fortran/95088
	* class.c (get_unique_type_string): Replace use of fixed size
	buffer by internally passing a pointer to strings.

(cherry picked from commit 3ee9d82484bdc0ae5b1b21f4a3d8ff46d40e36fd)

Since r10-7096 convert_like, when called in a template, creates an
IMPLICIT_CONV_EXPR when we're converting to/from array type.

In this test, we have e[f], and we're converting f (of type class A) to
int, so convert_like in build_new_op_1 created the IMPLICIT_CONV_EXPR
that got into cp_build_array_ref which calls maybe_constant_value.  My
patch above failed to adjust this spot to call fold_non_dependent_expr
instead, which can handle codes like I_C_E in a template.  Fixed by
using a new function maybe_fold_non_dependent_expr, which, if the expr
can't be evaluated to a constant, returns the original expression.

gcc/cp/ChangeLog:

	PR c++/95508
	* constexpr.c (maybe_fold_non_dependent_expr): New.
	* cp-tree.h (maybe_fold_non_dependent_expr): Declare.
	* typeck.c (cp_build_array_ref): Call maybe_fold_non_dependent_expr
	instead of maybe_constant_value.

gcc/testsuite/ChangeLog:

	PR c++/95508
	* g++.dg/template/conv16.C: New test.

Following MVE intrinsic testcases are failing in GCC testsuite.

Directory: gcc.target/arm/mve/intrinsics/
Testcases: vbicq_f16.c, vbicq_f32.c, vbicq_s16.c, vbicq_s32.c, vbicq_s8.c
,vbicq_u16.c, vbicq_u32.c and vbicq_u8.c.

This patch fixes the vbicq intrinsics by modifying the intrinsic parameters
and polymorphic variants in "arm_mve.h" header file.

	Backported from mainline
	2020-06-04  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>

gcc/
	* config/arm/arm_mve.h (__arm_vbicq_n_u16): Correct the intrinsic
	arguments.
	(__arm_vbicq_n_s16): Likewise.
	(__arm_vbicq_n_u32): Likewise.
	(__arm_vbicq_n_s32): Likewise.
	(__arm_vbicq): Modify polymorphic variant.

gcc/testsuite/
	* gcc.target/arm/mve/intrinsics/vbicq_f16.c: Modify.
	* gcc.target/arm/mve/intrinsics/vbicq_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vbicq_n_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vbicq_n_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vbicq_n_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vbicq_n_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vbicq_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vbicq_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vbicq_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vbicq_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vbicq_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vbicq_u8.c: Likewise.

The operands in RTL patterns of MVE vector scatter store intrinsics are
wrongly grouped, because of which few vector loads and stores instructions
are wrongly getting optimized out with -O2.

A new predicate "mve_scatter_memory" is defined in this patch, this predicate
returns TRUE on matching: (mem(reg)) for MVE scatter store intrinsics.
This patch fixes the issue by adding define_expand pattern with
"mve_scatter_memory" predicate and calls the corresponding define_insn by
passing register_operand as first argument. This register_operand is extracted
from the operand with "mve_scatter_memory" predicate in define_expand pattern.

	Backported from mainline
	2020-06-04  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>

gcc/
	PR target/94735
	* config/arm/predicates.md (mve_scatter_memory): Define to
	match (mem (reg)) for scatter store memory.
	* config/arm/mve.md (mve_vstrbq_scatter_offset_<supf><mode>): Modify
	define_insn to define_expand.
	(mve_vstrbq_scatter_offset_p_<supf><mode>): Likewise.
	(mve_vstrhq_scatter_offset_<supf><mode>): Likewise.
	(mve_vstrhq_scatter_shifted_offset_p_<supf><mode>): Likewise.
	(mve_vstrhq_scatter_shifted_offset_<supf><mode>): Likewise.
	(mve_vstrdq_scatter_offset_p_<supf>v2di): Likewise.
	(mve_vstrdq_scatter_offset_<supf>v2di): Likewise.
	(mve_vstrdq_scatter_shifted_offset_p_<supf>v2di): Likewise.
	(mve_vstrdq_scatter_shifted_offset_<supf>v2di): Likewise.
	(mve_vstrhq_scatter_offset_fv8hf): Likewise.
	(mve_vstrhq_scatter_offset_p_fv8hf): Likewise.
	(mve_vstrhq_scatter_shifted_offset_fv8hf): Likewise.
	(mve_vstrhq_scatter_shifted_offset_p_fv8hf): Likewise.
	(mve_vstrwq_scatter_offset_fv4sf): Likewise.
	(mve_vstrwq_scatter_offset_p_fv4sf): Likewise.
	(mve_vstrwq_scatter_offset_p_<supf>v4si): Likewise.
	(mve_vstrwq_scatter_offset_<supf>v4si): Likewise.
	(mve_vstrwq_scatter_shifted_offset_fv4sf): Likewise.
	(mve_vstrwq_scatter_shifted_offset_p_fv4sf): Likewise.
	(mve_vstrwq_scatter_shifted_offset_p_<supf>v4si): Likewise.
	(mve_vstrwq_scatter_shifted_offset_<supf>v4si): Likewise.
	(mve_vstrbq_scatter_offset_<supf><mode>_insn): Define insn for scatter
	stores.
	(mve_vstrbq_scatter_offset_p_<supf><mode>_insn): Likewise.
	(mve_vstrhq_scatter_offset_<supf><mode>_insn): Likewise.
	(mve_vstrhq_scatter_shifted_offset_p_<supf><mode>_insn): Likewise.
	(mve_vstrhq_scatter_shifted_offset_<supf><mode>_insn): Likewise.
	(mve_vstrdq_scatter_offset_p_<supf>v2di_insn): Likewise.
	(mve_vstrdq_scatter_offset_<supf>v2di_insn): Likewise.
	(mve_vstrdq_scatter_shifted_offset_p_<supf>v2di_insn): Likewise.
	(mve_vstrdq_scatter_shifted_offset_<supf>v2di_insn): Likewise.
	(mve_vstrhq_scatter_offset_fv8hf_insn): Likewise.
	(mve_vstrhq_scatter_offset_p_fv8hf_insn): Likewise.
	(mve_vstrhq_scatter_shifted_offset_fv8hf_insn): Likewise.
	(mve_vstrhq_scatter_shifted_offset_p_fv8hf_insn): Likewise.
	(mve_vstrwq_scatter_offset_fv4sf_insn): Likewise.
	(mve_vstrwq_scatter_offset_p_fv4sf_insn): Likewise.
	(mve_vstrwq_scatter_offset_p_<supf>v4si_insn): Likewise.
	(mve_vstrwq_scatter_offset_<supf>v4si_insn): Likewise.
	(mve_vstrwq_scatter_shifted_offset_fv4sf_insn): Likewise.
	(mve_vstrwq_scatter_shifted_offset_p_fv4sf_insn): Likewise.
	(mve_vstrwq_scatter_shifted_offset_p_<supf>v4si_insn): Likewise.
	(mve_vstrwq_scatter_shifted_offset_<supf>v4si_insn): Likewise.

gcc/testsuite/
	PR target/94735
	* gcc.target/arm/mve/intrinsics/mve_vstore_scatter_base.c: New test.
	* gcc.target/arm/mve/intrinsics/mve_vstore_scatter_base_p.c: Likewise.
	* gcc.target/arm/mve/intrinsics/mve_vstore_scatter_offset.c: Likewise.
	* gcc.target/arm/mve/intrinsics/mve_vstore_scatter_offset_p.c: Likewise.
	* gcc.target/arm/mve/intrinsics/mve_vstore_scatter_shifted_offset.c:
	Likewise.
	* gcc.target/arm/mve/intrinsics/mve_vstore_scatter_shifted_offset_p.c:
	Likewise.

This small patch fix some unintentional fall-throughs in
`mve_vector_mem_operand'.

	Backported from mainline
	2020-05-28  Andrea Corallo  <andrea.corallo@arm.com>

gcc/
	* config/arm/arm.c (mve_vector_mem_operand): Fix unwanted
	fall-throughs.

Few MVE intrinsics like vldrbq_s32, vldrhq_s32 etc., the assembler instructions
generated by current compiler are wrong.
eg: vldrbq_s32 generates an assembly instructions `vldrb.s32 q0,[ip]`.
But as per Arm-arm second argument in above instructions must also be a low
register (<= r7). This patch fixes this issue by creating a new predicate
"mve_memory_operand" and constraint "Ux" which allows low registers as arguments
to the generated instructions depending on the mode of the argument. A new constraint
"Ul" is created to handle loading to PC-relative addressing modes for vector
store/load intrinsiscs.
All the corresponding MVE intrinsic generating wrong code-gen as vldrbq_s32
are modified in this patch.

	Backported from mainline
	2020-05-20  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>

gcc/
	PR target/94959
	* config/arm/arm-protos.h (arm_mode_base_reg_class): Function
	declaration.
	(mve_vector_mem_operand): Likewise.
	* config/arm/arm.c (thumb2_legitimate_address_p): For MVE target check
	the load from memory to a core register is legitimate for give mode.
	(mve_vector_mem_operand): Define function.
	(arm_print_operand): Modify comment.
	(arm_mode_base_reg_class): Define.
	* config/arm/arm.h (MODE_BASE_REG_CLASS): Modify to add check for
	TARGET_HAVE_MVE and expand to arm_mode_base_reg_class on TRUE.
	* config/arm/constraints.md (Ux): Likewise.
	(Ul): Likewise.
	* config/arm/mve.md (mve_mov): Replace constraint Us with Ux and also
	add support for missing Vector Store Register and Vector Load Register.
	Add a new alternative to support load from memory to PC (or label) in
	vector store/load.
	(mve_vstrbq_<supf><mode>): Modify constraint Us to Ux.
	(mve_vldrbq_<supf><mode>): Modify constriant Us to Ux, predicate to
	mve_memory_operand and also modify the MVE instructions to emit.
	(mve_vldrbq_z_<supf><mode>): Modify constraint Us to Ux.
	(mve_vldrhq_fv8hf): Modify constriant Us to Ux, predicate to
	mve_memory_operand and also modify the MVE instructions to emit.
	(mve_vldrhq_<supf><mode>): Modify constriant Us to Ux, predicate to
	mve_memory_operand and also modify the MVE instructions to emit.
	(mve_vldrhq_z_fv8hf): Likewise.
	(mve_vldrhq_z_<supf><mode>): Likewise.
	(mve_vldrwq_fv4sf): Likewise.
	(mve_vldrwq_<supf>v4si): Likewise.
	(mve_vldrwq_z_fv4sf): Likewise.
	(mve_vldrwq_z_<supf>v4si): Likewise.
	(mve_vld1q_f<mode>): Modify constriant Us to Ux.
	(mve_vld1q_<supf><mode>): Likewise.
	(mve_vstrhq_fv8hf): Modify constriant Us to Ux, predicate to
	mve_memory_operand.
	(mve_vstrhq_p_fv8hf): Modify constriant Us to Ux, predicate to
	mve_memory_operand and also modify the MVE instructions to emit.
	(mve_vstrhq_p_<supf><mode>): Likewise.
	(mve_vstrhq_<supf><mode>): Modify constriant Us to Ux, predicate to
	mve_memory_operand.
	(mve_vstrwq_fv4sf): Modify constriant Us to Ux.
	(mve_vstrwq_p_fv4sf): Modify constriant Us to Ux and also modify the MVE
	instructions to emit.
	(mve_vstrwq_p_<supf>v4si): Likewise.
	(mve_vstrwq_<supf>v4si): Likewise.Modify constriant Us to Ux.
	* config/arm/predicates.md (mve_memory_operand): Define.

gcc/testsuite/
	PR target/94959
	* gcc.target/arm/mve/intrinsics/mve_vector_float2.c: Modify.
	* gcc.target/arm/mve/intrinsics/mve_vldr.c: New test.
	* gcc.target/arm/mve/intrinsics/mve_vldr_z.c: Likewise.
	* gcc.target/arm/mve/intrinsics/mve_vstr.c: Likewise.
	* gcc.target/arm/mve/intrinsics/mve_vstr_p.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vld1q_f16.c: Modify.
	* gcc.target/arm/mve/intrinsics/vld1q_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vld1q_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vld1q_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vld1q_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vld1q_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vld1q_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vld1q_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vld1q_z_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vld1q_z_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vld1q_z_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vld1q_z_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vld1q_z_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vld1q_z_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vld1q_z_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vld1q_z_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vldrbq_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vldrbq_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vldrbq_z_s8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vldrbq_z_u8.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_s64.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_u64.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_z_s64.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_z_u64.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vldrhq_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vldrhq_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vldrhq_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vldrhq_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vldrhq_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vldrhq_z_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vldrhq_z_s16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vldrhq_z_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vldrhq_z_u16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vldrhq_z_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vldrwq_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vldrwq_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vldrwq_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vldrwq_z_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vldrwq_z_s32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vldrwq_z_u32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vuninitializedq_float.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vuninitializedq_float1.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vuninitializedq_int.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vuninitializedq_int1.c: Likewise.

Co-Authored-By: Andre Vieira  <andre.simoesdiasvieira@arm.com>

gcc/testsuite/ChangeLog:

	PR middle-end/95622
	* lib/target-supports.exp (check_effective_target_offloading_enabled):
	New.
	* c-c++-common/goacc/kernels-alias-ipa-pta-2.c: Use it for xfail.
	* c-c++-common/goacc/kernels-alias-ipa-pta-4.c: Likewise.
	* c-c++-common/goacc/kernels-alias-ipa-pta.c: Likewise.

Reviewed-by: Thomas Schwinge <thomas@codesourcery.com>
(cherry picked from commit e70fbee1a3dd9fdeb661366dbf3096d76c4e2d6e)