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  1. 04 Feb, 2016 15 commits
  3. 03 Feb, 2016 16 commits
  5. 02 Feb, 2016 9 commits
    • This testcase fails on 32-bit powerpc-linux with · a8394fa0 
      vector-compare-4.c

This testcase fails on 32-bit powerpc-linux with

Excess errors:
/home/segher/src/gcc/gcc/testsuite/c-c++-common/vector-compare-4.c:31:1: warning: GCC vector returned by reference: non-standard ABI extension with no compatibility guarantee

Fix this as in vector-compare-2.c .


testsuite/
	* c-c++-common/vector-compare-4.c: Prune "non-standard ABI extension"
	warning.

From-SVN: r233093
      Segher Boessenkool committed
    • wide-int.cc (canonize_uhwi): New function. · 321a2b65 
      	* wide-int.cc (canonize_uhwi): New function.
	(wi::divmod_internal): Use it.

From-SVN: r233092
      Jakub Jelinek committed
    • Add IA MCU tests for passing/returning of empty structures/unions · f3baa1d3 
      	* gcc.target/i386/iamcu/test_empty_structs_and_unions.c: New test.

From-SVN: r233090
      H.J. Lu committed
    • gimplify.c (omp_notice_variable): Add usage check. · eb077516 
      	gcc/
	* gimplify.c (omp_notice_variable): Add usage check.

	gcc/testsuite/
	* c-c++-common/goacc/routine-5.c: Add tests.

From-SVN: r233089
      James Norris committed
    • nvptx: do not use alternative spelling of unsigned comparisons · 578fb225 
      gcc/ChangeLog:
	* config/nvptx/nvptx.c (nvptx_print_operand): Treat LEU, GEU, LTU, GTU
        like LE, GE, LT, GT when emitting relational operator.

gcc/testsuite/ChangeLog:
	* gcc.target/nvptx/unsigned-cmp.c: New test.

From-SVN: r233088
      Alexander Monakov committed
    • libgomp: fix target-31.c testcase · 5854ee30 
      	* testsuite/libgomp.c/target-31.c: Fix testcase.

From-SVN: r233087
      Alexander Monakov committed
    • libgomp: fix teams-3/4 testcases · e70b6ad7 
      	* testsuite/libgomp.c/examples-4/teams-3.c: Add missing reduction
	clause.
	* testsuite/libgomp.c/examples-4/teams-4.c: Likewise.
	* testsuite/libgomp.fortran/examples-4/teams-3.f90: Add missing
	reduction and map clauses.
	* testsuite/libgomp.fortran/examples-4/teams-4.f90: Likewise.

From-SVN: r233086
      Alexander Monakov committed
    • Improve TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS target hook. · 31e2b5a3 
      Improve TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS target hook.  It turns out there
is another case where the register allocator uses the union of register classes
without checking that the cost of the resulting register class is lower than
both (see https://gcc.gnu.org/ml/gcc-patches/2015-12/msg01765.html ).  This
happens when the cost of the best and alternative class are both lower than the
memory cost.  In this case we typically end up with ALL_REGS as the allocno
class, which almost invariably results in bad allocations with many redundant
int<->FP moves (which are expensive on various cores).  AArch64 is affected by
this significantly due to supporting many scalar integer operations in SIMD.

Currently the TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS hook forces the class to
GENERAL_REGS if the allocno class is ALL_REGS and the register has an integer
mode.  This is bad if the best class happens to be FP_REGS.  To handle this
case as well, an extra argument is needed in the hook to pass the best class.
If the allocno class is ALL_REGS, but the best class isn't, we use the best
class instead (rather than using the mode to force to GENERAL_REGS or FP_REGS).

Previously this might happen:

r79: preferred FP_REGS, alternative GENERAL_REGS, allocno GENERAL_REGS
     a1 (r79,l0) best GENERAL_REGS, allocno GENERAL_REGS

a1(r79,l0) costs: CALLER_SAVE_REGS:5000,5000 GENERAL_REGS:5000,5000
                  FP_LO_REGS:0,0 FP_REGS:0,0 ALL_REGS:10000,10000 MEM:9000,9000

The proposed allocno is ALL_REGS (despite having the highest cost!) and is then
forced by the hook to GENERAL_REGS because r79 has integer mode.  However
FP_REGS has the lowest cost.  After this patch the choice is as follows:

r79: preferred FP_REGS, alternative GENERAL_REGS, allocno FP_REGS
     a1 (r79,l0) best FP_REGS, allocno FP_REGS

As a result it is now no longer a requirement to use register move costs that 
are larger than the memory move cost.  So it will be feasible to use realistic
costs for both without a huge penalty.


2016-02-02  Wilco Dijkstra  <wdijkstr@arm.com>

    gcc/
        * ira-costs.c (find_costs_and_classes): Add extra argument.
        * target.def (ira_change_pseudo_allocno_class): Add parameter.
        * targhooks.h (ira_change_pseudo_allocno_class): Likewise.
        * targhooks.c (ira_change_pseudo_allocno_class): Likewise.
        * config/aarch64/aarch64.c (aarch64_ira_change_pseudo_allocno_class)
        Add best_class parameter, and return it if not ALL_REGS.
        * config/mips/mips.c (mips_ira_change_pseudo_allocno_class):
        Add parameter.
        * doc/tm.texi (TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS):
        Update target hook.

From-SVN: r233084
      Wilco Dijkstra committed
    • This patch adds support for the TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS hook. · c64f7d37 
      When the cost of GENERAL_REGS and FP_REGS is identical, the register allocator
always uses ALL_REGS even when it has a much higher cost. The hook changes the
class to either FP_REGS or GENERAL_REGS depending on the mode of the register.
This results in better register allocation overall, fewer spills and reduced
codesize - particularly in SPEC2006 gamess.

2016-02-02  Wilco Dijkstra  <wdijkstr@arm.com>

    gcc/
	* config/aarch64/aarch64.c
	(TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS): New define.
	(aarch64_ira_change_pseudo_allocno_class): New function.

    gcc/testsuite/
	* gcc.target/aarch64/scalar_shift_1.c
	(test_corners_sisd_di): Improve force to SIMD register.
	(test_corners_sisd_si): Likewise.
	* gcc.target/aarch64/vect-ld1r-compile-fp.c:
	Remove scan-assembler check for ldr.

From-SVN: r233083
      Wilco Dijkstra committed