2017-08-01  Steve Ellcey  <sellcey@cavium.com>

	PR tree-optimization/80925
	* gcc.dg/vect/vect-28.c: Add
	--param vect-max-peeling-for-alignment=0 option.
	Remove unaligned access and peeling checks.
	* gcc.dg/vect/vect-33-big-array.c: Ditto.
	* gcc.dg/vect/vect-70.c: Ditto.
	* gcc.dg/vect/vect-87.c: Ditto.
	* gcc.dg/vect/vect-88.c: Ditto.
	* gcc.dg/vect/vect-91.c: Ditto.
	* gcc.dg/vect/vect-93.c: Ditto.

From-SVN: r250783

2017-08-01  Jerome Lambourg  <lambourg@adacore.com>
           Doug Rupp  <rupp@adacore.com>
           Olivier Hainque  <hainque@adacore.com>

  	gcc/
   	* config.gcc (arm-wrs-vxworks*): Rework to handle arm-wrs-vxworks7 as
   	well as arm-wrs-vxworks. Update target_cpu_name from arm6 (arch v3) to
   	arm8 (arch v4).
   	* config/arm/vxworks.h (MAYBE_TARGET_BPABI_CPP_BUILTINS): New, helper
   	for TARGET_OS_CPP_BUILTIN.
   	(TARGET_OS_CPP_BUILTIN): Invoke MAYBE_TARGET_BPABI_CPP_BUILTINS(),
   	refine CPU definitions for arm_arch5 and add those for arm_arch6 and
   	arm_arch7.
    	(MAYBE_ASM_ABI_SPEC): New, helper for SUBTARGET_EXTRA_ASM_SPEC,
   	passing required abi options to the assembler for EABI configurations.
   	(EXTRA_CC1_SPEC): New macro, to help prevent the implicit production
   	of .text.hot and .text.unlikely sections for kernel modules when
   	using ARM style exceptions.
   	(CC1_SPEC): Remove obsolete attempt at mimicking Diab toolchain
   	options. Add EXTRA_CC1_SPEC.
   	(VXWORKS_ENDIAN_SPEC): Adjust comment and remove handling of Diab
   	toolchain options.
   	(DWARF2_UNWIND_INFO): Redefine to handle the pre/post VxWorks 7
   	transition.
   	(ARM_TARGET2_DWARF_FORMAT): Define.
   	* config/arm/t-vxworks: Adjust multilib control to removal of the
   	Diab command line options.

   	libgcc/
   	* config.host (arm-wrs-vxworks*): Rework to handle arm-wrs-vxworks7
   	as well as arm-wrs-vxworks.
   	* config/arm/t-vxworks7: New file.  Add unwind-arm-vxworks.c to
   	LIB2ADDEH.
   	* config/arm/unwind-arm-vxworks.c: New file. Provide dummy
   	__exidx_start and __exidx_end for downloadable modules.


Co-Authored-By: Doug Rupp <rupp@adacore.com>
Co-Authored-By: Olivier Hainque <hainque@adacore.com>

From-SVN: r250781

2017-08-01  Martin Liska  <mliska@suse.cz>

	PR gcov-profile/81561
	* gcov.c (unblock): Make unblocking safe as we need to preserve
	index correspondence of blocks and block_lists.

From-SVN: r250780

Use signed loop iteration variable in nvtpx/slp* test-cases to work around
PR tree-optimizaion/81635.

2017-08-01  Tom de Vries  <tom@codesourcery.com>

	* gcc.target/nvptx/slp-2.c (foo): Use signed loop iteration variable.
	* gcc.target/nvptx/slp.c (foo): Same.

From-SVN: r250778

2017-08-01  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/81181
	* tree-ssa-pre.c (compute_antic_aux): Defer clean() to ...
	(compute_antic): ... end of iteration here.

	* gcc.dg/torture/pr81181.c: New testcase.

From-SVN: r250777

2017-08-01  Olivier Hainque  <hainque@adacore.com>

	* config/t-vxworks (LIBGCC2_INCLUDES): Start with -I. after -nostdinc.
	* config/t-vxworks7: Likewise.

From-SVN: r250776

2017-08-01  Olivier Hainque  <hainque@adacore.com>

	* config/t-vxworks: Instead of redefining LIB2ADD,
	augment LIB2ADDEH with vxlib.c and vxlib-tls.c.

From-SVN: r250775

gcc/

	* common.opt (ftree-vectorize): No longer set flag_tree_vectorize.
	(ftree-loop-vectorize): Set as EnabledBy ftree-vectorize.
	(ftree-slp-vectorize): Likewise.
	* omp-expand (expand_omp_simd): Remove flag_tree_vectorize, as it
	can no longer be set independent of flag_tree_loop_vectorize.
	* omp-general.c (emp_max_vf): Likewise.
	* opts.c (enable_fdo_optimizations): Remove references to
	flag_tree_vectorize, these are now implicit.
	(common_handle_option): Remove handling for OPT_ftree_vectorize,
	and leave it for the options machinery.

From-SVN: r250774

From-SVN: r250773

2017-08-01  Martin Liska  <mliska@suse.cz>

	PR middle-end/70140
	* gcc.dg/string-opt-1.c: Adjust test-case to scan for memcpy.
2017-08-01  Martin Liska  <mliska@suse.cz>

	PR middle-end/70140
	* builtins.c (expand_builtin_memcpy_args): Remove.
	(expand_builtin_memcpy): Call newly added function
	expand_builtin_memory_copy_args.
	(expand_builtin_memcpy_with_bounds): Likewise.
	(expand_builtin_mempcpy): Remove last argument.
	(expand_builtin_mempcpy_with_bounds): Likewise.
	(expand_builtin_memory_copy_args): New function created from
	expand_builtin_mempcpy_args with small modifications.
	(expand_builtin_mempcpy_args): Remove.
	(expand_builtin_stpcpy): Remove unused argument.
	(expand_builtin): Likewise.
	(expand_builtin_with_bounds): Likewise.

From-SVN: r250771

2017-08-01  Tamar Christina  <tamar.christina@arm.com>

	* gcc.target/aarch64/dbl_mov_immediate_1.c:
	Use conditional assembler scans.

From-SVN: r250770

	PR target/81641
	* config/i386/i386.c (ix86_print_operand_address_as): For -masm=intel
	print "ds:" only for immediates in generic address space.

testsuite/ChangeLog:

	PR target/81641
	* gcc.target/i386/pr81641.c: New test.

From-SVN: r250769

	PR target/81639
	* config/i386/i386.c (ix86_funciton_naked): New prototype.
	(ix86_function_ok_for_sibcall): Return false for naked functions.

testsuite/ChangeLog:

	PR target/81639
	* gcc.target/i386/pr81639.c: New test.

From-SVN: r250768

2017-08-01  Richard Biener  <rguenther@suse.de>

	* tree-ssa-pre.c (print_pre_expr): Handle NULL expr.
	(compute_antic): Seed worklist with exit block predecessors.
	* cfganal.c (dfs_find_deadend): For a cycle return the source
	of the edge closing it.

	* gcc.dg/tree-ssa/ssa-dce-3.c: Adjust.
	* gcc.dg/tree-ssa/split-path-5.c: Remove case with just dead
	endless loop.
	* gcc.dg/uninit-23.c: Adjust.

From-SVN: r250767

	* config/aarch64/aarch64.c
	(aarch64_can_const_movi_rtx_p): Move 0 check.

From-SVN: r250766

	* tree.h (POINTER_TYPE_OVERFLOW_UNDEFINED): Delete.
	* fold-const.c (fold_comparison, fold_binary_loc): Delete use of
	above macro.
	* match.pd: Ditto in address comparison pattern.

	gcc/testsuite
	* gcc.dg/no-strict-overflow-7.c: Revise comment and test string.
	* gcc.dg/tree-ssa/pr81388-1.c: Ditto.

From-SVN: r250765

re PR tree-optimization/81627 (ICE on valid code at -O3: in check_loop_closed_ssa_use, at tree-ssa-loop-manip.c:707)

	PR tree-optimization/81627
	* tree-predcom.c (prepare_finalizers): Always rewrite into loop
	closed ssa form for store-store chain.

	gcc/testsuite
	* gcc.dg/tree-ssa/pr81627.c: New.

From-SVN: r250764

re PR tree-optimization/81620 (ICE in is_inv_store_elimination_chain, at tree-predcom.c:1651 with -O3)

	PR tree-optimization/81620
	* tree-predcom.c (add_ref_to_chain): Don't set has_max_use_after
	for store-store chain.

	gcc/testsuite
	* gcc.dg/tree-ssa/pr81620-1.c: New.
	* gcc.dg/tree-ssa/pr81620-2.c: New.

From-SVN: r250763

re PR fortran/53542 (Diagnostic of USE-associated variables shows original instead of renamed symbol name)

2017-08-01  Dominique d'Humieres  <dominiq@lps.ens.fr>

	PR fortran/53542
	* expr.c (gfc_check_init_expr): Use the renamed name.

	PR testsuite/53542
	* gfortran.dg/use_30.f90: New test.

From-SVN: r250762

	PR tree-optimization/81588
	* tree-ssa-reassoc.c (optimize_range_tests_var_bound): If
	ranges[i].in_p, invert comparison code ccode.  For >/>=,
	swap rhs1 and rhs2 and comparison code unconditionally,
	for </<= don't do that.  Don't swap rhs1/rhs2 again if
	ranges[i].in_p, instead invert comparison code ccode if
	opcode or oe->rank is BIT_IOR_EXPR.

	* gcc.dg/tree-ssa/pr81588.c: New test.
	* gcc.dg/pr81588.c: New test.
	* gcc.c-torture/execute/pr81588.c: New test.

From-SVN: r250760

re PR target/80846 (auto-vectorized AVX2 horizontal sum should narrow to 128b right away, to be more efficient for Ryzen and Intel)

	PR target/80846
	* optabs.def (vec_extract_optab, vec_init_optab): Change from
	a direct optab to conversion optab.
	* optabs.c (expand_vector_broadcast): Use convert_optab_handler
	with GET_MODE_INNER as last argument instead of optab_handler.
	* expmed.c (extract_bit_field_1): Likewise.  Use vector from
	vector extraction if possible and optab is available.
	* expr.c (store_constructor): Use convert_optab_handler instead
	of optab_handler.  Use vector initialization from smaller
	vectors if possible and optab is available.
	* tree-vect-stmts.c (vectorizable_load): Likewise.
	* doc/md.texi (vec_extract, vec_init): Document that the optabs
	now have two modes.
	* config/i386/i386.c (ix86_expand_vector_init): Handle expansion
	of vec_init from half-sized vectors with the same element mode.
	* config/i386/sse.md (ssehalfvecmode): Add V4TI case.
	(ssehalfvecmodelower, ssescalarmodelower): New mode attributes.
	(reduc_plus_scal_v8df, reduc_plus_scal_v4df, reduc_plus_scal_v2df,
	reduc_plus_scal_v16sf, reduc_plus_scal_v8sf, reduc_plus_scal_v4sf,
	reduc_<code>_scal_<mode>, reduc_umin_scal_v8hi): Add element mode
	after mode in gen_vec_extract* calls.
	(vec_extract<mode>): Renamed to ...
	(vec_extract<mode><ssescalarmodelower>): ... this.
	(vec_extract<mode><ssehalfvecmodelower>): New expander.
	(rotl<mode>3, rotr<mode>3, <shift_insn><mode>3, ashrv2di3): Add
	element mode after mode in gen_vec_init* calls.
	(VEC_INIT_HALF_MODE): New mode iterator.
	(vec_init<mode>): Renamed to ...
	(vec_init<mode><ssescalarmodelower>): ... this.
	(vec_init<mode><ssehalfvecmodelower>): New expander.
	* config/i386/mmx.md (vec_extractv2sf): Renamed to ...
	(vec_extractv2sfsf): ... this.
	(vec_initv2sf): Renamed to ...
	(vec_initv2sfsf): ... this.
	(vec_extractv2si): Renamed to ...
	(vec_extractv2sisi): ... this.
	(vec_initv2si): Renamed to ...
	(vec_initv2sisi): ... this.
	(vec_extractv4hi): Renamed to ...
	(vec_extractv4hihi): ... this.
	(vec_initv4hi): Renamed to ...
	(vec_initv4hihi): ... this.
	(vec_extractv8qi): Renamed to ...
	(vec_extractv8qiqi): ... this.
	(vec_initv8qi): Renamed to ...
	(vec_initv8qiqi): ... this.
	* config/rs6000/vector.md (VEC_base_l): New mode attribute.
	(vec_init<mode>): Renamed to ...
	(vec_init<mode><VEC_base_l>): ... this.
	(vec_extract<mode>): Renamed to ...
	(vec_extract<mode><VEC_base_l>): ... this.
	* config/rs6000/paired.md (vec_initv2sf): Renamed to ...
	(vec_initv2sfsf): ... this.
	* config/rs6000/altivec.md (splitter, altivec_copysign_v4sf3,
	vec_unpacku_hi_v16qi, vec_unpacku_hi_v8hi, vec_unpacku_lo_v16qi,
	vec_unpacku_lo_v8hi, mulv16qi3, altivec_vreve<mode>2): Add
	element mode after mode in gen_vec_init* calls.
	* config/aarch64/aarch64-simd.md (vec_init<mode>): Renamed to ...
	(vec_init<mode><Vel>): ... this.
	(vec_extract<mode>): Renamed to ...
	(vec_extract<mode><Vel>): ... this.
	* config/aarch64/iterators.md (Vel): New mode attribute.
	* config/s390/s390.c (s390_expand_vec_strlen, s390_expand_vec_movstr):
	Add element mode after mode in gen_vec_extract* calls.
	* config/s390/vector.md (non_vec_l): New mode attribute.
	(vec_extract<mode>): Renamed to ...
	(vec_extract<mode><non_vec_l>): ... this.
	(vec_init<mode>): Renamed to ...
	(vec_init<mode><non_vec_l>): ... this.
	* config/s390/s390-builtins.def (s390_vlgvb, s390_vlgvh, s390_vlgvf,
	s390_vlgvf_flt, s390_vlgvg, s390_vlgvg_dbl): Add element mode after
	vec_extract mode.
	* config/arm/iterators.md (V_elem_l): New mode attribute.
	* config/arm/neon.md (vec_extract<mode>): Renamed to ...
	(vec_extract<mode><V_elem_l>): ... this.
	(vec_extractv2di): Renamed to ...
	(vec_extractv2didi): ... this.
	(vec_init<mode>): Renamed to ...
	(vec_init<mode><V_elem_l>): ... this.
	(reduc_plus_scal_<mode>, reduc_plus_scal_v2di, reduc_smin_scal_<mode>,
	reduc_smax_scal_<mode>, reduc_umin_scal_<mode>,
	reduc_umax_scal_<mode>, neon_vget_lane<mode>, neon_vget_laneu<mode>):
	Add element mode after gen_vec_extract* calls.
	* config/mips/mips-msa.md (vec_init<mode>): Renamed to ...
	(vec_init<mode><unitmode>): ... this.
	(vec_extract<mode>): Renamed to ...
	(vec_extract<mode><unitmode>): ... this.
	* config/mips/loongson.md (vec_init<mode>): Renamed to ...
	(vec_init<mode><unitmode>): ... this.
	* config/mips/mips-ps-3d.md (vec_initv2sf): Renamed to ...
	(vec_initv2sfsf): ... this.
	(vec_extractv2sf): Renamed to ...
	(vec_extractv2sfsf): ... this.
	(reduc_plus_scal_v2sf, reduc_smin_scal_v2sf, reduc_smax_scal_v2sf):
	Add element mode after gen_vec_extract* calls.
	* config/mips/mips.md (unitmode): New mode iterator.
	* config/spu/spu.c (spu_expand_prologue, spu_allocate_stack,
	spu_builtin_extract): Add element mode after gen_vec_extract* calls.
	* config/spu/spu.md (inner_l): New mode attribute.
	(vec_init<mode>): Renamed to ...
	(vec_init<mode><inner_l>): ... this.
	(vec_extract<mode>): Renamed to ...
	(vec_extract<mode><inner_l>): ... this.
	* config/sparc/sparc.md (veltmode): New mode iterator.
	(vec_init<VMALL:mode>): Renamed to ...
	(vec_init<VMALL:mode><VMALL:veltmode>): ... this.
	* config/ia64/vect.md (vec_initv2si): Renamed to ...
	(vec_initv2sisi): ... this.
	(vec_initv2sf): Renamed to ...
	(vec_initv2sfsf): ... this.
	(vec_extractv2sf): Renamed to ...
	(vec_extractv2sfsf): ... this.
	* config/powerpcspe/vector.md (VEC_base_l): New mode attribute.
	(vec_init<mode>): Renamed to ...
	(vec_init<mode><VEC_base_l>): ... this.
	(vec_extract<mode>): Renamed to ...
	(vec_extract<mode><VEC_base_l>): ... this.
	* config/powerpcspe/paired.md (vec_initv2sf): Renamed to ...
	(vec_initv2sfsf): ... this.
	* config/powerpcspe/altivec.md (splitter, altivec_copysign_v4sf3,
	vec_unpacku_hi_v16qi, vec_unpacku_hi_v8hi, vec_unpacku_lo_v16qi,
	vec_unpacku_lo_v8hi, mulv16qi3): Add element mode after mode in
	gen_vec_init* calls.

From-SVN: r250759

2017-08-01  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/81297
	* tree-vrp.c (get_single_symbol): Remove assert, instead drop
	TREE_OVERFLOW from INTEGER_CSTs.

	* gcc.dg/torture/pr81297.c: New testcase.

From-SVN: r250758

	* gcc.target/i386/naked-1.c (dg-options): Add -fno-pic.

From-SVN: r250757

From-SVN: r250756

2017-07-31  Steve Ellcey  <sellcey@cavium.com>

	PR tree-optimization/80925
	* gcc.dg/vect/no-section-anchors-vect-69.c: Add 
	--param vect-max-peeling-for-alignment=0 option.
	Remove unaligned access and peeling checks.
	* gcc.dg/vect/section-anchors-vect-69.c: Ditto.

From-SVN: r250752

gcc/testsuite/ChangeLog:

2017-07-31  Carl Love  <cel@us.ibm.com>

	* gcc.target/powerpc/builtins-4-runnable.c: Fix dg argument that got
	missed in commit 250746.

From-SVN: r250751

From-SVN: r250750

	* config/rs6000/rs6000.c (enum rs6000_reg_type): Delete trailing comma.

From-SVN: r250749

From-SVN: r250747

gcc/ChangeLog:

2017-07-31  Carl Love  <cel@us.ibm.com>

	* config/rs6000/rs6000-c: Add support for built-in functions
	vector signed char vec_xl_be (signed long long, signed char *);
	vector unsigned char vec_xl_be (signed long long, unsigned char *);
	vector signed int vec_xl_be (signed long long, signed int *);
	vector unsigned int vec_xl_be (signed long long, unsigned int *);
	vector signed long long vec_xl_be (signed long long, signed long long *);
	vector unsigned long long vec_xl_be (signed long long, unsigned long long *);
	vector signed short vec_xl_be (signed long long, signed short *);
	vector unsigned short vec_xl_be (signed long long, unsigned short *);
	vector double vec_xl_be (signed long long, double *);
	vector float vec_xl_be (signed long long, float *);
	* config/rs6000/altivec.h (vec_xl_be): Add #define.
	* config/rs6000/rs6000-builtin.def (XL_BE_V16QI, XL_BE_V8HI, XL_BE_V4SI,
	XL_BE_V2DI, XL_BE_V4SF, XL_BE_V2DF, XL_BE): Add definitions for the builtins.
	* config/rs6000/rs6000.c (altivec_expand_xl_be_builtin): Add function.
	(altivec_expand_builtin): Add switch statement to call altivec_expand_xl_be
	for each builtin.
	(altivec_init_builtins): Add def_builtin for _builtin_vsx_le_be_v8hi,
	__builtin_vsx_le_be_v4si, __builtin_vsx_le_be_v2di, __builtin_vsx_le_be_v4sf,
	__builtin_vsx_le_be_v2df, __builtin_vsx_le_be_v16qi.
	* doc/extend.texi: Update the built-in documentation file for the
	new built-in functions.

gcc/testsuite/ChangeLog:

2017-07-31  Carl Love  <cel@us.ibm.com>

	* gcc.target/powerpc/builtins-4-runnable.c: Add test cases for the
	new builtins.

From-SVN: r250746

pr79793-1.c and pr79793-2.c are failed when GCC is configured with
--with-cpu=slm since lea is used to adjust stack, instead of sub/add.
This patch uses -mtune=generic to always generate sub and add.

	* gcc.target/i386/pr79793-1.c: Compile with -mtune=generic.
	* gcc.target/i386/pr79793-2.c: Likewise.

From-SVN: r250745

	PR libstdc++/81599
	* include/bits/stl_stack.h: Fix typo.

From-SVN: r250743

	PR target/25967
	* config/i386/i386.c (ix86_allocate_stack_slots_for_args):
	New function.
	(TARGET_ALLOCATE_STACK_SLOTS_FOR_ARGS): Define.

testsuite/ChangeLog:

	PR target/25967
	* gcc.target/i386/naked-3.c (dg-options): Use -O0.
	(naked): Add attribute regparm(1) for x86_32 targets.
	Add integer argument.  Remove global "data" variable.
	(main): Pass integer argument to naked function.
	* gcc.target/i386/naked-4.c: New test.

From-SVN: r250742

From-SVN: r250741

With IBM z14 officially announced we can add support for z14 as
preferred CPU name.  We still pass arch12 to Binutils in order to keep
older Binutils versions supported.

gcc/ChangeLog:

2017-07-31  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>

	* config.gcc: Add z14.
	* config/s390/driver-native.c (s390_host_detect_local_cpu): Add
	CPU model numbers for z13s and z14.
	* config/s390/s390-c.c (s390_resolve_overloaded_builtin): Replace
	arch12 with z14.
	* config/s390/s390-opts.h (enum processor_type): Rename
	PROCESSOR_ARCH12 to PROCESSOR_3906_Z14.
	* config/s390/s390.c (processor_table): Add field for CPU name to
	be passed to Binutils.
	(s390_asm_output_machine_for_arch): Use the new field in
	processor_table for Binutils.
	(s390_expand_builtin): Replace arch12 with z14.
	(s390_issue_rate): Rename PROCESSOR_ARCH12 to PROCESSOR_3906_Z14.
	(s390_get_sched_attrmask): Likewise.
	(s390_get_unit_mask): Likewise.
	* config/s390/s390.opt: Add z14 to processor_type enum.

From-SVN: r250739

2017-07-31  Martin Jambor  <mjambor@suse.cz>

	PR hsa/81477
	* ipa-fnsummary.c (ipa_fn_summary_generate): Set versionable
	regardless of optimization level.

From-SVN: r250738

2017-07-31  Jan Hubicka <hubicka@ucw.cz>
	    Martin Liska  <mliska@suse.cz>

	* c-typeck.c (c_finish_goto_label): Build gimple predict
	stament.
2017-07-31  Jan Hubicka <hubicka@ucw.cz>
	    Martin Liska  <mliska@suse.cz>

	* predict.def: Remove old comment and adjust probability.
	* gimplify.c (should_warn_for_implicit_fallthrough): Ignore
	PREDICT statements.
2017-07-31  Jan Hubicka <hubicka@ucw.cz>
	    Martin Liska  <mliska@suse.cz>

	* gcc.dg/predict-15.c: New test.
	* gcc.dg/tree-ssa/vrp24.c: Update scanned pattern.
2017-07-31  Jan Hubicka <hubicka@ucw.cz>
	    Martin Liska  <mliska@suse.cz>

	* pt.c (tsubst_copy): Copy PREDICT_EXPR.
	* semantics.c (finish_goto_stmt): Build gimple predict
	stament.
	* constexpr.c (potential_constant_expression_1): Handle
	PREDICT_EXPR.

Co-Authored-By: Martin Liska <mliska@suse.cz>

From-SVN: r250737

	PR target/25967
	* config/i386/i386.c (ix86_function_naked): New function.
	(ix86_can_use_return_insn_p): Return false for naked functions.
	(ix86_expand_prologue): Skip prologue for naked functions.
	(ix86_expand_epilogue): Skip epilogue for naked functions
	and emit trap instruction.
	(ix86_warn_func_return): New function.
	(ix86_attribute_table): Add "naked" attribute specification.
	(TARGET_WARN_FUNC_RETURN): Define.
	* doc/extend.texi (x86 Function Attributes) <naked>: Document it.

testsuite/ChangeLog:

	PR target/25967
	* gcc.target/i386/naked-1.c: New test.
	* gcc.target/i386/naked-2.c: Ditto.
	* gcc.target/i386/naked-3.c: Ditto.
	* gcc.target/x86_64/abi/ms-sysv/ms-sysv.c: Remove
	do_test_body0 stub function, use attribute "naked" instead.
	* gcc.dg/pr44290-1.c: Use naked_functions effective target.
	* gcc.dg/pr44290-2.c: Ditto.

From-SVN: r250736

2017-07-31  Thomas Koenig  <tkoenig@gcc.gnu.org>

	PR fortran/81581
	* m4/ifuntion.m4 (name`'rtype_qual`_'atype_code): Perform check
	for dim.
	(`m'name`'rtype_qual`_'atype_code): Likewise. Change type of rank
	and tim to index_type.
	(`s'name`'rtype_qual`_'atype_code): Perform check for dim.
	* generated/iall_i16.c: Regenerated.
	* generated/iall_i1.c: Regenerated.
	* generated/iall_i2.c: Regenerated.
	* generated/iall_i4.c: Regenerated.
	* generated/iall_i8.c: Regenerated.
	* generated/iany_i16.c: Regenerated.
	* generated/iany_i1.c: Regenerated.
	* generated/iany_i2.c: Regenerated.
	* generated/iany_i4.c: Regenerated.
	* generated/iany_i8.c: Regenerated.
	* generated/iparity_i16.c: Regenerated.
	* generated/iparity_i1.c: Regenerated.
	* generated/iparity_i2.c: Regenerated.
	* generated/iparity_i4.c: Regenerated.
	* generated/iparity_i8.c: Regenerated.
	* generated/maxloc1_16_i16.c: Regenerated.
	* generated/maxloc1_16_i1.c: Regenerated.
	* generated/maxloc1_16_i2.c: Regenerated.
	* generated/maxloc1_16_i4.c: Regenerated.
	* generated/maxloc1_16_i8.c: Regenerated.
	* generated/maxloc1_16_r10.c: Regenerated.
	* generated/maxloc1_16_r16.c: Regenerated.
	* generated/maxloc1_16_r4.c: Regenerated.
	* generated/maxloc1_16_r8.c: Regenerated.
	* generated/maxloc1_4_i16.c: Regenerated.
	* generated/maxloc1_4_i1.c: Regenerated.
	* generated/maxloc1_4_i2.c: Regenerated.
	* generated/maxloc1_4_i4.c: Regenerated.
	* generated/maxloc1_4_i8.c: Regenerated.
	* generated/maxloc1_4_r10.c: Regenerated.
	* generated/maxloc1_4_r16.c: Regenerated.
	* generated/maxloc1_4_r4.c: Regenerated.
	* generated/maxloc1_4_r8.c: Regenerated.
	* generated/maxloc1_8_i16.c: Regenerated.
	* generated/maxloc1_8_i1.c: Regenerated.
	* generated/maxloc1_8_i2.c: Regenerated.
	* generated/maxloc1_8_i4.c: Regenerated.
	* generated/maxloc1_8_i8.c: Regenerated.
	* generated/maxloc1_8_r10.c: Regenerated.
	* generated/maxloc1_8_r16.c: Regenerated.
	* generated/maxloc1_8_r4.c: Regenerated.
	* generated/maxloc1_8_r8.c: Regenerated.
	* generated/maxval_i16.c: Regenerated.
	* generated/maxval_i1.c: Regenerated.
	* generated/maxval_i2.c: Regenerated.
	* generated/maxval_i4.c: Regenerated.
	* generated/maxval_i8.c: Regenerated.
	* generated/maxval_r10.c: Regenerated.
	* generated/maxval_r16.c: Regenerated.
	* generated/maxval_r4.c: Regenerated.
	* generated/maxval_r8.c: Regenerated.
	* generated/minloc1_16_i16.c: Regenerated.
	* generated/minloc1_16_i1.c: Regenerated.
	* generated/minloc1_16_i2.c: Regenerated.
	* generated/minloc1_16_i4.c: Regenerated.
	* generated/minloc1_16_i8.c: Regenerated.
	* generated/minloc1_16_r10.c: Regenerated.
	* generated/minloc1_16_r16.c: Regenerated.
	* generated/minloc1_16_r4.c: Regenerated.
	* generated/minloc1_16_r8.c: Regenerated.
	* generated/minloc1_4_i16.c: Regenerated.
	* generated/minloc1_4_i1.c: Regenerated.
	* generated/minloc1_4_i2.c: Regenerated.
	* generated/minloc1_4_i4.c: Regenerated.
	* generated/minloc1_4_i8.c: Regenerated.
	* generated/minloc1_4_r10.c: Regenerated.
	* generated/minloc1_4_r16.c: Regenerated.
	* generated/minloc1_4_r4.c: Regenerated.
	* generated/minloc1_4_r8.c: Regenerated.
	* generated/minloc1_8_i16.c: Regenerated.
	* generated/minloc1_8_i1.c: Regenerated.
	* generated/minloc1_8_i2.c: Regenerated.
	* generated/minloc1_8_i4.c: Regenerated.
	* generated/minloc1_8_i8.c: Regenerated.
	* generated/minloc1_8_r10.c: Regenerated.
	* generated/minloc1_8_r16.c: Regenerated.
	* generated/minloc1_8_r4.c: Regenerated.
	* generated/minloc1_8_r8.c: Regenerated.
	* generated/minval_i16.c: Regenerated.
	* generated/minval_i1.c: Regenerated.
	* generated/minval_i2.c: Regenerated.
	* generated/minval_i4.c: Regenerated.
	* generated/minval_i8.c: Regenerated.
	* generated/minval_r10.c: Regenerated.
	* generated/minval_r16.c: Regenerated.
	* generated/minval_r4.c: Regenerated.
	* generated/minval_r8.c: Regenerated.
	* generated/norm2_r10.c: Regenerated.
	* generated/norm2_r16.c: Regenerated.
	* generated/norm2_r4.c: Regenerated.
	* generated/norm2_r8.c: Regenerated.
	* generated/parity_l16.c: Regenerated.
	* generated/parity_l1.c: Regenerated.
	* generated/parity_l2.c: Regenerated.
	* generated/parity_l4.c: Regenerated.
	* generated/parity_l8.c: Regenerated.
	* generated/product_c10.c: Regenerated.
	* generated/product_c16.c: Regenerated.
	* generated/product_c4.c: Regenerated.
	* generated/product_c8.c: Regenerated.
	* generated/product_i16.c: Regenerated.
	* generated/product_i1.c: Regenerated.
	* generated/product_i2.c: Regenerated.
	* generated/product_i4.c: Regenerated.
	* generated/product_i8.c: Regenerated.
	* generated/product_r10.c: Regenerated.
	* generated/product_r16.c: Regenerated.
	* generated/product_r4.c: Regenerated.
	* generated/product_r8.c: Regenerated.
	* generated/sum_c10.c: Regenerated.
	* generated/sum_c16.c: Regenerated.
	* generated/sum_c4.c: Regenerated.
	* generated/sum_c8.c: Regenerated.
	* generated/sum_i16.c: Regenerated.
	* generated/sum_i1.c: Regenerated.
	* generated/sum_i2.c: Regenerated.
	* generated/sum_i4.c: Regenerated.
	* generated/sum_i8.c: Regenerated.
	* generated/sum_r10.c: Regenerated.
	* generated/sum_r16.c: Regenerated.
	* generated/sum_r4.c: Regenerated.
	* generated/sum_r8.c: Regenerated.

2017-07-31  Thomas Koenig  <tkoenig@gcc.gnu.org>

	PR fortran/81581
	* gfortran.dg/dim_sum_1.f90: New test case.
	* gfortran.dg/dim_sum_2.f90: New test case.
	* gfortran.dg/dim_sum_3.f90: New test case.

From-SVN: r250735

From-SVN: r250734