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lvzhengyang
riscv-gcc-1
Commits
225dcdec
Commit
225dcdec
authored
Aug 01, 2017
by
Tamar Christina
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Reverted 250770
From-SVN: r250773
parent
98b7180c
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gcc/testsuite/ChangeLog
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gcc/testsuite/gcc.target/aarch64/dbl_mov_immediate_1.c
+3
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gcc/testsuite/ChangeLog
View file @
225dcdec
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@@ -3,11 +3,6 @@
PR middle-end/70140
* gcc.dg/string-opt-1.c: Adjust test-case to scan for memcpy.
2017-08-01 Tamar Christina <tamar.christina@arm.com>
* gcc.target/aarch64/dbl_mov_immediate_1.c:
Use conditional assembler scans.
2017-08-01 Uros Bizjak <ubizjak@gmail.com>
PR target/81641
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gcc/testsuite/gcc.target/aarch64/dbl_mov_immediate_1.c
View file @
225dcdec
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@@ -46,11 +46,8 @@ double d4(void)
/* { dg-final { scan-assembler-times "fmov\td\[0-9\]+, 1\\\.5e\\\+0" 1 } } */
/* { dg-final { scan-assembler-times "mov\tx\[0-9\]+, 25838523252736" 1 { target aarch64-*-* } } } */
/* { dg-final { scan-assembler-times "movk\tx\[0-9\]+, 0x40fe, lsl 48" 1 { target aarch64-*-* } } } */
/* { dg-final { scan-assembler-times "mov\tx\[0-9\]+, -9223372036854775808" 1 { target aarch64-*-* } } } */
/* { dg-final { scan-assembler-times "mov\tx\[0-9\]+, 6016" 1 { target aarch64_be-*-* } } } */
/* { dg-final { scan-assembler-times "movk\tx\[0-9\]+, 0x40fe, lsl 16" 1 { target aarch64_be-*-* } } } */
/* { dg-final { scan-assembler-times "mov\tx\[0-9\]+, 2147483648" 1 { target aarch64_be-*-* } } } */
/* { dg-final { scan-assembler-times "mov\tx\[0-9\]+, 25838523252736" 1 } } */
/* { dg-final { scan-assembler-times "movk\tx\[0-9\]+, 0x40fe, lsl 48" 1 } } */
/* { dg-final { scan-assembler-times "mov\tx\[0-9\]+, -9223372036854775808" 1 } } */
/* { dg-final { scan-assembler-times "fmov\td\[0-9\]+, x\[0-9\]+" 2 } } */
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