PR target/86048
	* config/i386/winnt.c (i386_pe_seh_cold_init): Do not emit negative
	offsets for register save directives.  Emit a second batch of save
	directives, if need be, when the function accesses prior frames.

From-SVN: r261544

Accept at most a single constant for fma patterns.

gcc/
2018-03-21  Claudiu Zissulescu  <claziss@synopsys.com>

	* config/arc/fpu.md (fmasf4): Force operand to register.
	(fnmasf4): Likewise.

gcc/testsuite
2018-03-21  Claudiu Zissulescu  <claziss@synopsys.com>

	* gcc.target/arc/fma-1.c: New test.

From-SVN: r261543

For ARC700, adding padding if necessary to avoid a mispredict.  A
return could happen immediately after the function start.  A
call/return and return/return must be 6 bytes apart to avoid
mispredict.

The old implementation was doing this operation very late in the
compilation process, and the additional nop instructions and/or
forcing some other instruction to take their long form was not taken
into account when generating brcc instructions. Thus, wrong code could
be generated.

gcc/
2017-03-24  Claudiu Zissulescu  <claziss@synopsys.com>

	* config/arc/arc-protos.h (arc_pad_return): Remove.
	* config/arc/arc.c (machine_function): Remove force_short_suffix
	and size_reason.
	(arc_print_operand): Adjust printing of '&'.
	(arc_verify_short): Remove conditional printing of short suffix.
	(arc_final_prescan_insn): Remove reference to size_reason.
	(pad_return): New function.
	(arc_reorg): Call pad_return.
	(arc_pad_return): Remove.
	(arc_init_machine_status): Remove reference to force_short_suffix.
	* config/arc/arc.md (vunspec): Add VUNSPEC_ARC_BLOCKAGE.
	(attr length): When attribute iscompact is true force to 2
	regardless; in the case of maybe check if we want to force the
	instruction to have 4 bytes length.
	(nopv): Change it to generate 4 byte long nop as well.
	(blockage): New pattern.
	(simple_return): Remove call to arc_pad_return.
	(p_return_i): Likewise.

gcc/testsuite/
2017-03-24  Claudiu Zissulescu  <claziss@synopsys.com>

	* gcc.target/arc/pr9001107555.c: New file.

From-SVN: r261542

If no specs file is provided, default to nosys library.

gcc/
2017-05-03  Claudiu Zissulescu  <claziss@synopsys.com>

	* config/arc/elf.h (LINK_GCC_C_SEQUENCE_SPEC): Define.

From-SVN: r261541

gcc/
2017-05-03  Claudiu Zissulescu  <claziss@synopsys.com>

	* config/arc/builtins.def (SYNC): SYNC instruction is valid on all
	ARC cores.

From-SVN: r261540

gcc/
2017-05-02  Claudiu Zissulescu  <claziss@synopsys.com>

	* config/arc/arc.c (atomic_exchangesi): EX instruction is default
	for ARC700 and ARCv2.

From-SVN: r261539

re PR tree-optimization/86076 (ICE: verify_gimple failed (error: location references block not in block tree))

2018-06-13  Chenghua Xu <paul.hua.gm@gmail.com>

	PR target/86076
	* config/mips/loongson.md (vec_setv4hi): Gen_lowpart for
	operands[2] instead of operands[1].

From-SVN: r261538

2018-06-13  François Dumont  <fdumont@gcc.gnu.org>

	* include/debug/debug.h (__glibcxx_requires_can_increment_range): New.
	(__glibcxx_requires_can_decrement_range): New.

From-SVN: r261537

	* typeck.c (structural_comptypes) [TEMPLATE_TYPE_PARM]: Check
	CLASS_PLACEHOLDER_TEMPLATE.

From-SVN: r261536

From-SVN: r261535

This patch fixes an LRA cycling problem on the attached testcase.
The original insn was:

(insn 74 72 76 8 (set (reg:V2DI 287 [ _166 ])
        (subreg:V2DI (reg/v/f:DI 112 [ d ]) 0)) 1060 {*aarch64_simd_movv2di}
     (nil))

which IRA converted to:

(insn 74 72 580 8 (set (reg:V2DI 287 [ _166 ])
        (subreg:V2DI (reg/v/f:DI 517 [orig:112 d ] [112]) 0)) 1060 {*aarch64_simd_movv2di}
     (nil))

after creating loop allocnos.  It happens that the ALLOCNO_WMODEs for
both 112 and 517 were not set to V2DI due to another bug that I'll post
a separate patch for, but we nevertheless got a valid allocation of
register 1.

LRA's first try at constraining the instruction gave:

         Choosing alt 5 in insn 74:  (0) ?w  (1) r {*aarch64_simd_movv2di}

at which point all was good.  But LRA later decided it needed
to spill r517:

    Spill r517 after risky transformations

so the next constraint attempt gave:

         Choosing alt 0 in insn 74:  (0) =w  (1) m {*aarch64_simd_movv2di}

which was still good.  Then during inheritance we had:

      Creating newreg=672 from oldreg=517, assigning class GENERAL_REGS to inheritance r672
    Original reg change 517->672 (bb8):
   74: r287:V2DI=r672:DI#0
    Add inheritance<-original before:
  939: r672:DI=r517:DI

    Inheritance reuse change 517->672 (bb8):
  620: r572:DI=r672:DI
      REG_DEAD r672:DI

    Use smallest class of POINTER_REGS and GENERAL_REGS
      Creating newreg=673 from oldreg=517, assigning class POINTER_REGS to inheritance r673
    Original reg change 517->673 (bb8):
  936: r669:DI=r673:DI
    Add inheritance<-original before:
  940: r673:DI=r517:DI

("Use smallest class of POINTER_REGS and GENERAL_REGS" ought to
give GENERAL_REGS.  That might be a missed optimisation, and probably
due to both classes having the same number of allocatable registers.
I'll look at that as a follow-on.)

Thus LRA created two inheritance registers for r517, one (r673)
that included the unallocatable x31 and another (r672) that didn't.
The r672 references included the paradoxical subreg in insn 74 but the
r673 ones didn't.  LRA then allocated x30 to r673, which was a valid
choice.

Later LRA decided to "undo" the inheritance for insn 620, but because
of the double inheritance, it got confused as to what the original
situation was, and made insn 74 use the other inheritance register
instead of r517:

********** Undoing inheritance #2: **********

Inherit 11 out of 12 (91.67%)
   Insn after restoring regs:
  620: r572:DI=r517:DI
      REG_DEAD r517:DI
    Change reload insn:
   74: r287:V2DI=r673:DI#0       <-------------------
   Insn after restoring regs:
  939: r517:DI=r673:DI
      REG_DEAD r673:DI

This might be a bug in itself: we should probably look through sets
of other inheritance pseudos to find the "real" origin.

Either way, at this point we had a situation in which r673 was used in an
insn whose subreg was larger than the biggest_mode that r673 had when it
was allocated.  While x30 was valid for the original biggest_mode, it
wasn't valid for this subreg use.

The next attempt to constrain insn 74 was:

        Choosing alt 5 in insn 74:  (0) ?w  (1) r {*aarch64_simd_movv2di}
      Creating newreg=684, assigning class GENERAL_REGS to r684
   74: r287:V2DI=r684:V2DI
    Inserting insn reload before:
  951: r684:V2DI=r673:DI#0

where LRA reloaded the SUBREG rather than the SUBREG_REG.  And it
then cycled trying the same thing when reloading the reload (and the
reload of the reload, etc.).

What it should be doing here is reloading the SUBREG_REG instead.
There's already code to cope with this case when the paradoxical
subreg falls outside the class (which isn't true here, since r673
is POINTER_REGS and POINTER_REGS includes x31).  But I think we
should also test whether LRA is entitled to allocate the spanned
registers.  Not doing that seems like a bug regardless of the above
missed optimisation and the mix-up undoing inheritance.

2018-05-30  Richard Sandiford  <richard.sandiford@linaro.org>

gcc/
	* lra-constraints.c (simplify_operand_subreg): In the paradoxical
	case, check whether the outer register overlaps an unallocatable
	register, not just whether it fits the required class.

gcc/testsuite/
	* g++.dg/torture/aarch64-vect-init-1.C: New test.

From-SVN: r261531

This patch generalises various places that used hwi rtx accessors so
that they can handle poly_ints instead.  In many cases these changes
are by inspection rather than because something had shown them to be
necessary.

2018-06-12  Richard Sandiford  <richard.sandiford@linaro.org>

gcc/
	* poly-int.h (can_div_trunc_p): Add new overload in which all values
	are poly_ints.
	* alias.c (get_addr): Extend CONST_INT handling to poly_int_rtx_p.
	(memrefs_conflict_p): Likewise.
	(init_alias_analysis): Likewise.
	* cfgexpand.c (expand_debug_expr): Likewise.
	* combine.c (combine_simplify_rtx, force_int_to_mode): Likewise.
	* cse.c (fold_rtx): Likewise.
	* explow.c (adjust_stack, anti_adjust_stack): Likewise.
	* expr.c (emit_block_move_hints): Likewise.
	(clear_storage_hints, push_block, emit_push_insn): Likewise.
	(store_expr_with_bounds, reduce_to_bit_field_precision): Likewise.
	(emit_group_load_1): Use rtx_to_poly_int64 for group offsets.
	(emit_group_store): Likewise.
	(find_args_size_adjust): Use strip_offset.  Use rtx_to_poly_int64
	to read the PRE/POST_MODIFY increment.
	* calls.c (store_one_arg): Use strip_offset.
	* rtlanal.c (rtx_addr_can_trap_p_1): Extend CONST_INT handling to
	poly_int_rtx_p.
	(set_noop_p): Use rtx_to_poly_int64 for the elements selected
	by a VEC_SELECT.
	* simplify-rtx.c (avoid_constant_pool_reference): Use strip_offset.
	(simplify_binary_operation_1): Extend CONST_INT handling to
	poly_int_rtx_p.
	* var-tracking.c (compute_cfa_pointer): Take a poly_int64 rather
	than a HOST_WIDE_INT.
	(hard_frame_pointer_adjustment): Change from HOST_WIDE_INT to
	poly_int64.
	(adjust_mems, add_stores): Update accodingly.
	(vt_canonicalize_addr): Track polynomial offsets.
	(emit_note_insn_var_location): Likewise.
	(vt_add_function_parameter): Likewise.
	(vt_initialize): Likewise.

From-SVN: r261530

	* config.gcc (alpha*-*-freebsd*): Remove.
	* config/alpha/freebsd.h: Remove.

contrib/

	* config-list.mk (LIST): Remove alpha-freebsd6.

From-SVN: r261529

/cp
2018-06-12  Paolo Carlini  <paolo.carlini@oracle.com>

	* decl2.c (coerce_new_type, coerce_delete_type): Add location_t
	parameter and adjust error_at calls.
	* decl.c (grok_op_properties): Adjust calls.
	* cp-tree.h (oerce_new_type, coerce_delete_type): Adjust decls.

/testsuite
2018-06-12  Paolo Carlini  <paolo.carlini@oracle.com>

	* g++.dg/init/delete3.C: New.
	* g++.dg/init/new49.C: Likewise.
	* g++.dg/init/new25.C: Test locations too.
	* g++.dg/template/new4.C: Likewise.
	* g++.old-deja/g++.jason/operator.C: Likewise.

From-SVN: r261528

/cp
2018-06-12  Paolo Carlini  <paolo.carlini@oracle.com>

	* decl2.c (coerce_new_type, coerce_delete_type): Add location_t
	parameter and adjust error_at calls.
	* decl.c (grok_op_properties): Adjust calls.
	* cp-tree.h (oerce_new_type, coerce_delete_type): Adjust decls.

/testsuite
2018-06-12  Paolo Carlini  <paolo.carlini@oracle.com>

	* g++.dg/init/delete3.C: New.
	* g++.dg/init/new49.C: Likewise.
	* g++.dg/init/new25.C: Test locations too.
	* g++.dg/template/new4.C: Likewise.
	* g++.old-deja/g++.jason/operator.C: Likewise.

From-SVN: r261527

	Core issue 1331 - const mismatch with defaulted copy constructor
	* class.c (check_bases_and_members): When checking a defaulted
	function, mark it as deleted rather than giving an error.

	* g++.dg/cpp0x/defaulted15.C (struct F): Remove dg-error.
	* g++.dg/cpp0x/defaulted52.C: New test.
	* g++.dg/cpp0x/defaulted53.C: New test.
	* g++.dg/cpp0x/defaulted54.C: New test.
	* g++.dg/cpp0x/defaulted55.C: New test.
	* g++.dg/cpp0x/defaulted56.C: New test.
	* g++.dg/cpp0x/defaulted57.C: New test.
	* g++.dg/cpp0x/defaulted58.C: New test.
	* g++.dg/cpp0x/defaulted59.C: New test.
	* g++.dg/cpp0x/defaulted60.C: New test.

From-SVN: r261526

2018-06-12  François Dumont  <fdumont@gcc.gnu.org>

	* include/debug/macros.h (__glibcxx_check_can_increment_range): New.
	(__glibcxx_check_can_decrement_range): New.
	* include/debug/debug.h (__glibcxx_requires_can_increment_range): New.
	(__glibcxx_requires_can_decrement_range): New.
	* include/bits/stl_algobase.h (std::copy(_II, _II, _OI)): Use
	__glibcxx_requires_can_increment_range.
	(std::move(_II, _II, _OI)): Likewise.
	(std::copy_backward(_BI, _BI, _BI2)): Use
	__glibcxx_requires_can_decrement_range.
	(std::move_backward(_BI, _BI, _BI2)): Likewise.
	* testsuite/25_algorithms/copy_backward/debug/1_neg.cc: New.
	* testsuite/25_algorithms/copy_backward/debug/2_neg.cc: New.
	* testsuite/25_algorithms/copy_backward/debug/3_neg.cc: New.
	* testsuite/25_algorithms/equal/debug/1_neg.cc: New.
	* testsuite/25_algorithms/equal/debug/2_neg.cc: New.
	* testsuite/25_algorithms/equal/debug/3_neg.cc: New.

From-SVN: r261525

Explicit default constructors are problematic, so this change removes
them from <random> and <ext/random>, as per P0935R0.

	* include/bits/random.h (linear_congruential_engine)
	(mersenne_twister_engine, subtract_with_carry_engine, random_device)
	(uniform_real_distribution, normal_distribution)
	(lognormal_distribution, gamma_distribution, chi_squared_distribution)
	(cauchy_distribution, fisher_f_distribution, student_t_distribution)
	(bernoulli_distribution, binomial_distribution,geometric_distribution)
	(negative_binomial_distribution, exponential_distribution)
	(weibull_distribution, extreme_value_distribution): Add non-explicit
	default constructors. Remove default argument for first parameter of
	explicit constructors.
	(piecewise_constant_distribution, piecewise_linear_distribution):
	Make default constructor non-explicit.
	* include/bits/uniform_int_dist.h (uniform_int_distribution): Add
	non-explicit default constructors. Remove default argument for first
	parameter of explicit constructor.
	(simd_fast_mersenne_twister_engine, beta_distribution)
	(rice_distribution, nakagami_distribution, pareto_distribution)
	(k_distribution, arcsine_distribution, hoyt_distribution)
	(triangular_distribution, von_mises_distribution)
	(hypergeometric_distribution, logistic_distribution)
	(uniform_inside_sphere_distribution): Likewise.
	(uniform_on_sphere_distribution): Make default constructor
	non-explicit.
	* testsuite/26_numerics/random/bernoulli_distribution/cons/default.cc:
	Test for non-explicit default constructor. Fix references to standard.
	* testsuite/26_numerics/random/binomial_distribution/cons/default.cc:
	Likewise.
	* testsuite/26_numerics/random/cauchy_distribution/cons/default.cc:
	Likewise.
	* testsuite/26_numerics/random/chi_squared_distribution/cons/default.cc:
	Likewise.
	* testsuite/26_numerics/random/discrete_distribution/cons/default.cc:
	Likewise.
	* testsuite/26_numerics/random/exponential_distribution/cons/default.cc:
	Likewise.
	* testsuite/26_numerics/random/extreme_value_distribution/cons/default.cc:
	Likewise.
	* testsuite/26_numerics/random/fisher_f_distribution/cons/default.cc:
	Likewise.
	* testsuite/26_numerics/random/gamma_distribution/cons/default.cc:
	Likewise.
	* testsuite/26_numerics/random/geometric_distribution/cons/default.cc:
	Likewise.
	* testsuite/26_numerics/random/lognormal_distribution/cons/default.cc:
	Likewise.
	* testsuite/26_numerics/random/negative_binomial_distribution/cons/default.cc:
	Likewise.
	* testsuite/26_numerics/random/normal_distribution/cons/default.cc:
	Likewise.
	* testsuite/26_numerics/random/piecewise_constant_distribution/cons/default.cc:
	Likewise.
	* testsuite/26_numerics/random/piecewise_linear_distribution/cons/default.cc:
	Likewise.
	* testsuite/26_numerics/random/poisson_distribution/cons/default.cc:
	Likewise.
	* testsuite/26_numerics/random/student_t_distribution/cons/default.cc:
	Likewise.
	* testsuite/26_numerics/random/uniform_int_distribution/cons/default.cc:
	Likewise.
	* testsuite/26_numerics/random/uniform_real_distribution/cons/default.cc:
	Likewise.
	* testsuite/26_numerics/random/weibull_distribution/cons/default.cc:
	Likewise.
	* testsuite/ext/random/arcsine_distribution/cons/default.cc: Likewise.
	* testsuite/ext/random/beta_distribution/cons/default.cc: Likewise.
	* testsuite/ext/random/hoyt_distribution/cons/default.cc: Likewise.
	* testsuite/ext/random/hypergeometric_distribution/cons/default.cc:
	Likewise.
	* testsuite/ext/random/k_distribution/cons/default.cc: Likewise.
	* testsuite/ext/random/logistic_distribution/cons/default.cc: Likewise.
	* testsuite/ext/random/nakagami_distribution/cons/default.cc: Likewise.
	* testsuite/ext/random/normal_mv_distribution/cons/default.cc:
	Likewise.
	* testsuite/ext/random/pareto_distribution/cons/default.cc: Likewise.
	* testsuite/ext/random/rice_distribution/cons/default.cc: Likewise.
	* testsuite/ext/random/triangular_distribution/cons/default.cc:
	Likewise.
	* testsuite/ext/random/uniform_inside_sphere_distribution/cons/default.cc:
	Likewise.
	* testsuite/ext/random/uniform_on_sphere_distribution/cons/default.cc:
	Likewise.
	* testsuite/ext/random/von_mises_distribution/cons/default.cc:
	Likewise.
	* testsuite/util/testsuite_common_types.h
	(implicitly_default_constructible): New helper.

From-SVN: r261522

gcc/fortran/ChangeLog:
	PR other/69968
	* misc.c (gfc_closest_fuzzy_match): Update for renaming of
	levenshtein_distance to get_edit_distance.

gcc/ChangeLog:
	PR other/69968
	* spellcheck-tree.c (levenshtein_distance): Rename to...
	(get_edit_distance): ...this, and update for underlying renaming.
	* spellcheck-tree.h (levenshtein_distance): Rename to...
	(get_edit_distance): ...this.
	* spellcheck.c (levenshtein_distance): Rename to...
	(get_edit_distance): ...this.  Convert from Levenshtein distance
	to Damerau-Levenshtein distance by supporting transpositions of
	adjacent characters.  Rename "v1" to "v_next" and "v0" to
	"v_one_ago".
	(selftest::levenshtein_distance_unit_test_oneway): Rename to...
	(selftest::test_edit_distance_unit_test_oneway): ...this, and
	update for underlying renaming.
	(selftest::levenshtein_distance_unit_test): Rename to...
	(selftest::test_get_edit_distance_unit): ...this, and update for
	underlying renaming.
	(selftest::test_find_closest_string): Add example from PR 69968
	where transposition helps
	(selftest::test_metric_conditions): Update for renaming.
	(selftest::test_metric_conditions): Likewise.
	(selftest::spellcheck_c_tests): Likewise.
	* spellcheck.h (levenshtein_distance): Rename both overloads to...
	(get_edit_distance): ...this.
	(best_match::consider): Update for renaming.

gcc/testsuite/ChangeLog:
	PR other/69968
	* gcc.dg/spellcheck-transposition.c: New test.

From-SVN: r261521

gcc/ChangeLog:

	PR tree-optimization/85259
	* builtins.c (compute_objsize): Handle constant offsets.
	* gimple-ssa-warn-restrict.c (maybe_diag_offset_bounds): Return
	true iff a warning has been issued.
	* gimple.h (gimple_nonartificial_location): New function.
	* tree-ssa-strlen.c (maybe_diag_stxncpy_trunc): Call
	gimple_nonartificial_location and handle -Wno-system-headers.
	(handle_builtin_stxncpy): Same.

gcc/testsuite/ChangeLog:

	PR tree-optimization/85259
	* gcc.dg/Wstringop-overflow-5.c: New test.
	* gcc.dg/Wstringop-overflow-6.c: New test.

From-SVN: r261518

2018-06-12  Steven G. Kargl  <kargl@gcc.gnu.org>

	PR fortran/44491
	* expr.c (gfc_check_assign): Select non-NULL locus.

2018-06-12  Steven G. Kargl  <kargl@gcc.gnu.org>

	PR fortran/44491
	* gfortran.dg/pr44491.f90: New testcase

From-SVN: r261516

gcc/c-family/ChangeLog:

	PR c/85931
	* c-warn.c (sizeof_pointer_memaccess_warning): Avoid warning when
	sizeof source and destination yields the same value.

gcc/ChangeLog:

	PR c/85931
	* fold-const.c (operand_equal_p): Handle SAVE_EXPR.

gcc/testsuite/ChangeLog:

	PR c/85931
	* gcc.dg/Wstringop-truncation-3.c: New test.

From-SVN: r261515

[testsuite]

2018-05-31  Will Schmidt  <will_schmidt@vnet.ibm.com>

	* gcc.target/powerpc/p8-vec-xl-xst-v2.c: New.(actually added this time).

From-SVN: r261510

[testsuite]

2018-05-31  Will Schmidt  <will_schmidt@vnet.ibm.com>

	* gcc.target/powerpc/p8-vec-xl-xst-v2.c: New.
	* gcc.target/powerpc/p8-vec-xl-xst.c: Disable gimple-folding.
	* gcc.target/powerpc/swaps-p8-17.c: Same.

From-SVN: r261509

[testsuite]

2018-05-31  Will Schmidt  <will_schmidt@vnet.ibm.com>

	* gcc.target/powerpc/fold-vec-store-vec_vsx_st-char.c: New.
	* gcc.target/powerpc/fold-vec-store-vec_vsx_st-double.c: New.
	* gcc.target/powerpc/fold-vec-store-vec_vsx_st-float.c: New.
	* gcc.target/powerpc/fold-vec-store-vec_vsx_st-int.c: New.
	* gcc.target/powerpc/fold-vec-store-vec_vsx_st-longlong.c: New.
	* gcc.target/powerpc/fold-vec-store-vec_vsx_st-short.c: New.

From-SVN: r261508

[testsuite]

2018-05-31  Will Schmidt  <will_schmidt@vnet.ibm.com>

	* gcc.target/powerpc/fold-vec-store-builtin_vec_xst-char.c: New.
	* gcc.target/powerpc/fold-vec-store-builtin_vec_xst-double.c: New.
	* gcc.target/powerpc/fold-vec-store-builtin_vec_xst-float.c: New.
	* gcc.target/powerpc/fold-vec-store-builtin_vec_xst-int.c: New.
	* gcc.target/powerpc/fold-vec-store-builtin_vec_xst-longlong.c: New.
	* gcc.target/powerpc/fold-vec-store-builtin_vec_xst-short.c: New.

From-SVN: r261507

[testsuite]

    2018-05-31  Will Schmidt  <will_schmidt@vnet.ibm.com>

	* gcc.target/powerpc/fold-vec-store-vec_xst-char.c: New.
	* gcc.target/powerpc/fold-vec-store-vec_xst-double.c: New.
	* gcc.target/powerpc/fold-vec-store-vec_xst-float.c: New.
	* gcc.target/powerpc/fold-vec-store-vec_xst-int.c: New.
	* gcc.target/powerpc/fold-vec-store-vec_xst-longlong.c: New.
	* gcc.target/powerpc/fold-vec-store-vec_xst-short.c: New.

From-SVN: r261506

[testsuite]

2018-05-31  Will Schmidt  <will_schmidt@vnet.ibm.com>

	* gcc.target/powerpc/fold-vec-load-vec_vsx_ld-char.c: New.
	* gcc.target/powerpc/fold-vec-load-vec_vsx_ld-double.c: New.
	* gcc.target/powerpc/fold-vec-load-vec_vsx_ld-float.c: New.
	* gcc.target/powerpc/fold-vec-load-vec_vsx_ld-int.c: New.
	* gcc.target/powerpc/fold-vec-load-vec_vsx_ld-longlong.c: New.
	* gcc.target/powerpc/fold-vec-load-vec_vsx_ld-short.c: New.

From-SVN: r261505

[testsuite]

2018-05-31  Will Schmidt  <will_schmidt@vnet.ibm.com>

	* gcc.target/powerpc/fold-vec-load-builtin_vec_xl-char.c: New.
	* gcc.target/powerpc/fold-vec-load-builtin_vec_xl-double.c: New.
	* gcc.target/powerpc/fold-vec-load-builtin_vec_xl-float.c: New.
	* gcc.target/powerpc/fold-vec-load-builtin_vec_xl-int.c: New.
	* gcc.target/powerpc/fold-vec-load-builtin_vec_xl-longlong.c: New.
	* gcc.target/powerpc/fold-vec-load-builtin_vec_xl-short.c: New.

From-SVN: r261504

[testsuite]

2018-06-12  Will Schmidt  <will_schmidt@vnet.ibm.com>

	* gcc.target/powerpc/fold-vec-load-vec_xl-char.c: New testcase.
	* gcc.target/powerpc/fold-vec-load-vec_xl-double.c: New testcase.
	* gcc.target/powerpc/fold-vec-load-vec_xl-float.c: New testcase.
	* gcc.target/powerpc/fold-vec-load-vec_xl-int.c: New testcase.
	* gcc.target/powerpc/fold-vec-load-vec_xl-longlong.c: New testcase.
	* gcc.target/powerpc/fold-vec-load-vec_xl-short.c: New testcase.

From-SVN: r261503

rs6000-c.c (altivec_overloaded_builtins): Add BUILTIN_VEC_XST entries for pointer to double and long long.


[gcc]

2018-06-12  Will Schmidt  <will_schmidt@vnet.ibm.com>

	* config/rs6000/rs6000-c.c (altivec_overloaded_builtins): Add
	BUILTIN_VEC_XST entries for pointer to double and long long.

From-SVN: r261502

Glibc 2.18 was changed by

commit ecbf434213c0333d81706074e4d107ac45011635
Author: Andreas Jaeger <aj@suse.de>
Date:   Wed May 15 20:20:54 2013 +0200

    Reserve new TLS field for x86 and x86_64

        [BZ #10686]
        * sysdeps/x86_64/tls.h (struct tcbhead_t): Add __private_ss
        field.
        * sysdeps/i386/tls.h (struct tcbhead_t): Likewise.

to reduce the size of __private_tm to make room for __private_ss, which
was supposed to be used for TARGET_THREAD_SPLIT_STACK_OFFSET:

typedef struct
{
  void *tcb;            /* Pointer to the TCB.  Not necessarily the
                           thread descriptor used by libpthread.  */
  dtv_t *dtv;
  void *self;           /* Pointer to the thread descriptor.  */
  int multiple_threads;
  uintptr_t sysinfo;
  uintptr_t stack_guard;
  uintptr_t pointer_guard;
  int gscope_flag;
  int __glibc_reserved1;
  /* Reservation of some values for the TM ABI.  */
  void *__private_tm[4];
  /* GCC split stack support.  */
  void *__private_ss;
} tcbhead_t;

But the offset of __private_ss for i386 was mistakenly set to 0x30,
instead of 0x34 and libgcc/config/i386/morestack.S has:

	cmpl	%gs:0x30,%eax		# See if we have enough space.
	movl	%eax,%gs:0x30		# Save the new stack boundary.
	movl	%eax,%gs:0x30		# Save the new stack boundary.
	movl	%ecx,%gs:0x30		# Save new stack boundary.
	movl	%eax,%gs:0x30
	movl	%gs:0x30,%eax
	movl	%eax,%gs:0x30

Since update TARGET_THREAD_SPLIT_STACK_OFFSET changes split stack ABI,
glibc 2.28 has been changed by

commit 0221ce2a90be2d40fc90f0b5dcec77a1ec013f53
Author: H.J. Lu <hjl.tools@gmail.com>
Date:   Tue Jun 12 06:23:28 2018 -0700

    i386: Change offset of __private_ss to 0x30 [BZ #23250]

to match GCC:

typedef struct
{
  void *tcb;		/* Pointer to the TCB.  Not necessarily the
			   thread descriptor used by libpthread.  */
  dtv_t *dtv;
  void *self;		/* Pointer to the thread descriptor.  */
  int multiple_threads;
  uintptr_t sysinfo;
  uintptr_t stack_guard;
  uintptr_t pointer_guard;
  int gscope_flag;
  int __glibc_reserved1;
  /* Reservation of some values for the TM ABI.  */
  void *__private_tm[3];
  /* GCC split stack support.  */
  void *__private_ss;
  void *__glibc_reserved2;
} tcbhead_t;

	PR target/85990
	* config/i386/gnu-user.h (TARGET_THREAD_SPLIT_STACK_OFFSET):
	Update comments.
	* config/i386/gnu-user64.h (TARGET_THREAD_SPLIT_STACK_OFFSET):
	Likewise.

From-SVN: r261501

	* genfixes: exit 1 when autogen not found.
	* genfixes: Remove some redundant code.
	* genfixes: Update URL to autogen source code.

From-SVN: r261500

	* inclhack.def: Fix fixup for assert.h on vxworks.
	* fixincl.x: Regenerate.

From-SVN: r261499

2018-06-12  Martin Liska  <mliska@suse.cz>

	* doc/options.texi: Document IntegerRange.

From-SVN: r261498

2018-06-12  Martin Liska  <mliska@suse.cz>

	* doc/options.texi: Document Deprecated option flag.
2018-06-12  Martin Liska  <mliska@suse.cz>

	* config/i386/i386.opt: Make MPX-related options as Deprecated.
	* opt-functions.awk: Handle Deprecated flag.
	* opts-common.c (decode_cmdline_option): Handle cl_deprecated
        and report error.
	(read_cmdline_option): Report warning for a deprecated option.
	* opts.h (struct cl_option): Add new field cl_deprecated.
	(CL_ERR_DEPRECATED): New.
2018-06-12  Martin Liska  <mliska@suse.cz>

	* c.opt: Make MPX-related options as Deprecated.
2018-06-12  Martin Liska  <mliska@suse.cz>

	* g++.dg/opt/mpx.C: New test.
	* gcc.target/i386/mpx.c: New test.

From-SVN: r261497

QuarkSE has lp_count width set to 16 bits. Update the compiler to
consider it.

gcc/
2018-06-12  Claudiu Zissulescu  <claziss@synopsys.com>

	* config/arc/arc-arch.h (arc_extras): New enum.
	(arc_cpu_t):Add field extra.
	(arc_cpu_types): Consider the extras.
	* config/arc/arc-cpus.def: Add extras info.
	* config/arc/arc-opts.h (processor_type): Consider extra field.
	* config/arc/arc.c (arc_override_options): Handle extra field.

From-SVN: r261496

When we pass an mcpu to the compiler we have two types of (hardware
configuration) flags that are set:

1. Architecture specific, for example code-density is always enabled
for ARCHS architectures. These options are overwriting whatever the
corresponding user options with the preset ones.

2. CPU specific, for example archs is using LL64 option by
default. These options can be freely enabled or disabled.

Because of the above complexity, we need to throw some errors for the
user to know when he/she does something which goes against the above
rules. Thus, I came up with the following set of rules:

1. Overwriting default architecture specific hardware option: it is
ignored, a warning is thrown;

2. Overwriting default CPU specific hardware option: it is taken into
account, a warning is thrown.

gcc/
2018-06-12  Claudiu Zissulescu  <claziss@synopsys.com>

	* config/arc/arc-arch.h: Update ARC_OPTX macro.
	* config/arc/arc-options.def (ARC_OPTX): Introduce a new doc
	field.
	* config/arc/arc.c (arc_init): Update pic warning.
	(irq_range): Update irq range parsing warnings.
	(arc_override_options): Update various warning messages.
	(arc_handle_aux_attribute): Likewise.

gcc/testsuite
2018-06-12  Claudiu Zissulescu  <claziss@synopsys.com>

	* gcc.target/arc/builtin_simdarc.c: Update test.
	* gcc.target/arc/mulsi3_highpart-2.c: Likewise.
	* gcc.target/arc/tumaddsidi4.c: Likewise.

From-SVN: r261495

gcc/
	* config/mips/i6400.md (i6400_fpu_fadd): Remove frint.

From-SVN: r261494

	* doc/sourcebuild.texi: Document usage of line number 0 in verify
	compiler messages directives.

From-SVN: r261493