From-SVN: r279973

From-SVN: r279972

From-SVN: r279971

	* include/bits/stl_tree.h
	(_Rb_tree<>::_M_move_assign(_Rb_tree&, false_type)): Replace
	std::move_if_noexcept by std::move.
	* testsuite/23_containers/map/92124.cc: New.
	* testsuite/23_containers/set/92124.cc: New.

From-SVN: r279967

/gcc/cp
2020-01-07  Paolo Carlini  <paolo.carlini@oracle.com>

	* init.c (build_new): Add location_t parameter and use it throughout.
	(build_raw_new_expr): Likewise.
	* parser.c (cp_parser_new_expression): Pass the combined_loc.
	* pt.c (tsubst_copy_and_build): Adjust call.
	* cp-tree.h: Update declarations.

/libcc1
2020-01-07  Paolo Carlini  <paolo.carlini@oracle.com>

	* libcp1plugin.cc (plugin_build_new_expr): Update build_new call.

/gcc/testsuite
2020-01-07  Paolo Carlini  <paolo.carlini@oracle.com>

	* g++.old-deja/g++.bugs/900208_03.C: Check locations too.
	* g++.old-deja/g++.bugs/900519_06.C: Likewise.

From-SVN: r279963

    
    This avoids generating a write barrier for code that appears in the
    Go1.14beta1 runtime package in (*pageAlloc).sysGrow:
        s.summary[l] = s.summary[l][:needIdxLimit]
    
    Reviewed-on: https://go-review.googlesource.com/c/gofrontend/+/213558

From-SVN: r279962

2020-01-07  Andrew Stubbs  <ams@codesourcery.com>

	gcc/
	* config/gcn/gcn-valu.md (VEC_1REG_INT_ALT): Delete iterator.
	(VEC_ALLREG_ALT): New iterator.
	(VEC_ALLREG_INT_MODE): New iterator.
	(VCMP_MODE): New iterator.
	(VCMP_MODE_INT): New iterator.
	(vec_cmpu<mode>di): Use VCMP_MODE_INT.
	(vec_cmp<u>v64qidi): New define_expand.
	(vec_cmp<mode>di_exec): Use VCMP_MODE.
	(vec_cmpu<mode>di_exec): New define_expand.
	(vec_cmp<u>v64qidi_exec): New define_expand.
	(vec_cmp<mode>di_dup): Use VCMP_MODE.
	(vec_cmp<mode>di_dup_exec): Use VCMP_MODE.
	(vcond<VEC_ALL1REG_MODE:mode><VEC_1REG_ALT:mode>): Rename ...
	(vcond<VEC_ALLREG_MODE:mode><VEC_ALLREG_ALT:mode>): ... to this.
	(vcond<VEC_ALL1REG_MODE:mode><VEC_1REG_ALT:mode>_exec): Rename ...
	(vcond<VEC_ALLREG_MODE:mode><VEC_ALLREG_ALT:mode>_exec): ... to this.
	(vcondu<VEC_ALL1REG_MODE:mode><VEC_1REG_INT_ALT:mode>): Rename ...
	(vcondu<VEC_ALLREG_MODE:mode><VEC_ALLREG_INT_MODE:mode>): ... to this.
	(vcondu<VEC_ALL1REG_MODE:mode><VEC_1REG_INT_ALT:mode>_exec): Rename ...
	(vcondu<VEC_ALLREG_MODE:mode><VEC_ALLREG_INT_MODE:mode>_exec): ... to
	this.
	* config/gcn/gcn.c (print_operand): Fix 8 and 16 bit suffixes.
	* config/gcn/gcn.md (expander): Add sign_extend and zero_extend.

From-SVN: r279961

DECL_VISIBILITY_SPECIFIED is also true if an enclosing scope has explicit
visibility, and we don't want that to override -fvisibility-inlines-hidden.
So check for the attribute specifically on the function, like we already do
for template argument visibility restriction.

	* decl2.c (determine_visibility): -fvisibility-inlines-hidden beats
	explicit class visibility for a template.

From-SVN: r279960

2020-01-07  Andrew Stubbs  <ams@codesourcery.com>

	gcc/
	* config/gcn/constraints.md (DA): Update description and match.
	(DB): Likewise.
	(Db): New constraint.
	* config/gcn/gcn-protos.h (gcn_inline_constant64_p): Add second
	parameter.
	* config/gcn/gcn.c (gcn_inline_constant64_p): Add 'mixed' parameter.
	Implement 'Db' mixed immediate type.
	* config/gcn/gcn-valu.md (addcv64si3<exec_vcc>): Rework constraints.
	(addcv64si3_dup<exec_vcc>): Delete.
	(subcv64si3<exec_vcc>): Rework constraints.
	(addv64di3): Rework constraints.
	(addv64di3_exec): Rework constraints.
	(subv64di3): Rework constraints.
	(addv64di3_dup): Delete.
	(addv64di3_dup_exec): Delete.
	(addv64di3_zext): Rework constraints.
	(addv64di3_zext_exec): Rework constraints.
	(addv64di3_zext_dup): Rework constraints.
	(addv64di3_zext_dup_exec): Rework constraints.
	(addv64di3_zext_dup2): Rework constraints.
	(addv64di3_zext_dup2_exec): Rework constraints.
	(addv64di3_sext_dup2): Rework constraints.
	(addv64di3_sext_dup2_exec): Rework constraints.

From-SVN: r279959

gcc/testsuite/ChangeLog:
2020-01-07  Andre Vieira  <andre.simoesdiasvieira@arm.com>

	* gcc.dg/vect/vect-epilogues.c: XFAIL for arm big endian.

From-SVN: r279958

gcc/ChangeLog:
2020-01-07  Andre Vieira  <andre.simoesdiasvieira@arm.com>

	* doc/sourcebuild.texi (arm_little_endian, arm_nothumb): Documented
	existing target checks.

From-SVN: r279957

    
    These came up while building 1.14beta1 while the code was still invalid.
    The policy is to not bother committing invalid test cases that cause
    compiler crashes.
    
    Reviewed-on: https://go-review.googlesource.com/c/gofrontend/+/213537

From-SVN: r279956

2020-01-07  Richard Biener  <rguenther@suse.de>

	* doc/install.texi: Bump minimal supported MPC version.

From-SVN: r279955

Normally we only create SVE ACLE functions when arm_sve.h is included.
But for LTO we need to do it at start-up, so that the functions are
already defined when streaming in the LTO objects.

One hitch with doing that is that LTO doesn't yet implement the
simulate_enum_decl langhook.  This patch adds a simple default
implementation that it can use.

2020-01-07  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
	* langhooks-def.h (lhd_simulate_enum_decl): Declare.
	(LANG_HOOKS_SIMULATE_ENUM_DECL): Use it.
	* langhooks.c: Include stor-layout.h.
	(lhd_simulate_enum_decl): New function.
	* config/aarch64/aarch64-sve-builtins.cc (init_builtins): Call
	handle_arm_sve_h for the LTO frontend.
	(register_vector_type): Cope with null returns from pushdecl.

gcc/testsuite/
	* gcc.target/aarch64/sve/pcs/asm_4.c: New test.

From-SVN: r279954

The SVE port needs to maintain a different type identity for
GNU vectors and "SVE vectors", since the types use different ABIs.
Until now we've done that using pointer equality between the
TYPE_MAIN_VARIANT and the built-in SVE type.

However, as Richard B noted, that doesn't work well for LTO,
where we stream both GNU and SVE types from a file instead of
creating them directly.  We need a mechanism for distinguishing
the types using streamed type information.

This patch does that using a new type attribute.  This attribute
is only meant to be used for the built-in SVE types and shouldn't
be user-visible.  The patch tries to ensure this by including a space
in the attribute name, like we already do for things like "fn spec"
and "omp declare simd".

2020-01-07  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
	* config/aarch64/aarch64-protos.h (aarch64_sve::svbool_type_p)
	(aarch64_sve::nvectors_if_data_type): Replace with...
	(aarch64_sve::builtin_type_p): ...this.
	* config/aarch64/aarch64-sve-builtins.cc: Include attribs.h.
	(find_vector_type): Delete.
	(add_sve_type_attribute): New function.
	(lookup_sve_type_attribute): Likewise.
	(register_builtin_types): Add an "SVE type" attribute to each type.
	(register_tuple_type): Likewise.
	(svbool_type_p, nvectors_if_data_type): Delete.
	(mangle_builtin_type): Use lookup_sve_type_attribute.
	(builtin_type_p): Likewise.  Add an overload that returns the
	number of constituent vector and predicate registers.
	* config/aarch64/aarch64.c (aarch64_sve_argument_p): Delete.
	(aarch64_returns_value_in_sve_regs_p): Use aarch64_sve::builtin_type_p
	instead of aarch64_sve_argument_p.
	(aarch64_takes_arguments_in_sve_regs_p): Likewise.
	(aarch64_pass_by_reference): Likewise.
	(aarch64_function_value_1): Likewise.
	(aarch64_return_in_memory): Likewise.
	(aarch64_layout_arg): Likewise.

gcc/testsuite/
	* g++.target/aarch64/sve/acle/general-c++/mangle_5.C: New test.
	* gcc.target/aarch64/sve/pcs/asm_1.c: Likewise.
	* gcc.target/aarch64/sve/pcs/asm_2.c: Likewise.
	* gcc.target/aarch64/sve/pcs/asm_3.c: Likewise.

From-SVN: r279953

The SVE port needs to maintain a different type identity for
GNU vectors and "SVE vectors" even during LTO, since the types
use different ABIs.  The easiest way of doing that seemed to be
to use type attributes.  However, these type attributes shouldn't
be user-facing; they're just a convenient way of representing the
types internally in GCC.

There are already several internal-only attributes, such as "fn spec"
and "omp declare simd".  They're distinguished from normal user-facing
attributes by having a space in their name, which means that it isn't
possible to write them directly in C or C++.

Taking the same approach mostly works well for SVE.  The only snag
I've hit so far is that the new attribute needs to (and only exists to)
affect type identity.  This means that it would normally get included
in mangled names, to distinguish it from types without the attribute.

However, the SVE ABI specifies a separate mangling for SVE vector types,
rather than using an attribute mangling + a normal vector mangling.
So we need some way of suppressing the attribute mangling for this case.

There are currently no other target-independent or target-specific
internal-only attributes that affect type identity, so this patch goes
for the simplest fix of skipping mangling for attributes whose names
contain a space (which usually wouldn't give a valid symbol anyway).
Other options I thought about were:

(1) Also make sure that targetm.mangled_type returns nonnull.

(2) Check directly for the target-specific name.

(3) Add a new target hook.

(4) Add new information to attribute_spec.  This would be very invasive
    at this stage, but maybe we should consider replacing all the boolean
    fields with flags?  That should make the tables slightly easier to
    read and would make adding new flags much simpler in future.

2020-01-07  Richard Sandiford  <richard.sandiford@arm.com>

gcc/cp/
	* mangle.c (mangle_type_attribute_p): New function, split out from...
	(write_CV_qualifiers_for_type): ...here.  Don't mangle attributes
	that contain a space.

From-SVN: r279952

re PR tree-optimization/93156 (abused nonnull attribute evokes new segfault in gcc 10 since Nov 4 commit, 0fb958ab8aa)

	PR tree-optimization/93156
	* tree-ssa-ccp.c (bit_value_binop): For x * x note that the second
	least significant bit is always clear.

	* gcc.dg/tree-ssa/pr93156.c: New test.

From-SVN: r279951

re PR tree-optimization/93118 (>>32<<32 is not always converted into &~0ffffffffull at the tree level)

	PR tree-optimization/93118
	* match.pd ((x >> c) << c -> x & (-1<<c)): Add nop_convert?.  Add new
	simplifier with two intermediate conversions.

	* gcc.dg/tree-ssa/pr93118.c: New test.

From-SVN: r279950

2020-01-07  Martin Liska  <mliska@suse.cz>

	* params.opt: Add Optimization for various parameters.

From-SVN: r279949

2020-01-07  Martin Liska  <mliska@suse.cz>

	PR ipa/83411
	* doc/extend.texi: Explain cloning for target_clone
	attribute.

From-SVN: r279948

2020-01-07  Martin Liska  <mliska@suse.cz>

	PR tree-optimization/92860
	* common.opt: Make in Optimization option
	as it is affected by -O0, which is an Optimization
	option.
	* tree-inline.c (tree_inlinable_function_p):
	Use opt_for_fn for warn_inline.
	(expand_call_inline): Likewise.
2020-01-07  Martin Liska  <mliska@suse.cz>

	PR tree-optimization/92860
	* gcc.dg/pr92860-2.c: New test.

From-SVN: r279947

From-SVN: r279946

2020-01-07  Martin Liska  <mliska@suse.cz>

    PR optimization/92860
    * params.opt: Mark param_min_crossjump_insns with Optimization
    keyword.

From-SVN: r279945

re PR fortran/93162 (gcc/fortran/trans-openmp.c:2469:50: runtime error: load of value 145992800, which is not a valid value for type 'ar_type' since r279628)

	PR fortran/93162
	* trans-openmp.c (gfc_trans_omp_clauses): Check for REF_ARRAY type
	before testing u.ar.type == AR_FULL.

From-SVN: r279944

	PR c++/91369
	* constexpr.c (struct constexpr_global_ctx): Add heap_alloc_count
	member, initialize it to zero in ctor.
	(cxx_eval_call_expression): Bump heap_dealloc_count when deleting
	a heap object.  Don't cache calls to functions which allocate some
	heap objects and don't deallocate them or deallocate some heap
	objects they didn't allocate.

	* g++.dg/cpp1y/constexpr-new.C: Expect an error explaining why
	static_assert failed for C++2a.
	* g++.dg/cpp2a/constexpr-new9.C: New test.

From-SVN: r279943

Inline should return failure either (newsize > param_large_function_insns)
OR (newsize > limit).  Sometimes newsize is larger than
param_large_function_insns, but smaller than limit, inline doesn't return
failure even if the new function is a large function.
Therefore, param_large_function_insns and param_large_function_growth should be
OR instead of AND, otherwise --param large-function-growth won't
work correctly with --param large-function-insns.

gcc/ChangeLog:

	2020-01-07  Luo Xiong Hu  <luoxhu@linux.ibm.com>

	* ipa-inline-analysis.c (estimate_growth): Fix typo.
	* ipa-inline.c (caller_growth_limits): Use OR instead of AND.

From-SVN: r279942

2020-01-06  Michael Meissner  <meissner@linux.ibm.com>

	* config/rs6000/rs6000.c (hard_reg_and_mode_to_addr_mask): New
	helper function to return the valid addressing formats for a given
	hard register and mode.
	(rs6000_adjust_vec_address): Call hard_reg_and_mode_to_addr_mask.

Index: gcc/config/rs6000/rs6000.c
===================================================================
--- gcc/config/rs6000/rs6000.c	(revision 279912)
+++ gcc/config/rs6000/rs6000.c	(working copy)
@@ -6729,6 +6729,30 @@ rs6000_expand_vector_extract (rtx target
     }
 }
 
+/* Helper function to return an address mask based on a physical register.  */
+
+static addr_mask_type
+hard_reg_and_mode_to_addr_mask (rtx reg, machine_mode mode)
+{
+  unsigned int r = reg_or_subregno (reg);
+  addr_mask_type addr_mask;
+
+  gcc_assert (HARD_REGISTER_NUM_P (r));
+  if (INT_REGNO_P (r))
+    addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_GPR];
+
+  else if (FP_REGNO_P (r))
+    addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_FPR];
+
+  else if (ALTIVEC_REGNO_P (r))
+    addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_VMX];
+
+  else
+    gcc_unreachable ();
+
+  return addr_mask;
+}
+
 /* Adjust a memory address (MEM) of a vector type to point to a scalar field
    within the vector (ELEMENT) with a mode (SCALAR_MODE).  Use a base register
    temporary (BASE_TMP) to fixup the address.  Return the new memory address
@@ -6865,21 +6889,8 @@ rs6000_adjust_vec_address (rtx scalar_re
   if (GET_CODE (new_addr) == PLUS)
     {
       rtx op1 = XEXP (new_addr, 1);
-      addr_mask_type addr_mask;
-      unsigned int scalar_regno = reg_or_subregno (scalar_reg);
-
-      gcc_assert (HARD_REGISTER_NUM_P (scalar_regno));
-      if (INT_REGNO_P (scalar_regno))
-	addr_mask = reg_addr[scalar_mode].addr_mask[RELOAD_REG_GPR];
-
-      else if (FP_REGNO_P (scalar_regno))
-	addr_mask = reg_addr[scalar_mode].addr_mask[RELOAD_REG_FPR];
-
-      else if (ALTIVEC_REGNO_P (scalar_regno))
-	addr_mask = reg_addr[scalar_mode].addr_mask[RELOAD_REG_VMX];
-
-      else
-	gcc_unreachable ();
+      addr_mask_type addr_mask
+	= hard_reg_and_mode_to_addr_mask (scalar_reg, scalar_mode);
 
       if (REG_P (op1) || SUBREG_P (op1))
 	valid_addr_p = (addr_mask & RELOAD_REG_INDEXED) != 0;

From-SVN: r279941

From-SVN: r279940

2020-01-06  Michael Meissner  <meissner@linux.ibm.com>

	* config/rs6000/constraints.md (Q constraint): Update
	documentation.
	* doc/md.texi (RS/6000 constraints): Update 'Q' cosntraint
	documentation.

From-SVN: r279939

2020-01-06  Michael Meissner  <meissner@linux.ibm.com>

	* config/rs6000/vsx.md (vsx_extract_<mode>_var, VSX_D iterator):
	Use 'Q' for doing vector extract from memory.
	(vsx_extract_v4sf_var): Use 'Q' for doing vector extract from
	memory.
	(vsx_extract_<mode>_var, VSX_EXTRACT_I iterator): Use 'Q' for
	doing vector extract from memory.
	(vsx_extract_<mode>_<VS_scalar>mode_var): Use 'Q' for doing vector
	extract from memory.

From-SVN: r279938

2020-01-06  Michael Meissner  <meissner@linux.ibm.com>

	* config/rs6000/rs6000.c (rs6000_adjust_vec_address): Add support
	for the offset being 34-bits when -mcpu=future is used.

From-SVN: r279937

We set TYPE_HAS_USER_CONSTRUCTOR on the template type in lookup_using_decl,
but we didn't copy it to the instantiation.  Setting it in
one_inherited_ctor is too late, as that gets called after we decide whether
to set CLASSTYPE_LAZY_DEFAULT_CTOR.  This change affects other testcases as
well; the changes are fixes for the other inherited constructor tests as
well.

	* pt.c (instantiate_class_template_1): Copy
	TYPE_HAS_USER_CONSTRUCTOR.
	* class.c (one_inherited_ctor): Don't set it here.

From-SVN: r279936

gcc/cp/
	* parser.c (cp_parser_constraint_requires_parens): Exclude
	attributes as postfix expressions.

gcc/testsuite/
	* g++.dg/concepts-pr92739.C: New test.

From-SVN: r279935

From-SVN: r279932

	* config/pa/pa.md: Revert change to use ordered_comparison_operator
	instead of cmpib_comparison_operator in cmpib patterns.
	* config/pa/predicates.md (cmpib_comparison_operator): Revert removal
	of cmpib_comparison_operator.  Revise comment.

From-SVN: r279927

IFN_DIV_POW2 currently requires all elements to be shifted by the
same amount, in a similar way as for WIDEN_LSHIFT_EXPR.  This patch
enforces that when building the SLP tree.

If in future targets want to support IFN_DIV_POW2 without this
restriction, we'll probably need the kind of vector-vector/
vector-scalar split that we already have for normal shifts.

2020-01-06  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
	* tree-vect-slp.c (vect_build_slp_tree_1): Require all shifts
	in an IFN_DIV_POW2 node to be equal.

gcc/testsuite/
	* gcc.target/aarch64/sve/asrdiv_1.c: Remove trailing %s.
	* gcc.target/aarch64/sve/asrdiv_2.c: New test.
	* gcc.target/aarch64/sve/asrdiv_3.c: Likewise.

From-SVN: r279908

We can't yet vectorise conditional internal functions whose boolean
condition is fed by a data access (or more generally, by a tree of logic
ops in which all the leaves are data accesses).  Although we should add
that eventually, we'd need further work to generate good-quality code.

Unlike vectorizable_load and vectorizalbe_store, vectorizable_call
wasn't checking whether the mask had a suitable type, leading to an
ICE on the testcases.

2020-01-06  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
	* tree-vect-stmts.c (vect_check_load_store_mask): Rename to...
	(vect_check_scalar_mask): ...this.
	(vectorizable_store, vectorizable_load): Update call accordingly.
	(vectorizable_call): Use vect_check_scalar_mask to check the mask
	argument in calls to conditional internal functions.

gcc/testsuite/
	* gcc.dg/vect/vect-cond-arith-8.c: New test.
	* gcc.target/aarch64/sve/cond_fmul_5.c: Likewise.

From-SVN: r279907

2020-01-06  Andrew Stubbs  <ams@codesourcery.com>

	gcc/
	* config/gcn/gcn-valu.md (subv64di3): Use separate alternatives for
	'0' matching inputs.
	(subv64di3_exec): Likewise.

From-SVN: r279906

2020-01-06  Bryan Stenson  <bryan@siliconvortex.com>

	* config/mips/mips.c (vr4130_align_insns): Fix typo.
	* doc/md.texi (movstr): Likewise.

From-SVN: r279905

2020-01-06  Andrew Stubbs  <ams@codesourcery.com>

	gcc/
	* config/gcn/gcn-valu.md (vec_extract<mode><scalar_mode>): Add early
	clobber.

From-SVN: r279904