Skip to content

R
riscv-gcc-1
Switch branch/tag
  1. 25 Jul, 2017 30 commits
  3. 24 Jul, 2017 10 commits
    • PR testsuite/80759 Fix broken tests in ms-sysv.exp · 52d0f7bd 
      2017-07-24  Daniel Santos  <daniel.santos@pobox.com>

	PR testsuite/80759
	* gcc.target/x86_64/abi/ms-sysv/do-test.S
	(ELFFN_BEGIN): Rename to FN_TYPE.
	(ELFFN_END): Rename to FN_SIZE.
	(ASMNAME): New macro.
	(FUNC): Rename to FUNC_BEGIN, use ASMNAME and use .globl instead of
	.global.
	(FUNC_END): Use ASMNAME.
	(test_data_save): Remove.
	(test_data_input): Likewise.
	(test_data_output: Likewise.
	(test_data_fn): Likewise.
	(test_data_retaddr): Likewise.
	(regs_to_mem): Make globals, use r10 instead of rax.
	(mem_to_regs): Likewise.
	(do_test_unaligned): Remove .cfi directives, remove pushf/popf, move
	body to ms-sysv.c.
	(do_test_aligned): Likewise.
	* gcc.target/x86_64/abi/ms-sysv/ms-sysv.c:
	Add dg-* directives.
	(PASTE_STR): New macro.
	(ASMNAME): Likewise.
	(LOAD_TEST_DATA_ADDR): Likewise.
	(TEST_DATA_OFFSET): Likewise.
	(do_test_body0): New C function.
	(do_test_body): New inline assembly routine.
	* gcc.target/x86_64/abi/ms-sysv/ms-sysv.exp
	(runtest_ms_sysv): Modify.

From-SVN: r250489
      Daniel Santos committed
    • PR testsuite/80759 Fix -mcall-ms2sysv-xlogues on Darwin and Solaris · 9cbc07cc 
      2017-07-24  Daniel Santos  <daniel.santos@pobox.com>

	PR testsuite/80759
	* config.host: include i386/t-msabi for darwin and solaris.
	* config/i386/i386-asm.h
	(ELFFN): Rename to FN_TYPE.
	(FN_SIZE): New macro.
	(FN_HIDDEN): Likewise.
	(ASMNAME): Likewise.
	(FUNC_START): Rename to FUNC_BEGIN, use ASMNAME, replace .global with
	.globl.
	(HIDDEN_FUNC): Use ASMNAME and .globl instead of .global.
	(SSE_SAVE): Convert to cpp macro, hard-code offset (always 0x60).
	* config/i386/resms64.S: Use SSE_SAVE as cpp macro instead of gas
	.macro.
	* config/i386/resms64f.S: Likewise.
	* config/i386/resms64fx.S: Likewise.
	* config/i386/resms64x.S: Likewise.
	* config/i386/savms64.S: Likewise.
	* config/i386/savms64f.S: Likewise.

From-SVN: r250488
      Daniel Santos committed
    • rs6000-cpus.def (ISA_2_6_MASKS_SERVER): Delete upper-regs options. · 19930989 
      [gcc]
2017-07-24  Michael Meissner  <meissner@linux.vnet.ibm.com>

	* config/rs6000/rs6000-cpus.def (ISA_2_6_MASKS_SERVER): Delete
	upper-regs options.
	(ISA_2_7_MASKS_SERVER): Likewise.
	(ISA_3_0_MASKS_IEEE): Likewise.
	(OTHER_P8_VECTOR_MASKS): Likewise.
	(OTHER_VSX_VECTOR_MASKS): Likewise.
	(POWERPC_MASKS): Likewise.
	(power7 cpu): Use ISA_2_6_MASKS_SERVER instead of using a
	duplicate list of options.
	* config/rs6000/rs6000-c.c (rs6000_target_modify_macros): Remove
	explicit -mupper-regs options.
	* config/rs6000/rs6000.opt (-mvsx-scalar-memory): Delete
	-mupper-regs* options.  Delete -mvsx-scalar-memory, which was an
	alias for -mupper-regs-df.
	* config/rs6000/rs6000.c (rs6000_setup_reg_addr_masks): Likewise.
	(rs6000_init_hard_regno_mode_ok): Likewise.
	(rs6000_option_override_internal): Likewise.
	(rs6000_opt_masks): Likewise.
	* config/rs6000/rs6000.h (TARGET_UPPER_REGS_DF): Define upper regs
	options in terms of whether -mvsx or -mpower8-vector was used.
	(TARGET_UPPER_REGS_DI): Likewise.
	(TARGET_UPPER_REGS_SF): Likewise.
	* doc/invoke.texi (RS/6000 and PowerPC Options): Delete the
	-mupper-regs-* options.

[gcc/testsuite]
2017-07-24  Michael Meissner  <meissner@linux.vnet.ibm.com>

	* gcc.target/powerpc/pr65849-1.c: Delete, test no longer valid
	since the upper-regs options have been deleted.
	* gcc.target/powerpc/pr65849-2.c: Likewise.
	* gcc.target/powerpc/pr80099-1.c: Likewise.
	* gcc.target/powerpc/pr80099-2.c: Likewise.
	* gcc.target/powerpc/pr80099-3.c: Likewise.
	* gcc.target/powerpc/pr80099-4.c: Likewise.
	* gcc.target/powerpc/pr80099-5.c: Likewise.
	* gcc.target/powerpc/builtins-2-p9-runnable.c: Update test to
	support removal of the upper-regs options.
	* gcc.target/powerpc/p8vector-fp.c: Likewise.
	* gcc.target/powerpc/p8vector-ldst.c: Likewise.
	* gcc.target/powerpc/p9-dimode1.c: Likewise.
	* gcc.target/powerpc/p9-dimode2.c: Likewise.
	* gcc.target/powerpc/ppc-fpconv-1.c: Likewise.
	* gcc.target/powerpc/ppc-fpconv-10.c: Likewise.
	* gcc.target/powerpc/ppc-fpconv-5.c: Likewise.
	* gcc.target/powerpc/ppc-fpconv-9.c: Likewise.
	* gcc.target/powerpc/ppc-round.c: Likewise.
	* gcc.target/powerpc/pr71720.c: Likewise.
	* gcc.target/powerpc/pr72853.c: Likewise.
	* gcc.target/powerpc/pr79907.c: Likewise.
	* gcc.target/powerpc/pr78953.c: Likewise.
	* gcc.target/powerpc/upper-regs-df.c: Likewise.
	* gcc.target/powerpc/upper-regs-sf.c: Likewise.
	* gcc.target/powerpc/vec-extract-1.c: Likewise.
	* gcc.target/powerpc/vec-init-3.c: Likewise.
	* gcc.target/powerpc/vec-init-6.c: Likewise.
	* gcc.target/powerpc/vec-init-7.c: Likewise.
	* gcc.target/powerpc/vec-set-char.c: Likewise.
	* gcc.target/powerpc/vec-set-int.c: Likewise.
	* gcc.target/powerpc/vec-set-short.c: Likewise.

From-SVN: r250482
      Michael Meissner committed
    • passes: Print a header in emergency_dump_function · 0281547a 
      Currently the emergency dump has no separation whatsoever from any
previous output in the dump file, making it harder than necessary
to find.


	* passes.c (emergency_dump_function): Print some empty lines and a
	header before the RTL dump.

From-SVN: r250481
      Segher Boessenkool committed
    • cfgrtl: Don't crash in rtl_dump_bb if BB_END(bb) is NULL · 9fcaf059 
      Currently rtl_dump_bb crashes if BB_END(bb) is NULL, like it can be
during expand (rtl_dump_bb can be called at any time, by the emergency
dump added recently for example).

This fixes it.


	* cfgrtl.c (rtl_dump_bb): Don't call NEXT_INSN on NULL.

From-SVN: r250480
      Segher Boessenkool committed
    • re PR target/79041 (aarch64 backend emits R_AARCH64_ADR_PREL_PG_HI21 relocation… · d47d34bb 
      re PR target/79041 (aarch64 backend emits R_AARCH64_ADR_PREL_PG_HI21 relocation despite -mpc-relative-literal-loads option being used)

Fix PR79041

As described in PR79041, -mcmodel=large -mpc-relative-literal-loads
may be used to avoid generating ADRP/ADD or ADRP/LDR.  However both
trunk and GCC7 may still emit ADRP for some constant pool literals.
Fix this by adding a aarch64_pcrelative_literal_loads check.

gcc/
	PR target/79041
	* config/aarch64/aarch64.c (aarch64_classify_symbol):
	Avoid SYMBOL_SMALL_ABSOLUTE for literals with pc-relative literals
gcc/testsuite/
	* gcc.target/aarch64/pr79041-2.c: New test.

From-SVN: r250478
      Wilco Dijkstra committed
    • rs6000-c.c: Add support for built-in functions vector float vec_extract_fp32_from_shorth... · 26bca0ed 
      gcc/ChangeLog:

2017-07-24  Carl Love  <cel@us.ibm.com>

	* config/rs6000/rs6000-c.c: Add support for built-in functions
	vector float vec_extract_fp32_from_shorth (vector unsigned short);
	vector float vec_extract_fp32_from_shortl (vector unsigned short);
	* config/rs6000/altivec.h (vec_extract_fp_from_shorth,
	vec_extract_fp_from_shortl): Add defines for the two builtins.
	* config/rs6000/rs6000-builtin.def (VEXTRACT_FP_FROM_SHORTH,
	VEXTRACT_FP_FROM_SHORTL): Add BU_P9V_OVERLOAD_1 and BU_P9V_VSX_1
	new builtins.
	* config/rs6000/vsx.md vsx_xvcvhpsp): Add define_insn.
	(vextract_fp_from_shorth, vextract_fp_from_shortl): Add define_expands.
	* doc/extend.texi: Update the built-in documentation file for the
	new built-in function.

gcc/testsuite/ChangeLog:

2017-07-24  Carl Love  <cel@us.ibm.com>

	* gcc.target/powerpc/builtins-3-p9-runnable.c: Add new test file for
	the new built-ins.

From-SVN: r250477
      Carl Love committed
    • re PR target/81521 (After [r250413] GCC 8.0 doesn't compile for Windows) · 570e228b 
      	PR bootstrap/81521
	* tree.def: Remove TYPE_METHODS documentation, adjust TYPE_FIELDS
	documentation.
	* doc/generic.texi: Likewise.
	* config/i386/winnt-cxx.c (i386_pe_adjust_class_at_definition): Look
	for FUNCTION_DECLs in TYPE_FIELDS rather than TYPE_METHODS.

From-SVN: r250476
      Jakub Jelinek committed
    • [AArch64, Patch] Generate MLA when multiply + add vector by scalar · 4b40986c 
      (On behalf of jackson.woodruff@arm.com)

This merges vector multiplies and adds into a single mla instruction
when the multiplication is done by a scalar.

    typedef int __attribute__((vector_size(16))) vec;

    vec
    mla1(vec v0, vec v1, int v2)
    {
      return v0 + v1 * c;
    }

Now generates:

    mla1:
        fmov   s2, w0
        mla    v0.4s, v1.4s, v2.s[0]

This is also done for the identical case for a multiply followed by a
subtract of vectors with an integer operand on the multiply.

gcc/

2017-07-24  Jackson Woodruff  <jackson.woodruff@arm.com>

        * config/aarch64/aarch64-simd.md (aarch64_mla_elt_merge<mode>): New.
        (aarch64_mls_elt_merge<mode>): Likewise.

gcc/testsuite/

2017-07-24  Jackson Woodruff  <jackson.woodruff@arm.com>

	* gcc.target/aarch64/simd/vmla_elem_1.c: New.

From-SVN: r250475
      Jackson Woodruff committed
    • ChangeLog: Fix typo in date and ommitted PR number. · e678ce86 
      2017-07-24  Thomas Koenig  <tkoenig@gcc.gnu.org>

	* ChangeLog: Fix typo in date and ommitted PR number.

From-SVN: r250474
      Thomas Koenig committed