re PR target/81414 (ICE in fma steering on AArch64/cortex-a57)

	PR target/81414
	* config/aarch64/cortex-a57-fma-steering.c (analyze): Skip fmul/fmac
	instructions if no du chain is found.

	gcc/testsuite
	* gcc.target/aarch64/pr81414.C: New.

From-SVN: r250496

gcc/ChangeLog

+2017-07-25  Bin Cheng  <bin.cheng@arm.com>
+
+	PR target/81414
+	* config/aarch64/cortex-a57-fma-steering.c (analyze): Skip fmul/fmac
+	instructions if no du chain is found.
+
 2017-07-25  Georg-Johann Lay  <avr@gjlay.de>
 
 	* config/avr/avr-log.c (avr_log_vadump) ['T']: Print NULL-TREE.

gcc/config/aarch64/cortex-a57-fma-steering.c

@@ -973,10 +973,17 @@ func_fma_steering::analyze ()
 		break;
 	    }
 
-	  /* We didn't find a chain with a def for this instruction.  */
-	  gcc_assert (i < dest_op_info->n_chains);
-
-	  this->analyze_fma_fmul_insn (forest, chain, head);
+	  /* Due to implementation of regrename, dest register can slip away
+	     from regrename's analysis.  As a result, there is no chain for
+	     the destination register of insn.  We simply skip the insn even
+	     it is a fmul/fmac instruction.  This can happen when the dest
+	     register is also a source register of insn and one of the below
+	     conditions is satisfied:
+	       1) the source reg is setup in larger mode than this insn;
+	       2) the source reg is uninitialized;
+	       3) the source reg is passed in as parameter.  */
+	  if (i < dest_op_info->n_chains)
+	    this->analyze_fma_fmul_insn (forest, chain, head);
 	}
     }
   free (bb_dfs_preorder);

gcc/testsuite/ChangeLog

+2017-07-25  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	PR target/81414
+	* gcc.target/aarch64/pr81414.C: New.
+
 2017-07-25  Richard Biener  <rguenther@suse.de>
 
 	PR middle-end/81505

gcc/testsuite/gcc.target/aarch64/pr81414.C

+/* { dg-do compile } */
+/* { dg-options "-O2 -mcpu=cortex-a57" } */
+
+typedef __Float32x2_t float32x2_t;
+float32x2_t
+foo1 (float32x2_t __a, float32x2_t __b, float32x2_t __c) {
+  return __b * __c + __a;
+}
+