* tree-ssa-loop-ivopts.c (avg_loop_niter): Fix coding style.
	(struct cost_pair): Change inv_expr_id (int) to inv_expr
	(iv_inv_expr_ent *).
	(struct iv_inv_expr_ent): Comment struct fields.
	(sort_iv_inv_expr_ent): New function.
	(struct ivopts_data): Rename inv_expr_id to max_inv_expr_id.
	(struct iv_ca): Replace used_inv_expr and num_used_inv_expr with
	a hash_map between iv_inv_expr_ent and number of usages.
	(niter_for_exit): Fix coding style.
	(tree_ssa_iv_optimize_init): Use renamed variable.
	(determine_base_object): Fix coding style.
	(alloc_iv): Likewise.
	(find_interesting_uses_outside): Likewise.
	(add_candidate_1): Likewise.
	(add_standard_iv_candidates): Likewise.
	(set_group_iv_cost): Replace inv_expr_id with inv_expr.
	(prepare_decl_rtl): Fix coding style.
	(get_address_cost): Likewise.
	(get_shiftadd_cost): Likewise.
	(force_expr_to_var_cost): Likewise.
	(compare_aff_trees): Likewise.
	(get_expr_id): Restructure the function.
	(get_loop_invariant_expr_id): Renamed to
	get_loop_invariant_expr.
	(get_computation_cost_at): Replace usage of inv_expr_id with
	inv_expr.
	(get_computation_cost): Likewise.
	(determine_group_iv_cost_generic): Likewise.
	(determine_group_iv_cost_address): Likewise.
	(iv_period): Fix coding style.
	(iv_elimination_compare_lt): Likewise.
	(may_eliminate_iv): Likewise.
	(determine_group_iv_cost_cond):  Replace usage of inv_expr_id with
	inv_expr.
	(determine_group_iv_costs): Dump invariant expressions.
	(iv_ca_recount_cost): Use the newly added hash_map.
	(iv_ca_set_remove_invariants): Fix coding style.
	(iv_ca_set_add_invariants): Fix coding style.
	(iv_ca_set_no_cp): Utilize the newly added hash_map for used
	invariants.
	(iv_ca_set_cp): Likewise.
	(iv_ca_new): Initialize the newly added hash_map and remove
	initialization of fields.
	(iv_ca_free): Delete the hash_map.
	(iv_ca_dump): Dump invariant expressions.
	(iv_ca_extend): Fix coding style.
	(try_add_cand_for): Likewise.
	(create_new_ivs): Dump information about # of avg iterations and
	# of used invariant expressions.
	(rewrite_use_compare): Fix coding style.
	(free_loop_data): Set default value for max_inv_expr_id.
	* g++.dg/tree-ssa/ivopts-3.C: Change test-case to follow
	the new format of dump output.

From-SVN: r236200

gcc/

	* cse.c (rest_of_handle_cse): Use cleanup_cfg
	returned value cse_cfg_altered computation.
	(rest_of_handle_cse2): Likewise.
	(rest_of_handle_cse_after_global_opts): Likewise.

gcc/testsuite/

	* gcc.dg/pr71084.c: New test.

From-SVN: r236199

This partially fixes PR target/53440 atleast in ARM and
Thumb2 state. I haven't yet managed to get my head around
rewriting the Thumb1 support yet.

Tested on armhf with a bootstrap and regression test
with no regressions.

Queued for stage1 now as it isn't technically a regression.

regards
Ramana


2016-05-13  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>

        PR target/53440
        * config/arm/arm.c (arm32_output_mi_thunk): New.
        (arm_output_mi_thunk): Rename to arm_thumb1_mi_thunk. Rework
        to split Thumb1 vs TARGET_32BIT functionality.
        (arm_thumb1_mi_thunk): New.


        * g++.dg/inherit/thunk1.C: Support arm / aarch64.

From-SVN: r236198

The reason this caught my eye on aarch64 is because
the return value register (x0) is not identical to the register in which
the hidden parameter for AArch64 is set (x8). Thus setting this to true
seems to be quite reasonable and shaves off 100 odd mov x0, x8's from
cc1 in a bootstrap build.

I don't expect this to make a huge impact on performance but as they
say every little counts.  The AAPCS64 is quite explicit about not
requiring that the contents of x8 be kept live.

Bootstrapped and regression tested on aarch64.

Ok to apply ?

Ramana

gcc/
* config/aarch64/aarch64.c (TARGET_OMIT_STRUCT_RETURN_REG): Set to
true.

gcc/testsuite

* gcc.target/aarch64/struct_return.c: New test.

From-SVN: r236197

	PR target/71080
	* config/i386/i386.c (ix86_in_large_data_p): Guard against NULL exp.

From-SVN: r236196

	* builtins.c (expand_builtin_memcmp): Do not emit the call here.
	(expand_builtin_trap): Emit a regular call.
	(set_builtin_user_assembler_name): Remove obsolete cases.
	* dse.c (scan_insn): Adjust.
	* except.c: Include calls.h.
	(sjlj_emit_function_enter): If DONT_USE_BUILTIN_SETJMP is defined,
	emit a regular call to setjmp.
	* expr.c (emit_block_move_hints): Call emit_block_copy_via_libcall.
	(block_move_libcall_safe_for_call_parm): Use memcpy builtin.
	(emit_block_move_via_libcall): Delete.
	(block_move_fn): Delete.
	(init_block_move_fn): Likewise.
	(emit_block_move_libcall_fn): Likewise.
	(emit_block_op_via_libcall): New function.
	(set_storage_via_libcall): Tidy up and use memset builtin.
	(block_clear_fn): Delete.
	(init_block_clear_fn): Likewise.
	(clear_storage_libcall_fn): Likewise.
	(expand_assignment): Call emit_block_move_via_libcall.
	Do not include gt-expr.h.
	* expr.h (emit_block_op_via_libcall): Declare.
	(emit_block_copy_via_libcall): New inline function.
	(emit_block_move_via_libcall): Likewise.
	(emit_block_comp_via_libcall): Likewise.
	(block_clear_fn): Delete.
	(init_block_move_fn): Likewise.
	(init_block_clear_fn): Likewise.
	(emit_block_move_via_libcall): Likewise.
	(set_storage_via_libcall): Add default parameter value.
	* libfuncs.h (enum libfunc_index): Remove obsolete values.
	(abort_libfunc): Delete.
	(memcpy_libfunc): Likewise.
	(memmove_libfunc): Likewise.
	(memcmp_libfunc): Likewise.
	(memset_libfunc): Likewise.
	(setbits_libfunc): Likewise.
	(setjmp_libfunc): Likewise.
	(longjmp_libfunc): Likewise.
	(profile_function_entry_libfunc): Likewise.
	(profile_function_exit_libfunc): Likewise.
	(gcov_flush_libfunc): Likewise.
	* optabs-libfuncs.c (build_libfunc_function): Set DECL_ARTIFICIAL
	and DECL_VISIBILITY on the declaration.
	(init_optabs): Do not initialize obsolete libfuncs.
	* optabs.c (prepare_cmp_insn): Call emit_block_comp_via_libcall.
	* tree-core.h (ECF_RET1): Define.
	(ECF_TM_PURE): Adjust.
	(ECF_TM_BUILTIN): Likewise.
	* tree.c (set_call_expr_flags): Deal with ECF_RET1.
	(build_common_builtin_nodes): Initialize abort builtin.
	Add ECF_RET1 on memcpy, memmove and memset builtins.
	Pass final flags for alloca and alloca_with_align builtins.
	* config/alpha/alpha.c (alpha_init_libfuncs): Do not initialize
	obsolete builtins.
	* config/ia64/ia64.c (ia64_vms_init_libfuncs): Likewise.
	* config/i386/i386.c (ix86_expand_set_or_movmem): Adjust call to
	set_storage_via_libcall and call emit_block_copy_via_libcall.

From-SVN: r236195

From-SVN: r236189

From-SVN: r236183

i386.md (*call_got_x32): Change operand 0 to DImode before it is passed to ix86_output_call_operand.

	* config/i386/i386.md (*call_got_x32): Change operand 0 to
	DImode before it is passed to ix86_output_call_operand.
	(*call_value_got_x32): Ditto for operand 1.

From-SVN: r236182

2016-05-12  Jiong Wang  <jiong.wang@arm.com>

gcc/
  PR rtl-optimization/70904
  * lra-constraint.c (process_addr_reg): Relax the restriction on
  subreg reload for wide mode.

From-SVN: r236181

	PR c/70756
	* c-common.c (pointer_int_sum): Call size_in_bytes_loc instead of
	size_in_bytes and pass LOC to it.

	* c-decl.c (build_compound_literal): Pass LOC down to
	c_incomplete_type_error.
	* c-tree.h (require_complete_type): Adjust declaration.
	(c_incomplete_type_error): Likewise.
	* c-typeck.c (require_complete_type): Add location parameter, pass it
	down to c_incomplete_type_error.
	(c_incomplete_type_error): Add location parameter, pass it down to
	error_at.
	(build_component_ref): Pass location down to c_incomplete_type_error.
	(default_conversion): Pass location down to require_complete_type.
	(build_array_ref): Likewise.
	(build_function_call_vec): Likewise.
	(convert_arguments): Likewise.
	(build_unary_op): Likewise.
	(build_c_cast): Likewise.
	(build_modify_expr): Likewise.
	(convert_for_assignment): Likewise.
	(c_finish_omp_clauses): Likewise.

	* call.c (build_new_op_1): Pass LOC to cp_build_modify_expr.
	* cp-tree.h (cp_build_modify_expr): Update declaration.
	(cxx_incomplete_type_error, cxx_incomplete_type_diagnostic): New inline
	overloads.
	* cp-ubsan.c (cp_ubsan_dfs_initialize_vtbl_ptrs): Pass INPUT_LOCATION to
	cp_build_modify_expr.
	* decl2.c (set_guard): Likewise.
	(handle_tls_init): Likewise.
	* init.c (perform_member_init): Likewise.
	(expand_virtual_init): Likewise.
	(build_new_1): Likewise.
	(build_vec_delete_1): Likewise.
	(get_temp_regvar): Likewise.
	(build_vec_init): Likewise.
	* method.c (do_build_copy_assign): Likewise.
	(assignable_expr): Likewise.
	* semantics.c (finish_omp_for): Likewise.
	* typeck.c (cp_build_binary_op): Pass LOCATION to pointer_diff and
	cp_pointer_int_sum.
	(cp_pointer_int_sum): Add location parameter.  Pass it down to
	pointer_int_sum.
	(pointer_diff): Add location parameter.  Use it.
	(build_modify_expr): Pass location down to cp_build_modify_expr.
	(cp_build_modify_expr): Add location parameter.  Use it.
	(build_x_modify_expr): Pass location down to cp_build_modify_expr.
	* typeck2.c (cxx_incomplete_type_diagnostic,
	cxx_incomplete_type_error): Add location parameter.

	* langhooks-def.h (lhd_incomplete_type_error): Adjust declaration.
	* langhooks.c (lhd_incomplete_type_error): Add location parameter.
	* langhooks.h (incomplete_type_error): Likewise.
	* tree.c (size_in_bytes_loc): Renamed from size_in_bytes.  Add location
	parameter, pass it down to incomplete_type_error.
	* tree.h (size_in_bytes): New inline overload.
	(size_in_bytes_loc): Renamed from size_in_bytes.

	* c-c++-common/pr70756-2.c: New test.
	* c-c++-common/pr70756.c: New test.

From-SVN: r236180

	PR libstdc++/71081
	* testsuite/experimental/memory_resource/1.cc: Require atomics.

From-SVN: r236177

re PR tree-optimization/71059 (gcc ICE at -O3 on valid code on x86_64-linux-gnu in "vn_nary_op_insert_into")

2016-05-12  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/71059
	* tree-ssa-pre.c (phi_translate_1): Fully fold translated
	nary before looking up or entering the expression into the VN
	hashes.
	* tree-ssa-sccvn.c (vn_nary_build_or_lookup): Fix comment typo.
	Make sure to re-use NARYs without result as inserted by
	phi-translation.

	* gcc.dg/torture/pr71059.c: New testcase.

From-SVN: r236175

2016-05-12  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/71062
	* tree-ssa-alias.h (struct pt_solution): Add vars_contains_restrict
	field.
	* tree-ssa-structalias.c (set_uids_in_ptset): Set vars_contains_restrict
	if the var is a restrict tag.
	* tree-ssa-alias.c (ptrs_compare_unequal): If vars_contains_restrict
	do not disambiguate pointers against it.
	(dump_points_to_solution): Re-structure and adjust for new
	vars_contains_restrict flag.
	* gimple-pretty-print.c (pp_points_to_solution): Likewise.

	* gcc.dg/torture/pr71062.c: New testcase.

From-SVN: r236174

	* doc/invoke.texi: Explain connection between -fsanitize-recover=address
	and ASAN_OPTIONS="halt_on_error=1".

From-SVN: r236172

re PR tree-optimization/71006 (ICE: verify_gimple failed (error: type mismatch in conditional expression) w/ -O1 -ftree-loop-vectorize)

gcc/

	PR tree-optimization/71006
	* tree-vect-loop.c (vect_determine_vectorization_factor): Don't
	consider COND_EXPR as a mask producer.

gcc/testsuite/

	PR tree-optimization/71006
	* gcc.dg/pr71006.c: New test.

From-SVN: r236171

	PR driver/71063
	* opts.c (common_handle_option): Detect missing argument for --help^.

	* gcc.dg/opts-7.c: New test.

From-SVN: r236170

	PR target/70830
	* config/arm/arm.c (arm_output_multireg_pop): Avoid POP instruction
	when popping the PC and within an interrupt handler routine.
	Add missing tab to output of "ldmfd".
	(output_return_instruction): Output LDMFD with SP update rather
	than POP when returning from interrupt handler.

	* gcc.target/arm/interrupt-1.c: Change dg-compile to dg-assemble.
	Add -save-temps to dg-options.
	Scan for ldmfd rather than pop instruction.
	* gcc.target/arm/interrupt-2.c: Likewise.
	* gcc.target/arm/pr70830.c: New test.

From-SVN: r236169

	* config/i386/i386.md (isa): Add x64_avx512dq, enable if
	TARGET_64BIT && TARGET_AVX512DQ.
	* config/i386/sse.md (*vec_extract<mode>): Add avx512bw alternatives.
	(*vec_extract<PEXTR_MODE12:mode>_zext): Add avx512bw alternative.
	(*vec_extract<ssevecmodelower>_0, *vec_extractv4si_0_zext,
	*vec_extractv2di_0_sse): Use v constraint instead of x constraint.
	(*vec_extractv4si): Add avx512dq and avx512bw alternatives.
	(*vec_extractv4si_zext): Add avx512dq alternative.
	(*vec_extractv2di_1): Add x64_avx512dq and avx512bw alternatives,
	use v instead of x constraint in other alternatives where possible.

	* gcc.target/i386/avx512bw-vpextr-1.c: New test.
	* gcc.target/i386/avx512dq-vpextr-1.c: New test.

From-SVN: r236167

	* config/i386/sse.md (sse2_loadld): Use v instead of x
	constraint in alternatives 0,1,4.

From-SVN: r236166

	* config/i386/sse.md (pinsr_evex_isa): New mode attr.
	(<sse2p4_1>_pinsr<ssemodesuffix>): Add 2 alternatives with
	v constraints instead of x and <pinsr_evex_isa> isa attribute.

	* gcc.target/i386/avx512bw-vpinsr-1.c: New test.
	* gcc.target/i386/avx512dq-vpinsr-1.c: New test.
	* gcc.target/i386/avx512vl-vpinsr-1.c: New test.

From-SVN: r236165

	PR target/71019
	* config/i386/sse.md (<sse2_avx2>_packssdw<mask_name>,
	<sse4_1_avx2>_packusdw<mask_name>): Make sure EVEX encoded insn
	is not emitted unless TARGET_AVX512BW.
	(<sse2_avx2>_packuswb<mask_name>, <sse2_avx2>_packsswb<mask_name>):
	Likewise.  For TARGET_AVX512BW, use "=v" constraint instead of "=x"
	for the result operand.

	* gcc.target/i386/avx512vl-pack-1.c: New test.
	* gcc.target/i386/avx512vl-pack-2.c: New test.
	* gcc.target/i386/avx512bw-pack-2.c: New test.

From-SVN: r236163

	* config/i386/sse.md (*vec_setv4sf_sse4_1, sse4_1_insertps): Use v
	constraint instead of x in avx alternatives.  Use maybe_evex instead
	of vex prefix.

	* gcc.target/i386/avx512vl-vinsertps-1.c: New test.

From-SVN: r236162

	* config/i386/constraints.md (Yv): New constraint.
	* config/i386/i386.h (VALID_AVX512VL_128_REG_MODE): Allow
	TFmode and V1TImode in xmm16+ registers for TARGET_AVX512VL.
	* config/i386/i386.md (avx512fvecmode): New mode attr.
	(*pushtf): Use v constraint instead of x.
	(*movtf_internal): Likewise.  For TARGET_AVX512VL and
	xmm16+ registers, use vmovdqu64 or vmovdqa64 instructions.
	(*absneg<mode>2): Use Yv constraint instead of x constraint.
	(*absnegtf2_sse): Likewise.
	(copysign<mode>3_const, copysign<mode>3_var): Likewise.
	* config/i386/sse.md (*andnot<mode>3): Add avx512vl and
	avx512f alternatives.
	(*andnottf3, *<code><mode>3, *<code>tf3): Likewise.

	* gcc.target/i386/avx512dq-abs-copysign-1.c: New test.
	* gcc.target/i386/avx512vl-abs-copysign-1.c: New test.
	* gcc.target/i386/avx512vl-abs-copysign-2.c: New test.

From-SVN: r236161

2016-05-12  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/71060
	* tree-data-ref.c (initialize_data_dependence_relation): Do not
	require exact match of DR_BASE_OBJECT but only matching address and
	type.

From-SVN: r236159

re PR tree-optimization/70986 (ICE on valid code at -O3 on x86_64-linux-gnu in combine_blocks, at tree-if-conv.c:2219)

2016-05-12  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/70986
	* cfganal.c: Include cfgloop.h.
	(dfs_find_deadend): Prefer to take edges exiting loops.

	* gcc.dg/torture/pr70986-1.c: New testcase.
	* gcc.dg/torture/pr70986-2.c: Likewise.
	* gcc.dg/torture/pr70986-3.c: Likewise.

From-SVN: r236158

From-SVN: r236152

2016-05-11  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>

	* gcc.target/powerpc/pr70963.c: Require at least power8 at both
	compile and run time.

From-SVN: r236146

gcc/c/

	PR c/43651
	* c-decl.c (declspecs_add_qual): Warn when -Wduplicate-decl-specifier
	is enabled.
	* c-errors.c (pedwarn_c90): Return true if warned.
	* c-tree.h (pedwarn_c90): Change return type to bool.
	(enum c_declspec_word): Add new enumerator cdw_atomic.

gcc/

	PR c/43651
	* doc/invoke.texi (Wduplicate-decl-specifier): Document new option.

gcc/testsuite/

	PR c/43651
	* gcc.dg/Wduplicate-decl-specifier-c11.c: New test.
	* gcc.dg/Wduplicate-decl-specifier.c: Likewise.

gcc/c-family/

	PR c/43651
	* c.opt (Wduplicate-decl-specifier): New option.

From-SVN: r236142

	* gcc.target/i386/sse-13.c: Add dg-add-options bind_pic_locally
	directive.
	* gcc.target/i386/pr66746.c: Ditto.

From-SVN: r236140

	* config/i386/i386.c (legitimize_pic_address): Use
	copy_to_suggested_reg instead of gen_movsi.

From-SVN: r236138

predicates.md (quad_memory_operand): Move most of the code into quad_address_p and call it to share code with...

[gcc]
2016-05-11  Michael Meissner  <meissner@linux.vnet.ibm.com>

	* config/rs6000/predicates.md (quad_memory_operand): Move most of
	the code into quad_address_p and call it to share code with
	vsx_quad_dform_memory_operand.
	(vsx_quad_dform_memory_operand): New predicate for ISA 3.0 vector
	d-form support.
	* config/rs6000/rs6000.opt (-mlra): Switch to being an option mask
	bit instead of being a separate word.  Split -mpower9-dform into
	two switches, -mpower9-dform-scalar and -mpower9-dform-vector.
	* config/rs6000/rs6000.c (RELOAD_REG_QUAD_OFFSET): New addr_mask
	for the register class supporting 128-bit quad word memory
	offsets.
	(mode_supports_vsx_dform_quad): Helper function to return if the
	register class uses quad word memory offsets.
	(rs6000_debug_addr_mask): Add support for quad word memory
	offsets.
	(rs6000_debug_reg_global): Always print if we are using LRA or
	not.
	(rs6000_setup_reg_addr_masks): If ISA 3.0 vector d-form
	instructions are enabled, set up the appropriate addr_masks for
	128-bit types.
	(rs6000_init_hard_regno_mode_ok): wb constraint is now based on
	-mpower9-dform-scalar, instead of -mpower9-dform.
	(rs6000_option_override_internal): Split -mpower9-dform into two
	switches, -mpower9-dform-scalar and -mpower9-dform-vector.  The
	-mpower9-dform switch sets or clears both.  If we are not using
	the LRA register allocator, do not enable -mpower9-dform-vector by
	default.  If we are using LRA, enable -mpower9-dform-vector and
	-mvsx-timode if it is appropriate.  Issue a warning if either
	-mpower9-dform-vector or -mvsx-timode are explicitly used without
	enabling LRA.
	(quad_address_offset_p): New helper function to return if the
	offset is legal for quad word memory instructions.
	(quad_address_p): New function to determin if GPR or vector
	register quad word memory addresses are legal.
	(mem_operand_gpr): Validate quad word address offsets.
	(reg_offset_addressing_ok_p): Add support for ISA 3.0 vector
	d-form (register + offset) instructions.
	(offsettable_ok_by_alignment): Likewise.
	(rs6000_legitimate_offset_address_p): Likewise.
	(legitimate_lo_sum_address_p): Likewise.
	(rs6000_legitimize_address): Likewise.
	(rs6000_legitimize_reload_address): Add more debug statements for
	-mdebug=addr.
	(rs6000_legitimate_address_p): Add support for ISA 3.0 vector
	d-form instructions.
	(rs6000_secondary_reload_memory): Add support for ISA 3.0 vector
	d-form instructions.  Distinguish different cases in debug
	output.	(rs6000_secondary_reload_inner): Add support for ISA 3.0 vector
	d-form instructions.
	(rs6000_preferred_reload_class): Likewise.
	(rs6000_output_move_128bit): Add support for ISA 3.0 d-form
	instructions.  If ISA 3.0 is available, generate lxvx/stxvx instead
	of the ISA 2.06 indexed memory instructions.
	(rs6000_emit_prologue): If we have ISA 3.0 d-form instructions,
	use them to save/restore the saved vector registers instead of
	using Altivec instructions.
	(rs6000_emit_epilogue): Likewise.
	(rs6000_lra_p): Use TARGET_LRA instead of the old option word.
	(rs6000_opt_masks): Split -mpower9-dform into
	-mpower9-dform-scalar and -mpower9-dform-vector.
	(rs6000_print_options_internal): Print -mno-<switch> if <switch>
	was not selected.
	* config/rs6000/vsx.md (p9_vecload_<mode>): Delete hack to emit
	ISA 3.0 vector indexed memory instructions, and fold the code into
	the normal mov<mode> patterns.
	(p9_vecstore_<mode>): Likewise.
	(vsx_mov<mode>): Add support for ISA 3.0 vector d-form
	instructions.
	(vsx_movti_64bit): Likewise.
	(vsx_movti_32bit): Likewise.
	* config/rs6000/constraints.md (wO constraint): New constraint for
	ISA 3.0 vector d-form support.
	* config/rs6000/rs6000-cpus.def (ISA_3_0_MASKS_SERVER): Use
	-mpower9-dform-scalar instead of -mpower9-dform.  Add note not to
	include -mpower9-dform-vector until we switch over to LRA.
	(POWERPC_MASKS): Add -mlra. Split -mpower9-dform into two. 
	switches, -mpower9-dform-scalar and -mpower9-dform-vector.
	* config/rs6000/rs6000-protos.h (quad_address_p): Add declaration.
	* doc/invoke.texi (RS/6000 and PowerPC Options): Add documentation
	for -mpower9-dform and -mlra.
	* doc/md.texi (wO constraint): Document wO constraint.

[gcc/testsuite]
2016-05-11  Michael Meissner  <meissner@linux.vnet.ibm.com>

	* gcc.target/powerpc/dform-3.c: New test for ISA 3.0 vector d-form
	support.
	* gcc.target/powerpc/dform-1.c: Add -mlra option to silence
	warning when using -mvsx-timode.
	* gcc.target/powerpc/p8vector-int128-1.c: Likewise.
	* gcc.target/powerpc/dform-2.c: Likewise.
	* gcc.target/powerpc/pr68805.c: Likewise.

From-SVN: r236133

	* genattr.c (main): Change 'rtx' to 'rtx_insn *' in prototypes of
	'insn_latency', 'maximal_insn_latency', 'min_insn_conflict_delay'.
	* genautomata.c (output_internal_insn_code_evaluation): Simplify.
	Move handling of non-insn arguments inline into the sole user:
	(output_trans_func): ...here.
	(output_min_insn_conflict_delay_func): Change 'rtx' to 'rtx_insn *'
	in emitted function prototype.
	(output_internal_insn_latency_func): Ditto.  Simplify.
	(output_internal_maximal_insn_latency_func): Ditto.  Delete
	always-unused argument.
	(output_insn_latency_func): Ditto.
	(output_maximal_insn_latency_func): Ditto.

From-SVN: r236132

	* gcc.dg/attr-opt-1.c: Move to c-c++-common/.
	* gcc.dg/pr18079-2.c: Remove file.

From-SVN: r236130

	PR c++/71024
	* c-common.c (diagnose_mismatched_attributes): New function.
	* c-common.h (diagnose_mismatched_attributes): Declare.

	* c-decl.c (diagnose_mismatched_decls): Factor out code to
	diagnose_mismatched_attributes and call it.

	* decl.c (duplicate_decls): Call diagnose_mismatched_decls.

	* c-c++-common/attributes-3.c: New test.

From-SVN: r236129

	* gcc.dg/pr68671.c: Xfail on PTX -- assembler crash.
	* gcc.c-torture/execute/pr68185.c: Likewise.
	* gcc.dg/ipa/pr70306.c: Requires global constructors.
	* gcc.dg/pr69634.c: Requires scheduling.
	* gcc.dg/torture/pr66178.c: Require label values.
	* gcc.dg/setjmp-6.c: Require indirect jumps.

From-SVN: r236125

2016-05-11  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/71055
	* tree-ssa-sccvn.c (vn_reference_lookup_3): When native-interpreting
	sth with precision not equal to access size verify we don't chop
	off bits.

	* gcc.dg/torture/pr71055.c: New testcase.

From-SVN: r236122

2016-05-11  Richard Biener  <rguenther@suse.de>

	PR debug/71057
	* dwarf2out.c (retry_incomplete_types): Set early_dwarf.
	(dwarf2out_finish): Move retry_incomplete_types call ...
	(dwarf2out_early_finish): ... here.

	* g++.dg/debug/pr71057.C: New testcase.

From-SVN: r236121

	PR fortran/70855
	* frontend-passes.c (inline_matmul_assign): Disable in !$omp workshare.

	* gfortran.dg/gomp/pr70855.f90: New test.

From-SVN: r236119

	PR libstdc++/71049
	* src/c++11/cow-stdexcept.cc [!_GLIBCXX_USE_DUAL_ABI]: Don't define
	exception constructors with __sso_string parameters.

From-SVN: r236118