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Commit 3fd2b007 by Michael Meissner Committed by Michael Meissner
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predicates.md (quad_memory_operand): Move most of the code into quad_address_p… 

predicates.md (quad_memory_operand): Move most of the code into quad_address_p and call it to share code with...

[gcc]
2016-05-11  Michael Meissner  <meissner@linux.vnet.ibm.com>

	* config/rs6000/predicates.md (quad_memory_operand): Move most of
	the code into quad_address_p and call it to share code with
	vsx_quad_dform_memory_operand.
	(vsx_quad_dform_memory_operand): New predicate for ISA 3.0 vector
	d-form support.
	* config/rs6000/rs6000.opt (-mlra): Switch to being an option mask
	bit instead of being a separate word.  Split -mpower9-dform into
	two switches, -mpower9-dform-scalar and -mpower9-dform-vector.
	* config/rs6000/rs6000.c (RELOAD_REG_QUAD_OFFSET): New addr_mask
	for the register class supporting 128-bit quad word memory
	offsets.
	(mode_supports_vsx_dform_quad): Helper function to return if the
	register class uses quad word memory offsets.
	(rs6000_debug_addr_mask): Add support for quad word memory
	offsets.
	(rs6000_debug_reg_global): Always print if we are using LRA or
	not.
	(rs6000_setup_reg_addr_masks): If ISA 3.0 vector d-form
	instructions are enabled, set up the appropriate addr_masks for
	128-bit types.
	(rs6000_init_hard_regno_mode_ok): wb constraint is now based on
	-mpower9-dform-scalar, instead of -mpower9-dform.
	(rs6000_option_override_internal): Split -mpower9-dform into two
	switches, -mpower9-dform-scalar and -mpower9-dform-vector.  The
	-mpower9-dform switch sets or clears both.  If we are not using
	the LRA register allocator, do not enable -mpower9-dform-vector by
	default.  If we are using LRA, enable -mpower9-dform-vector and
	-mvsx-timode if it is appropriate.  Issue a warning if either
	-mpower9-dform-vector or -mvsx-timode are explicitly used without
	enabling LRA.
	(quad_address_offset_p): New helper function to return if the
	offset is legal for quad word memory instructions.
	(quad_address_p): New function to determin if GPR or vector
	register quad word memory addresses are legal.
	(mem_operand_gpr): Validate quad word address offsets.
	(reg_offset_addressing_ok_p): Add support for ISA 3.0 vector
	d-form (register + offset) instructions.
	(offsettable_ok_by_alignment): Likewise.
	(rs6000_legitimate_offset_address_p): Likewise.
	(legitimate_lo_sum_address_p): Likewise.
	(rs6000_legitimize_address): Likewise.
	(rs6000_legitimize_reload_address): Add more debug statements for
	-mdebug=addr.
	(rs6000_legitimate_address_p): Add support for ISA 3.0 vector
	d-form instructions.
	(rs6000_secondary_reload_memory): Add support for ISA 3.0 vector
	d-form instructions.  Distinguish different cases in debug
	output.	(rs6000_secondary_reload_inner): Add support for ISA 3.0 vector
	d-form instructions.
	(rs6000_preferred_reload_class): Likewise.
	(rs6000_output_move_128bit): Add support for ISA 3.0 d-form
	instructions.  If ISA 3.0 is available, generate lxvx/stxvx instead
	of the ISA 2.06 indexed memory instructions.
	(rs6000_emit_prologue): If we have ISA 3.0 d-form instructions,
	use them to save/restore the saved vector registers instead of
	using Altivec instructions.
	(rs6000_emit_epilogue): Likewise.
	(rs6000_lra_p): Use TARGET_LRA instead of the old option word.
	(rs6000_opt_masks): Split -mpower9-dform into
	-mpower9-dform-scalar and -mpower9-dform-vector.
	(rs6000_print_options_internal): Print -mno-<switch> if <switch>
	was not selected.
	* config/rs6000/vsx.md (p9_vecload_<mode>): Delete hack to emit
	ISA 3.0 vector indexed memory instructions, and fold the code into
	the normal mov<mode> patterns.
	(p9_vecstore_<mode>): Likewise.
	(vsx_mov<mode>): Add support for ISA 3.0 vector d-form
	instructions.
	(vsx_movti_64bit): Likewise.
	(vsx_movti_32bit): Likewise.
	* config/rs6000/constraints.md (wO constraint): New constraint for
	ISA 3.0 vector d-form support.
	* config/rs6000/rs6000-cpus.def (ISA_3_0_MASKS_SERVER): Use
	-mpower9-dform-scalar instead of -mpower9-dform.  Add note not to
	include -mpower9-dform-vector until we switch over to LRA.
	(POWERPC_MASKS): Add -mlra. Split -mpower9-dform into two. 
	switches, -mpower9-dform-scalar and -mpower9-dform-vector.
	* config/rs6000/rs6000-protos.h (quad_address_p): Add declaration.
	* doc/invoke.texi (RS/6000 and PowerPC Options): Add documentation
	for -mpower9-dform and -mlra.
	* doc/md.texi (wO constraint): Document wO constraint.

[gcc/testsuite]
2016-05-11  Michael Meissner  <meissner@linux.vnet.ibm.com>

	* gcc.target/powerpc/dform-3.c: New test for ISA 3.0 vector d-form
	support.
	* gcc.target/powerpc/dform-1.c: Add -mlra option to silence
	warning when using -mvsx-timode.
	* gcc.target/powerpc/p8vector-int128-1.c: Likewise.
	* gcc.target/powerpc/dform-2.c: Likewise.
	* gcc.target/powerpc/pr68805.c: Likewise.

From-SVN: r236133
parent d8aecc55
Showing with 203 additions and 76 deletions
gcc/ChangeLog
2016-05-11 Michael Meissner <meissner@linux.vnet.ibm.com>
* config/rs6000/predicates.md (quad_memory_operand): Move most of
the code into quad_address_p and call it to share code with
vsx_quad_dform_memory_operand.
(vsx_quad_dform_memory_operand): New predicate for ISA 3.0 vector
d-form support.
* config/rs6000/rs6000.opt (-mlra): Switch to being an option mask
bit instead of being a separate word. Split -mpower9-dform into
two switches, -mpower9-dform-scalar and -mpower9-dform-vector.
* config/rs6000/rs6000.c (RELOAD_REG_QUAD_OFFSET): New addr_mask
for the register class supporting 128-bit quad word memory
offsets.
(mode_supports_vsx_dform_quad): Helper function to return if the
register class uses quad word memory offsets.
(rs6000_debug_addr_mask): Add support for quad word memory
offsets.
(rs6000_debug_reg_global): Always print if we are using LRA or
not.
(rs6000_setup_reg_addr_masks): If ISA 3.0 vector d-form
instructions are enabled, set up the appropriate addr_masks for
128-bit types.
(rs6000_init_hard_regno_mode_ok): wb constraint is now based on
-mpower9-dform-scalar, instead of -mpower9-dform.
(rs6000_option_override_internal): Split -mpower9-dform into two
switches, -mpower9-dform-scalar and -mpower9-dform-vector. The
-mpower9-dform switch sets or clears both. If we are not using
the LRA register allocator, do not enable -mpower9-dform-vector by
default. If we are using LRA, enable -mpower9-dform-vector and
-mvsx-timode if it is appropriate. Issue a warning if either
-mpower9-dform-vector or -mvsx-timode are explicitly used without
enabling LRA.
(quad_address_offset_p): New helper function to return if the
offset is legal for quad word memory instructions.
(quad_address_p): New function to determin if GPR or vector
register quad word memory addresses are legal.
(mem_operand_gpr): Validate quad word address offsets.
(reg_offset_addressing_ok_p): Add support for ISA 3.0 vector
d-form (register + offset) instructions.
(offsettable_ok_by_alignment): Likewise.
(rs6000_legitimate_offset_address_p): Likewise.
(legitimate_lo_sum_address_p): Likewise.
(rs6000_legitimize_address): Likewise.
(rs6000_legitimize_reload_address): Add more debug statements for
-mdebug=addr.
(rs6000_legitimate_address_p): Add support for ISA 3.0 vector
d-form instructions.
(rs6000_secondary_reload_memory): Add support for ISA 3.0 vector
d-form instructions. Distinguish different cases in debug
output. (rs6000_secondary_reload_inner): Add support for ISA 3.0 vector
d-form instructions.
(rs6000_preferred_reload_class): Likewise.
(rs6000_output_move_128bit): Add support for ISA 3.0 d-form
instructions. If ISA 3.0 is available, generate lxvx/stxvx instead
of the ISA 2.06 indexed memory instructions.
(rs6000_emit_prologue): If we have ISA 3.0 d-form instructions,
use them to save/restore the saved vector registers instead of
using Altivec instructions.
(rs6000_emit_epilogue): Likewise.
(rs6000_lra_p): Use TARGET_LRA instead of the old option word.
(rs6000_opt_masks): Split -mpower9-dform into
-mpower9-dform-scalar and -mpower9-dform-vector.
(rs6000_print_options_internal): Print -mno-<switch> if <switch>
was not selected.
* config/rs6000/vsx.md (p9_vecload_<mode>): Delete hack to emit
ISA 3.0 vector indexed memory instructions, and fold the code into
the normal mov<mode> patterns.
(p9_vecstore_<mode>): Likewise.
(vsx_mov<mode>): Add support for ISA 3.0 vector d-form
instructions.
(vsx_movti_64bit): Likewise.
(vsx_movti_32bit): Likewise.
* config/rs6000/constraints.md (wO constraint): New constraint for
ISA 3.0 vector d-form support.
* config/rs6000/rs6000-cpus.def (ISA_3_0_MASKS_SERVER): Use
-mpower9-dform-scalar instead of -mpower9-dform. Add note not to
include -mpower9-dform-vector until we switch over to LRA.
(POWERPC_MASKS): Add -mlra. Split -mpower9-dform into two.
switches, -mpower9-dform-scalar and -mpower9-dform-vector.
* config/rs6000/rs6000-protos.h (quad_address_p): Add declaration.
* doc/invoke.texi (RS/6000 and PowerPC Options): Add documentation
for -mpower9-dform and -mlra.
* doc/md.texi (wO constraint): Document wO constraint.
2016-05-11 Alexander Monakov <amonakov@ispras.ru>
* genattr.c (main): Change 'rtx' to 'rtx_insn *' in prototypes of
......
gcc/config/rs6000/constraints.md
......@@ -156,6 +156,11 @@
(and (match_test "TARGET_DIRECT_MOVE_128")
(match_test "(ival == VECTOR_ELEMENT_MFVSRLD_64BIT)"))))
;; ISA 3.0 vector d-form addresses
(define_memory_constraint "wO"
"Memory operand suitable for the ISA 3.0 vector d-form instructions."
(match_operand 0 "vsx_quad_dform_memory_operand"))
;; Lq/stq validates the address for load/store quad
(define_memory_constraint "wQ"
"Memory operand suitable for the load/store quad instructions"
......
gcc/config/rs6000/predicates.md
......@@ -691,48 +691,25 @@
(define_predicate "quad_memory_operand"
(match_code "mem")
{
rtx addr, op0, op1;
int ret;
if (!TARGET_QUAD_MEMORY && !TARGET_SYNC_TI)
ret = 0;
else if (!memory_operand (op, mode))
ret = 0;
else if (GET_MODE_SIZE (GET_MODE (op)) != 16)
ret = 0;
else if (MEM_ALIGN (op) < 128)
ret = 0;
else
{
addr = XEXP (op, 0);
if (int_reg_operand (addr, Pmode))
ret = 1;
return false;
else if (GET_CODE (addr) != PLUS)
ret = 0;
if (GET_MODE_SIZE (mode) != 16 || !MEM_P (op) || MEM_ALIGN (op) < 128)
return false;
else
{
op0 = XEXP (addr, 0);
op1 = XEXP (addr, 1);
ret = (int_reg_operand (op0, Pmode)
&& GET_CODE (op1) == CONST_INT
&& IN_RANGE (INTVAL (op1), -32768, 32767)
&& (INTVAL (op1) & 15) == 0);
}
}
return quad_address_p (XEXP (op, 0), mode, true);
})
if (TARGET_DEBUG_ADDR)
{
fprintf (stderr, "\nquad_memory_operand, ret = %s\n", ret ? "true" : "false");
debug_rtx (op);
}
;; Return 1 if the operand is suitable for load/store to vector registers with
;; d-form addressing (register+offset), which was added in ISA 3.0.
;; Unlike quad_memory_operand, we do not have to check for alignment.
(define_predicate "vsx_quad_dform_memory_operand"
(match_code "mem")
{
if (!TARGET_P9_DFORM_VECTOR || !MEM_P (op) || GET_MODE_SIZE (mode) != 16)
return false;
return ret;
return quad_address_p (XEXP (op, 0), mode, false);
})
;; Return 1 if the operand is an indexed or indirect memory operand.
......
gcc/config/rs6000/rs6000-cpus.def
......@@ -60,13 +60,14 @@
| OPTION_MASK_UPPER_REGS_SF)
/* Add ISEL back into ISA 3.0, since it is supposed to be a win. Do not add
P9_DFORM or P9_MINMAX until they are fully debugged. */
P9_MINMAX until the hardware that supports it is available. Do not add
P9_DFORM_VECTOR until LRA is the default register allocator. */
#define ISA_3_0_MASKS_SERVER (ISA_2_7_MASKS_SERVER \
| OPTION_MASK_FLOAT128_HW \
| OPTION_MASK_ISEL \
| OPTION_MASK_MODULO \
| OPTION_MASK_P9_FUSION \
| OPTION_MASK_P9_DFORM \
| OPTION_MASK_P9_DFORM_SCALAR \
| OPTION_MASK_P9_VECTOR)
#define POWERPC_7400_MASK (OPTION_MASK_PPC_GFXOPT | OPTION_MASK_ALTIVEC)
......@@ -94,6 +95,7 @@
| OPTION_MASK_FPRND \
| OPTION_MASK_HTM \
| OPTION_MASK_ISEL \
| OPTION_MASK_LRA \
| OPTION_MASK_MFCRF \
| OPTION_MASK_MFPGPR \
| OPTION_MASK_MODULO \
......@@ -101,7 +103,8 @@
| OPTION_MASK_NO_UPDATE \
| OPTION_MASK_P8_FUSION \
| OPTION_MASK_P8_VECTOR \
| OPTION_MASK_P9_DFORM \
| OPTION_MASK_P9_DFORM_SCALAR \
| OPTION_MASK_P9_DFORM_VECTOR \
| OPTION_MASK_P9_FUSION \
| OPTION_MASK_P9_MINMAX \
| OPTION_MASK_P9_VECTOR \
......
gcc/config/rs6000/rs6000-protos.h
......@@ -86,6 +86,7 @@ extern int registers_ok_for_quad_peep (rtx, rtx);
extern int mems_ok_for_quad_peep (rtx, rtx);
extern bool gpr_or_gpr_p (rtx, rtx);
extern bool direct_move_p (rtx, rtx);
extern bool quad_address_p (rtx, machine_mode, bool);
extern bool quad_load_store_p (rtx, rtx);
extern bool fusion_gpr_load_p (rtx, rtx, rtx, rtx);
extern void expand_fusion_gpr_load (rtx *);
......
gcc/config/rs6000/rs6000.opt
......@@ -470,8 +470,8 @@ Target RejectNegative Joined UInteger Var(rs6000_long_double_type_size) Save
-mlong-double-<n> Specify size of long double (64 or 128 bits).
mlra
Target Report Var(rs6000_lra_flag) Init(0) Save
Use LRA instead of reload.
Target Report Mask(LRA) Var(rs6000_isa_flags)
Enable Local Register Allocation.
msched-costly-dep=
Target RejectNegative Joined Var(rs6000_sched_costly_dep_str)
......@@ -609,9 +609,17 @@ mpower9-vector
Target Report Mask(P9_VECTOR) Var(rs6000_isa_flags)
Use/do not use vector and scalar instructions added in ISA 3.0.
mpower9-dform-scalar
Target Undocumented Mask(P9_DFORM_SCALAR) Var(rs6000_isa_flags)
Use/do not use scalar register+offset memory instructions added in ISA 3.0.
mpower9-dform-vector
Target Undocumented Mask(P9_DFORM_VECTOR) Var(rs6000_isa_flags)
Use/do not use vector register+offset memory instructions added in ISA 3.0.
mpower9-dform
Target Undocumented Mask(P9_DFORM) Var(rs6000_isa_flags)
Use/do not use vector and scalar instructions added in ISA 3.0.
Target Report Var(TARGET_P9_DFORM_BOTH) Init(-1) Save
Use/do not use register+offset memory instructions added in ISA 3.0.
mpower9-minmax
Target Undocumented Mask(P9_MINMAX) Var(rs6000_isa_flags)
......
gcc/config/rs6000/vsx.md
......@@ -301,24 +301,6 @@
UNSPEC_VSX_XVCVDPUXDS
])
;; VSX (P9) moves
(define_insn "*p9_vecload_<mode>"
[(set (match_operand:VSX_M2 0 "vsx_register_operand" "=<VSa>")
(match_operand:VSX_M2 1 "memory_operand" "Z"))]
"TARGET_P9_VECTOR"
"lxvx %x0,%y1"
[(set_attr "type" "vecload")
(set_attr "length" "4")])
(define_insn "*p9_vecstore_<mode>"
[(set (match_operand:VSX_M2 0 "memory_operand" "=Z")
(match_operand:VSX_M2 1 "vsx_register_operand" "<VSa>"))]
"TARGET_P9_VECTOR"
"stxvx %x1,%y0"
[(set_attr "type" "vecstore")
(set_attr "length" "4")])
;; VSX moves
;; The patterns for LE permuted loads and stores come before the general
......@@ -788,8 +770,8 @@
"")
(define_insn "*vsx_mov<mode>"
[(set (match_operand:VSX_M 0 "nonimmediate_operand" "=Z,<VSr>,<VSr>,?Z,?<VSa>,?<VSa>,r,we,wQ,?&r,??Y,??r,??r,<VSr>,?<VSa>,*r,v,wZ,v")
(match_operand:VSX_M 1 "input_operand" "<VSr>,Z,<VSr>,<VSa>,Z,<VSa>,we,b,r,wQ,r,Y,r,j,j,j,W,v,wZ"))]
[(set (match_operand:VSX_M 0 "nonimmediate_operand" "=ZwO,<VSr>,<VSr>,?ZwO,?<VSa>,?<VSa>,r,we,wQ,?&r,??Y,??r,??r,<VSr>,?<VSa>,*r,v,wZ,v")
(match_operand:VSX_M 1 "input_operand" "<VSr>,ZwO,<VSr>,<VSa>,ZwO,<VSa>,we,b,r,wQ,r,Y,r,j,j,j,W,v,wZ"))]
"VECTOR_MEM_VSX_P (<MODE>mode)
&& (register_operand (operands[0], <MODE>mode)
|| register_operand (operands[1], <MODE>mode))"
......@@ -803,8 +785,8 @@
;; use of TImode is for unions. However for plain data movement, slightly
;; favor the vector loads
(define_insn "*vsx_movti_64bit"
[(set (match_operand:TI 0 "nonimmediate_operand" "=Z,wa,wa,wa,r,we,v,v,wZ,wQ,&r,Y,r,r,?r")
(match_operand:TI 1 "input_operand" "wa,Z,wa,O,we,b,W,wZ,v,r,wQ,r,Y,r,n"))]
[(set (match_operand:TI 0 "nonimmediate_operand" "=ZwO,wa,wa,wa,r,we,v,v,wZ,wQ,&r,Y,r,r,?r")
(match_operand:TI 1 "input_operand" "wa,ZwO,wa,O,we,b,W,wZ,v,r,wQ,r,Y,r,n"))]
"TARGET_POWERPC64 && VECTOR_MEM_VSX_P (TImode)
&& (register_operand (operands[0], TImode)
|| register_operand (operands[1], TImode))"
......@@ -815,8 +797,8 @@
(set_attr "length" "4,4,4,4,8,4,16,4,4,8,8,8,8,8,8")])
(define_insn "*vsx_movti_32bit"
[(set (match_operand:TI 0 "nonimmediate_operand" "=Z,wa,wa,wa,v, v,wZ,Q,Y,????r,????r,????r,r")
(match_operand:TI 1 "input_operand" "wa, Z,wa, O,W,wZ, v,r,r, Q, Y, r,n"))]
[(set (match_operand:TI 0 "nonimmediate_operand" "=ZwO,wa,wa,wa,v,v,wZ,Q,Y,????r,????r,????r,r")
(match_operand:TI 1 "input_operand" "wa,ZwO,wa,O,W,wZ,v,r,r,Q,Y,r,n"))]
"! TARGET_POWERPC64 && VECTOR_MEM_VSX_P (TImode)
&& (register_operand (operands[0], TImode)
|| register_operand (operands[1], TImode))"
......
gcc/doc/invoke.texi
......@@ -1006,7 +1006,8 @@ See RS/6000 and PowerPC Options.
-mupper-regs-df -mno-upper-regs-df -mupper-regs-sf -mno-upper-regs-sf @gol
-mupper-regs -mno-upper-regs -mmodulo -mno-modulo @gol
-mfloat128 -mno-float128 -mfloat128-hardware -mno-float128-hardware @gol
-mpower9-fusion -mno-mpower9-fusion -mpower9-vector -mno-power9-vector}
-mpower9-fusion -mno-mpower9-fusion -mpower9-vector -mno-power9-vector @gol
-mpower9-dform -mno-power9-dform -mlra -mno-lra}
@emph{RX Options}
@gccoptlist{-m64bit-doubles -m32bit-doubles -fpu -nofpu@gol
......@@ -13702,7 +13703,6 @@ Enable the use of indexed loads. This can be problematic because some
optimizers then assume that indexed stores exist, which is not
the case.
@item -mlra
@opindex mlra
Enable Local Register Allocation. This is still experimental for ARC,
so by default the compiler uses standard reload
......@@ -19928,7 +19928,7 @@ following options:
-msimple-fpu -mstring -mmulhw -mdlmzb -mmfpgpr -mvsx @gol
-mcrypto -mdirect-move -mpower8-fusion -mpower8-vector @gol
-mquad-memory -mquad-memory-atomic -mmodulo -mfloat128 -mfloat128-hardware @gol
-mpower9-fusion -mpower9-vector}
-mpower9-fusion -mpower9-vector -mpower9-dform}
The particular options set for any particular CPU varies between
compiler versions, depending on what setting seems to produce optimal
......@@ -20052,6 +20052,12 @@ This switch enables or disables the generation of ISEL instructions.
This switch has been deprecated. Use @option{-misel} and
@option{-mno-isel} instead.
@item -mlra
@opindex mlra
Enable Local Register Allocation. This is still experimental for PowerPC,
so by default the compiler uses standard reload
(i.e. @option{-mno-lra}).
@item -mspe
@itemx -mno-spe
@opindex mspe
......@@ -20201,10 +20207,19 @@ processors.
@opindex mpower9-vector
@opindex mno-power9-vector
Generate code that uses (does not use) the vector and scalar
instructions that were added in version 2.07 of the PowerPC ISA. Also
instructions that were added in version 3.0 of the PowerPC ISA. Also
enable the use of built-in functions that allow more direct access to
the vector instructions.
@item -mpower9-dform
@itemx -mno-power9-dform
@opindex mpower9-dform
@opindex mno-power9-dform
Enable (disable) scalar d-form (register + offset) memory instructions
to load/store traditional Altivec registers. If the @var{LRA} register
allocator is enabled, also enable (disable) vector d-form memory
instructions.
@item -mfloat-gprs=@var{yes/single/double/no}
@itemx -mfloat-gprs
@opindex mfloat-gprs
......
gcc/doc/md.texi
......@@ -3224,6 +3224,9 @@ Memory operand suitable for TOC fusion memory references.
Int constant that is the element number that the MFVSRLD instruction
targets.
@item wO
A memory operand suitable for the ISA 3.0 vector d-form instructions.
@item wQ
A memory address that will work with the @code{lq} and @code{stq}
instructions.
......
gcc/testsuite/ChangeLog
2016-05-11 Michael Meissner <meissner@linux.vnet.ibm.com>
* gcc.target/powerpc/dform-3.c: New test for ISA 3.0 vector d-form
support.
* gcc.target/powerpc/dform-1.c: Add -mlra option to silence
warning when using -mvsx-timode.
* gcc.target/powerpc/p8vector-int128-1.c: Likewise.
* gcc.target/powerpc/dform-2.c: Likewise.
* gcc.target/powerpc/pr68805.c: Likewise.
2016-05-11 Marek Polacek <polacek@redhat.com>
PR c++/71024
......
gcc/testsuite/gcc.target/powerpc/dform-1.c
/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
/* { dg-options "-mcpu=power9 -mpower9-dform -O2" } */
/* { dg-options "-mcpu=power9 -mpower9-dform -O2 -mlra" } */
#ifndef TYPE
#define TYPE double
......
gcc/testsuite/gcc.target/powerpc/dform-2.c
/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
/* { dg-options "-mcpu=power9 -mpower9-dform -O2" } */
/* { dg-options "-mcpu=power9 -mpower9-dform -O2 -mlra" } */
#ifndef TYPE
#define TYPE float
......
gcc/testsuite/gcc.target/powerpc/dform-3.c 0 → 100644
/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
/* { dg-options "-mcpu=power9 -mpower9-dform -O2 -mlra" } */
#ifndef TYPE
#define TYPE vector double
#endif
struct foo {
TYPE a, b, c, d;
};
/* Test whether ISA 3.0 vector d-form instructions are implemented. */
void
add (struct foo *p)
{
p->b = p->c + p->d;
}
/* Make sure we don't use direct moves to get stuff into GPR registers. */
void
gpr (struct foo *p)
{
TYPE x = p->c;
__asm__ (" # reg = %0" : "+r" (x));
p->b = x;
}
/* { dg-final { scan-assembler "lxv " } } */
/* { dg-final { scan-assembler "stxv " } } */
/* { dg-final { scan-assembler-not "lxvx " } } */
/* { dg-final { scan-assembler-not "stxvx " } } */
/* { dg-final { scan-assembler-not "mfvsrd " } } */
/* { dg-final { scan-assembler-not "mfvsrld " } } */
/* { dg-final { scan-assembler "l\[dq\] " } } */
/* { dg-final { scan-assembler "st\[dq\] " } } */
gcc/testsuite/gcc.target/powerpc/p8vector-int128-1.c
......@@ -2,7 +2,7 @@
/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
/* { dg-require-effective-target powerpc_p8vector_ok } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
/* { dg-options "-mcpu=power8 -O3 -mvsx-timode" } */
/* { dg-options "-mcpu=power8 -O3 -mvsx-timode -mlra" } */
#include <altivec.h>
......
gcc/testsuite/gcc.target/powerpc/pr68805.c
/* { dg-do compile { target powerpc64le-*-* } } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
/* { dg-options "-O2 -mvsx-timode -mcpu=power8" } */
/* { dg-options "-O2 -mvsx-timode -mcpu=power8 -mlra" } */
typedef struct bar {
void *a;
......
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