* varasm.c (bss_initializer_p): Do not put constants into .bss
	(categorize_decl_for_section): Handle bss_initializer_p returning
	false when DECL_INITIAL is NULL.

	* gcc.target/i386/const-in-bss.c: New test.

From-SVN: r251602

TARGET_CAN_INLINE_P must be implemented when supporting target
attributes.

gcc/ChangeLog:

2017-09-01  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>

	PR target/82012
	* config/s390/s390.c (s390_can_inline_p): New function.

gcc/testsuite/ChangeLog:

2017-09-01  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>

	PR target/82012
	* gcc.target/s390/target-attribute/pr82012.c: New test.

From-SVN: r251601

re PR tree-optimization/82052 (ICE with "-O3 -m32" on x86_64-linux-gnu (internal compiler error: in pop_to_marker, at tree-ssa-scopedtables.c:71))

	PR tree-optimization/82052
	* tree-ssa-scopedtables.c (avail_exprs_stack::lookup_avail_expr):
	Always initialize the returned slot after a hash table miss
	when INSERT is true.

	PR tree-optimization/82052
	* gcc.c-torture/compile/pr82052.c: New test.

From-SVN: r251600

	* config/s390/s390.md (mem_signal_fence): Remove.
	* doc/md.texi (mem_signal_fence): Remove.
	* optabs.c (expand_mem_signal_fence): Remove uses of mem_signal_fence.
	Update comments.
	* target-insns.def (mem_signal_fence): Remove.

From-SVN: r251597

	PR sanitizer/81902
	* doc/invoke.texi: Document -fsanitize=pointer-overflow.

From-SVN: r251596

	PR sanitizer/81923
	* asan.c (create_odr_indicator): Strip name encoding from assembler
	name before appending it after __odr_asan_.

	* gcc.dg/asan/pr81923.c: New test.

From-SVN: r251595

2017-09-01  Olivier Hainque  <hainque@adacore.com>

	libgcc/
	* config.host (*-*-vxworks7): Widen scope to vxworks7*.

From-SVN: r251594

	Revert 2017-08-28  Nathan Sidwell  <nathan@acm.org>
	Restore sorted_fields vector.
	* cp-tree.h (lang_type): Restore sorted_fields vector.
	(CLASSTYPE_SORTED_FIELDS): Restore.
	(CLASSTYPE_BINDINGS): Delete.
	* name-lookup.c (lookup_field_1): Restore binary search.
	(sorted_fields_type_new, count_fields,
	add_fields_to_record_type, add_enum_fields_to_record_type): Restore
	(set_class_bindings): Revert.
	(insert_late_enum_def_binding): Restore field_vec insertion.

From-SVN: r251592

2017-09-01  Martin Liska  <mliska@suse.cz>

	PR tree-optimization/82059
	* gimple-ssa-isolate-paths.c (isolate_path): Add profile and
	frequency only when an edge is redirected.
2017-09-01  Martin Liska  <mliska@suse.cz>

	PR tree-optimization/82059
	* gcc.dg/tree-ssa/pr82059.c: New test.

From-SVN: r251591

2017-05-22  Claudiu Zissulescu <claziss@synopsys.com>

	* config/arc/arc-c.c (__ARC_LPC_WIDTH__): Add builtin define.
	* config/arc/arc.c (ARC_MAX_LOOP_LENGTH): Define.
	(arc_conditional_register_usage): Remove ARC600 lp_count
	exception.
	(arc_file_start): Emit Tag_ARC_CPU_variation.
	(arc_can_use_doloop_p): New conditions to use ZOLs.
	(hwloop_fail): New function.
	(hwloop_optimize): Likewise.
	(hwloop_pattern_reg): Likewise.
	(arc_doloop_hooks): New struct, to be used with reorg_loops.
	(arc_reorg_loops): New function, calls reorg_loops.
	(arc_reorg): Call arc_reorg_loops.  Remove old ZOL handling.
	(arc600_corereg_hazard): Remove ZOL checking, case handled by
	hwloop_optimize.
	(arc_loop_hazard): Remove function, functionality moved into
	hwloop_optimize.
	(arc_hazard): Remove arc_loop_hazard call.
	(arc_adjust_insn_length): Remove ZOL handling, functionality moved
	into hwloop_optimize.
	(arc_label_align): Remove ZOL handling.
	* config/arc/arc.h (LOOP_ALIGN): Changed to 0.
	* config/arc/arc.md (doloop_begin): Remove pattern.
	(doloop_begin_i): Likewise.
	(doloop_end_i): Likewise.
	(doloop_fallback): Likewise.
	(doloop_fallback_m): Likewise.
	(doloop_end): Reimplement expand.
	(arc_lp): New pattern for LP instruction.
	(loop_end): New pattern.
	(loop_fail): Likewise.
	(decrement_and_branch_until_zero): Likewise.
	* config/arc/arc.opt (mlpc-width): New option.
	* doc/invoke.texi (mlpc-width): Document option.

testsuite/
2017-05-22  Claudiu Zissulescu <claziss@synopsys.com>

 	    * gcc.target/arc/loop-1.c: Deleted.

From-SVN: r251589

The arc_ifcvt procedure is removing a label even when it is used by
another jump.  This patch fixes dg.exp/pr31507-1.c.

gcc/
2017-07-10  Claudiu Zissulescu  <claziss@synopsys.com>

	* config/arc/arc.c (arc_ifcvt): Remove use of merge_blocks call.
	(arc_ccfsm_advance): Fix checking for delay slots.
	(arc_reorg): Add rtl dump after each call to arc_ifcvt

From-SVN: r251588

gcc/
2017-04-25  Claudiu Zissulescu  <claziss@synopsys.com>

	* config/arc/arc.md (movqi_insn): Add stores to save constant long
	immediates.
	(movhi_insn): Update store instruction constraint which are saving
	6-bit short immediates.
	(movsi_insn): Consider also short scaled load operations.
	(zero_extendhisi2_i): Use Usd constraint instead of T.
	(extendhisi2_i): Add q constraint.
	(arc_clzsi2): Add type and length attributes.
	(arc_ctzsi2): Likewise.
	* config/arc/constraints.md (Usc): Update constraint, the
	assembler can parse two relocations for a single instruction.

gcc/testsuite/
2017-04-25  Claudiu Zissulescu  <claziss@synopsys.com>

	* gcc.target/arc/arc.exp: Test also cpp files.
	* gcc.target/arc/tdelay_slots.cpp: New test.

From-SVN: r251587

We don't want to use anchors for small data: the GP register acts as an anchor in that
case.  We also don't want to use them for PC-relative accesses,
where the PC acts as an anchor.  TLS symbols require special accesses as well, don't use
anchors for such symbols.

gcc/
2017-04-28  Claudiu Zissulescu  <claziss@synopsys.com>

	* config/arc/arc.c (arc_use_anchors_for_symbol_p): New function.
	(TARGET_USE_ANCHORS_FOR_SYMBOL_P): Define.

gcc/testsuite
2017-04-28  Claudiu Zissulescu  <claziss@synopsys.com>

	* gcc.target/arc/pr9001184797.c: New test.

From-SVN: r251586

	PR c/81887
c-family/
	* c-pragma.c (omp_pragmas): Move "ordered" entry from here to ...
	(omp_pragmas_simd): ... here.
	* c-omp.c (c_finish_omp_ordered): If clauses isn't simd clause alone,
	create new clauses list containing just simd clause.
c/
	* c-parser.c (c_parser_omp_ordered): Handle -fopenmp-simd.
cp/
	* parser.c (cp_parser_omp_ordered): Handle -fopenmp-simd.
fortran/
	* parse.c (decode_omp_directive): Use matchs instead of matcho for
	end ordered and ordered directives, except for ordered depend.  For
	-fopenmp-simd and ordered depend, reject the stmt.
	* trans-openmp.c (gfc_trans_omp_ordered): For -fopenmp-simd ignore
	threads clause and if simd clause isn't present, just translate the
	body.
testsuite/
	* c-c++-common/gomp/pr81887.c: New test.
	* gfortran.dg/gomp/pr81887.f90: New test.

From-SVN: r251585

2017-09-01  Martin Liska  <mliska@suse.cz>

	* simple-object-elf.c (simple_object_elf_copy_lto_debug_sections):
	Remove duplicite declaration.

From-SVN: r251584

	PR c++/82040
	* typeck.c (cp_build_unary_op): Avoid re-entering reporting routines.

	* g++.dg/warn/Wbool-operation-1.C: New test.

From-SVN: r251581

From-SVN: r251580

    
    Patch by Rainer Orth.
    
    Reviewed-on: https://go-review.googlesource.com/60732

From-SVN: r251574

2017-08-31  Olivier Hainque  <hainque@adacore.com>

       gcc/
       * config.gcc (powerpc-wrs-vxworks|vxworksae|vxworksmils): Now
	match as powerpc-wrs-vxworks*.

       libgcc/
       * config.host: Likewise.

From-SVN: r251573

	PR c++/82039
	* include/ext/new_allocator.h (__gnu_cxx::new_allocator::allocate):
	Adjust null pointer constant to avoid warning.

From-SVN: r251570

The MLA by-element instructions have the same restriction as other by-element
instructions whereby the forms operating on vectors of 16-bit integer data
may only use registers v0-v15. We have an iterator for that, applied to the
other patterns generating this instruction, so use that.

gcc/

	* config/aarch64/aarch64-simd.md (aarch64_mla_elt_merge<mode>): Fix
	register constraint for by-element operand.
	(aarch64_mls_elt_merge<mode>): Likewise.

From-SVN: r251568

	* pt.c (enclosing_instantiation_of, lambda_fn_in_template_p)
	(regenerated_lambda_fn_p): New.
	(tsubst_decl) [VAR_DECL]: Use enclosing_instantiation_of.
	(tsubst_copy) [VAR_DECL]: Likewise.

From-SVN: r251567

Short branches cannot be used to jump between hot/cold
sections. Update the hook.

gcc/
2017-04-26  Claudiu Zissulescu  <claziss@synopsys.com>

	* config/arc/arc.c (arc_can_follow_jump): Check for short
	branches.

From-SVN: r251566

gcc/
2017-04-24  Claudiu Zissulescu  <claziss@synopsys.com>

	* config.gcc: Use g.opt for arc.
	* config/arc/arc.c (LEGITIMATE_SCALED_ADDRESS_P): Deleted,
	functionality moved to ...
	(legitimate_scaled_address_p): New function, ...here.
	(LEGITIMATE_SMALL_DATA_OFFSET_P): New define.
	(LEGITIMATE_SMALL_DATA_ADDRESS_P): Use the above define.
	(legitimate_offset_address_p): Delete TARGET_NO_SDATA_SET
	condition.
	(arc_override_options): Handle G option.
	(arc_output_pic_addr_const): Correct function definition.
	(arc_legitimate_address_p): Use legitimate_scaled_address_p.
	(arc_decl_anon_ns_mem_p): Delete.
	(arc_in_small_data_p): Overhaul this function to take into
	consideration the value given via G option.
	(arc_rewrite_small_data_1): Renamed and corrected old
	arc_rewrite_small_data function.
	(arc_rewrite_small_data): New function.
	(small_data_pattern): Don't use pic_offset_table_rtx.
	* config/arc/arc.h (CC1_SPEC): Recognize G option.
	* config/arc/simdext.md (movmisalignv2hi): Use
	prepare_move_operands function.
	(mov*): Likewise.
	(movmisalign*): Likewise.

gcc/testsuite/
2017-04-24  Claudiu Zissulescu  <claziss@synopsys.com>

	* gcc.target/arc/sdata-5.c: New test.
	* gcc.target/arc/arc700-stld-hazard.c: Update test options.

Fix test

From-SVN: r251564

Add alignment check for short load/store instructions used for sdata,
as they request 32-bit aligned short immediate.  Use sdata symbol
alignment information and emit scalled loads/stores whenever is
possible. The scalled address will extend the access range for sdata
symbols.  Allow 64-bit datum into small data section, if double
load/store instructions are present.

gcc/
2017-04-12  Claudiu Zissulescu  <claziss@synopsys.com>

	* config/arc/arc-protos.h (compact_sda_memory_operand): Update
	prototype.
	* config/arc/arc.c (arc_print_operand): Output scalled address for
	sdata whenever is possible.
	(arc_in_small_data_p): Allow sdata for 64bit datum when double
	load/stores are available.
	(compact_sda_memory_operand): Check for the alignment required by
	code density instructions.
	* config/arc/arc.md (movsi_insn): Use newly introduced Us0
	constraint.
	* config/arc/constraints.md (Usd): Update constraint.
	(Us0): New constraint.
	(Usc): Update constraint.

gcc/testsuite/
2017-04-12  Claudiu Zissulescu  <claziss@synopsys.com>

	* gcc.target/arc/sdata-3.c: New file.

From-SVN: r251562

2017-08-31  Richard Biener  <rguenther@suse.de>

	PR lto/81968
	* simple-object-elf.c (simple_object_elf_copy_lto_debug_section):
	Keep names of removed global symbols.

From-SVN: r251560

2017-08-31  Richard Biener  <rguenther@suse.de>

	PR middle-end/82054
	* dwarf2out.c (dwarf2out_early_global_decl): Process each
	function only once.

	* g++.dg/gomp/pr82054.C: New testcase.

From-SVN: r251559

2017-08-31  Tamar Christina  <tamar.christina@arm.com>

	* config/aarch64/aarch64-builtins.c (aarch64_init_simd_builtins):
	Resize type_signature.

From-SVN: r251558

Previously we allowed subregs of non-GPR modes to be base and index
registers in non-strict mode.  In practice such subregs will always
require a reload, so we get better code by disallowing them.

2017-08-31  Richard Sandiford  <richard.sandiford@linaro.org>
	    Alan Hayward  <alan.hayward@arm.com>
	    David Sherwood  <david.sherwood@arm.com>

gcc/
	* config/aarch64/aarch64.c (aarch64_base_register_rtx_p): Only allow
	subregs whose inner modes can be stored in GPRs.
	(aarch64_classify_index): Likewise.

Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>

From-SVN: r251557

The comparison results provided by the V_cmp_result/v_cmp_result
attribute were simply the corresponding integer vector.  We'd also
like to have easy access to the integer vector for SVE, but using
"cmp_result" would be confusing because SVE comparisons return
predicates instead of vectors.  This patch therefore renames the
attributes to the more general V_INT_EQUIV/v_int_equiv instead.

As to the capitalisation: there are already many iterators that use
all lowercase vs. all uppercase names to distinguish all lowercase
vs. all uppercase expansions (e.g. fcvt_target and FCVT_TARGET).
It's also the convention used for the built-in mode/MODE/code/CODE/etc.
attributes.  IMO those names are easier to read at a glance, rather than
relying on a single letter's difference.

2017-08-22  Richard Sandiford  <richard.sandiford@linaro.org>
	    Alan Hayward  <alan.hayward@arm.com>
	    David Sherwood  <david.sherwood@arm.com>

gcc/
	* config/aarch64/iterators.md (V_cmp_result): Rename to...
	(V_INT_EQUIV): ...this.
	(v_cmp_result): Rename to...
	(v_int_equiv): ...this.
	* config/aarch64/aarch64.md (xorsign<mode>3): Update accordingly.
	* config/aarch64/aarch64-simd.md (xorsign<mode>3): Likewise.
	(copysign<mode>3): Likewise.
	(aarch64_simd_bsl<mode>_internal): Likewise.
	(aarch64_simd_bsl<mode>): Likewise.
	(vec_cmp<mode><mode>): Likewise.
	(vcond<mode><mode>): Likewise.
	(vcond<v_cmp_mixed><mode>): Likewise.
	(vcondu<mode><v_cmp_mixed>): Likewise.
	(aarch64_cm<optab><mode>): Likewise.
	(aarch64_cmtst<mode>): Likewise.
	(aarch64_fac<optab><mode>): Likewise.
	(vec_perm_const<mode>): Likewise.
	(vcond_mask_<mode><v_cmp_result>): Rename to...
	(vcond_mask_<mode><v_int_equiv>): ...this.
	(vec_cmp<mode><v_cmp_result>): Rename to...
	(vec_cmp<mode><v_int_equiv>): ...this.

Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>

From-SVN: r251556

The AArch64 port defined x2, x3 and x4 vector modes that were only used
in the rtl for the AdvSIMD LD{2,3,4} patterns.  It seems unlikely that
this rtl would have led to any valid simplifications, since the values
involved were unspecs that had a different number of operands from the
non-dreg versions.  (The dreg UNSPEC_LD2 had a single operand, while
the qreg one had two operands.)

As it happened, the patterns led to invalid simplifications on big-
endian targets due to a mix-up in the operand order, see Tamar's fix
in r240271.

This patch therefore replaces the rtl patterns with dedicated unspecs.
This allows the x2, x3 and x4 modes to be removed, avoiding a clash
with 256-bit and 512-bit SVE.

2017-08-22  Richard Sandiford  <richard.sandiford@linaro.org>
	    Alan Hayward  <alan.hayward@arm.com>
	    David Sherwood  <david.sherwood@arm.com>

gcc/
	* config/aarch64/aarch64-modes.def: Remove 32-, 48- and 64-byte
	vector modes.
	* config/aarch64/iterators.md (VRL2, VRL3, VRL4): Delete.
	* config/aarch64/aarch64.md (UNSPEC_LD2_DREG, UNSPEC_LD3_DREG)
	(UNSPEC_LD4_DREG): New unspecs.
	* config/aarch64/aarch64-simd.md (aarch64_ld2<mode>_dreg_le)
	(aarch64_ld2<mode>_dreg_be): Replace with...
	(aarch64_ld2<mode>_dreg): ...this pattern and use the new DREG
	unspec.
	(aarch64_ld3<mode>_dreg_le)
	(aarch64_ld3<mode>_dreg_be): Replace with...
	(aarch64_ld3<mode>_dreg): ...this pattern and use the new DREG
	unspec.
	(aarch64_ld4<mode>_dreg_le)
	(aarch64_ld4<mode>_dreg_be): Replace with...
	(aarch64_ld4<mode>_dreg): ...this pattern and use the new DREG
	unspec.

Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>

From-SVN: r251555

strcpy will keep reading and writing memory if the string is not terminated
with null character. In this case, it may visit memory beyond the boundary.

gcc/testsuite/

2017-08-31  Renlin Li  <renlin.li@arm.com>
	    Aaron Sawdey  <acsawdey@linux.vnet.ibm.com>

	* gcc.dg/memcmp-1.c (test_strncmp): Use memcpy instead of strcpy.


Co-Authored-By: Aaron Sawdey <acsawdey@linux.vnet.ibm.com>

From-SVN: r251554

From-SVN: r251553

	PR c++/80767
	* call.c (compare_ics): Handle null candidate.

From-SVN: r251549

cp/

* pt.c (unify_overload_resolution_failure): Remove.
(unify_one_argument): Adjust.

testsuite/

* g++.dg/overload/template6.C: New.

From-SVN: r251548

[gcc]

2017-08-30  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>

	PR tree-optimization/81987
	* gimple-ssa-strength-reduction.c (insert_initializers): Don't
	insert an initializer in a location not dominated by the stride
	definition.

[gcc/testsuite]

2017-08-30  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>

	PR tree-optimization/81987
	* g++.dg/torture/pr81987.C: New file.

From-SVN: r251547

tree-eh.c (lower_try_finally_switch): Set the location of the finally on the entire header of the finally block in...

	* tree-eh.c (lower_try_finally_switch): Set the location of the finally
	on the entire header of the finally block in the fallthru case.

From-SVN: r251546

From-SVN: r251545

rs6000.c (rs6000_emit_prologue_move_from_cr): Rename from rs6000_emit_move_from_cr and call renamed function.

	* config/rs6000/rs6000.c (rs6000_emit_prologue_move_from_cr): Rename from
	rs6000_emit_move_from_cr and call renamed function.
	(rs6000_emit_prologue): Call renamed functions.
	* config/rs6000/rs6000.md (prologue_movesi_from_cr): Rename from
	movesi_from_cr, remove volatile CRs.

	* gcc.target/powerpc/cr_shrink-wrap.c: New.

From-SVN: r251543

From-SVN: r251541