[ARC] Reimplement ZOL support.

2017-05-22  Claudiu Zissulescu <claziss@synopsys.com>

	* config/arc/arc-c.c (__ARC_LPC_WIDTH__): Add builtin define.
	* config/arc/arc.c (ARC_MAX_LOOP_LENGTH): Define.
	(arc_conditional_register_usage): Remove ARC600 lp_count
	exception.
	(arc_file_start): Emit Tag_ARC_CPU_variation.
	(arc_can_use_doloop_p): New conditions to use ZOLs.
	(hwloop_fail): New function.
	(hwloop_optimize): Likewise.
	(hwloop_pattern_reg): Likewise.
	(arc_doloop_hooks): New struct, to be used with reorg_loops.
	(arc_reorg_loops): New function, calls reorg_loops.
	(arc_reorg): Call arc_reorg_loops.  Remove old ZOL handling.
	(arc600_corereg_hazard): Remove ZOL checking, case handled by
	hwloop_optimize.
	(arc_loop_hazard): Remove function, functionality moved into
	hwloop_optimize.
	(arc_hazard): Remove arc_loop_hazard call.
	(arc_adjust_insn_length): Remove ZOL handling, functionality moved
	into hwloop_optimize.
	(arc_label_align): Remove ZOL handling.
	* config/arc/arc.h (LOOP_ALIGN): Changed to 0.
	* config/arc/arc.md (doloop_begin): Remove pattern.
	(doloop_begin_i): Likewise.
	(doloop_end_i): Likewise.
	(doloop_fallback): Likewise.
	(doloop_fallback_m): Likewise.
	(doloop_end): Reimplement expand.
	(arc_lp): New pattern for LP instruction.
	(loop_end): New pattern.
	(loop_fail): Likewise.
	(decrement_and_branch_until_zero): Likewise.
	* config/arc/arc.opt (mlpc-width): New option.
	* doc/invoke.texi (mlpc-width): Document option.

testsuite/
2017-05-22  Claudiu Zissulescu <claziss@synopsys.com>

 	    * gcc.target/arc/loop-1.c: Deleted.

From-SVN: r251589

gcc/ChangeLog

 2017-09-01  Claudiu Zissulescu  <claziss@synopsys.com>
 
+	* config/arc/arc-c.c (__ARC_LPC_WIDTH__): Add builtin define.
+	* config/arc/arc.c (ARC_MAX_LOOP_LENGTH): Define.
+	(arc_conditional_register_usage): Remove ARC600 lp_count
+	exception.
+	(arc_file_start): Emit Tag_ARC_CPU_variation.
+	(arc_can_use_doloop_p): New conditions to use ZOLs.
+	(hwloop_fail): New function.
+	(hwloop_optimize): Likewise.
+	(hwloop_pattern_reg): Likewise.
+	(arc_doloop_hooks): New struct, to be used with reorg_loops.
+	(arc_reorg_loops): New function, calls reorg_loops.
+	(arc_reorg): Call arc_reorg_loops.  Remove old ZOL handling.
+	(arc600_corereg_hazard): Remove ZOL checking, case handled by
+	hwloop_optimize.
+	(arc_loop_hazard): Remove function, functionality moved into
+	hwloop_optimize.
+	(arc_hazard): Remove arc_loop_hazard call.
+	(arc_adjust_insn_length): Remove ZOL handling, functionality moved
+	into hwloop_optimize.
+	(arc_label_align): Remove ZOL handling.
+	* config/arc/arc.h (LOOP_ALIGN): Changed to 0.
+	* config/arc/arc.md (doloop_begin): Remove pattern.
+	(doloop_begin_i): Likewise.
+	(doloop_end_i): Likewise.
+	(doloop_fallback): Likewise.
+	(doloop_fallback_m): Likewise.
+	(doloop_end): Reimplement expand.
+	(arc_lp): New pattern for LP instruction.
+	(loop_end): New pattern.
+	(loop_fail): Likewise.
+	(decrement_and_branch_until_zero): Likewise.
+	* config/arc/arc.opt (mlpc-width): New option.
+	* doc/invoke.texi (mlpc-width): Document option.
+
+2017-09-01  Claudiu Zissulescu  <claziss@synopsys.com>
+
 	* config/arc/arc.c (arc_ifcvt): Remove use of merge_blocks call.
 	(arc_ccfsm_advance): Fix checking for delay slots.
 	(arc_reorg): Add rtl dump after each call to arc_ifcvt.

gcc/config/arc/arc-c.c

@@ -62,6 +62,8 @@ arc_cpu_cpp_builtins (cpp_reader * pfile)
   builtin_define_with_int_value ("__ARC_TLS_REGNO__",
 				 arc_tp_regno);
 
+  builtin_define_with_int_value ("__ARC_LPC_WIDTH__", arc_lpcwidth);
+
   builtin_define (TARGET_BIG_ENDIAN
 		  ? "__BIG_ENDIAN__" : "__LITTLE_ENDIAN__");
   if (TARGET_BIG_ENDIAN)

gcc/config/arc/arc.h

@@ -581,15 +581,15 @@ enum reg_class
   {0x0000f00f, 0x00000000, 0x00000000, 0x00000000, 0x00000000},	     /* 'q', r0-r3, r12-r15 */		\
   {0x1000f00f, 0x00000000, 0x00000000, 0x00000000, 0x00000000},	     /* 'e', r0-r3, r12-r15, sp */	\
   {0x1c001fff, 0x00000000, 0x00000000, 0x00000000, 0x00000000},    /* "Rsc", r0-r12 */ \
-  {0x9fffffff, 0xc0000000, 0x00000000, 0x00000000, 0x00000000},      /* 'r', r0-r28, blink, ap and pcl */	\
+  {0x9fffffff, 0x80000000, 0x00000000, 0x00000000, 0x00000000},      /* 'r', r0-r28, blink, ap and pcl */	\
   {0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000},      /* 'W',  r0-r31 */ \
   /* Include ap / pcl in WRITABLE_CORE_REGS for sake of symmetry.  As these \
      registers are fixed, it does not affect the literal meaning of the \
      constraints, but it makes it a superset of GENERAL_REGS, thus \
      enabling some operations that would otherwise not be possible.  */ \
-  {0xffffffff, 0xd0000000, 0x00000000, 0x00000000, 0x00000000},      /* 'w', r0-r31, r60 */ \
-  {0xffffffff, 0xdfffffff, 0x00000000, 0x00000000, 0x00000000},      /* 'c', r0-r60, ap, pcl */ \
-  {0xffffffff, 0xdfffffff, 0x00000000, 0x00000000, 0x00000000},      /* 'Rac', r0-r60, ap, pcl */ \
+  {0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000},      /* 'w', r0-r31, r60 */ \
+  {0xffffffff, 0x9fffffff, 0x00000000, 0x00000000, 0x00000000},      /* 'c', r0-r60, ap, pcl */ \
+  {0xffffffff, 0x9fffffff, 0x00000000, 0x00000000, 0x00000000},      /* 'Rac', r0-r60, ap, pcl */ \
   {0x0000000f, 0x00000000, 0x00000000, 0x00000000, 0x00000000},      /* 'Rcd', r0-r3 */ \
   {0x00000003, 0x00000000, 0x00000000, 0x00000000, 0x00000000},      /* 'Rsd', r0-r1 */ \
   {0x9fffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000},      /* 'h',  r0-28, r30 */ \
@@ -1351,7 +1351,7 @@ do {							\
    of a loop.  */
 /* On the ARC, align loops to 4 byte boundaries unless doing all-out size
    optimization.  */
-#define LOOP_ALIGN JUMP_ALIGN
+#define LOOP_ALIGN(X) 0
 
 #define LABEL_ALIGN(LABEL) (arc_label_align (LABEL))
 

gcc/config/arc/arc.opt

@@ -494,3 +494,28 @@ Specifies the registers that the processor saves on an interrupt entry and exit.
 mrgf-banked-regs=
 Target RejectNegative Joined Var(arc_deferred_options) Defer
 Specifies the number of registers replicated in second register bank on entry to fast interrupt.
+
+mlpc-width=
+Target RejectNegative Joined Enum(arc_lpc) Var(arc_lpcwidth) Init(32)
+Sets LP_COUNT register width.  Possible values are 8, 16, 20, 24, 28, and 32.
+
+Enum
+Name(arc_lpc) Type(int)
+
+EnumValue
+Enum(arc_lpc) String(8) Value(8)
+
+EnumValue
+Enum(arc_lpc) String(16) Value(16)
+
+EnumValue
+Enum(arc_lpc) String(20) Value(20)
+
+EnumValue
+Enum(arc_lpc) String(24) Value(24)
+
+EnumValue
+Enum(arc_lpc) String(28) Value(28)
+
+EnumValue
+Enum(arc_lpc) String(32) Value(32)

gcc/config/arc/predicates.md

@@ -362,6 +362,8 @@
       else if (TARGET_MUL64_SET
 	       && (REGNO (op) == 57 || REGNO(op) == 58 || REGNO(op) == 59 ))
 	return 0;
+      else if (REGNO (op) == LP_COUNT)
+        return 1;
       else
 	return dest_reg_operand (op, mode);
     case SUBREG :

gcc/doc/invoke.texi

@@ -614,7 +614,7 @@ Objective-C and Objective-C++ Dialects}.
 -mcrc  -mdsp-packa  -mdvbf  -mlock  -mmac-d16  -mmac-24  -mrtsc  -mswape @gol
 -mtelephony  -mxy  -misize  -mannotate-align  -marclinux  -marclinux_prof @gol
 -mlong-calls  -mmedium-calls  -msdata -mirq-ctrl-saved @gol
--mrgf-banked-regs -G @var{num} @gol
+-mrgf-banked-regs -mlpc-width=@var{width} -G @var{num} @gol
 -mvolatile-cache  -mtp-regno=@var{regno} @gol
 -malign-call  -mauto-modify-reg  -mbbit-peephole  -mno-brcc @gol
 -mcase-vector-pcrel  -mcompact-casesi  -mno-cond-exec  -mearly-cbranchsi @gol
@@ -14779,6 +14779,18 @@ registers to avoid memory transactions during interrupt entry and exit
 sequences.  Use this option when you are using fast interrupts in an
 ARC V2 family processor.  Permitted values are 4, 8, 16, and 32.
 
+@item -mlpc-width=@var{width}
+@opindex mlpc-width
+Specify the width of the @code{lp_count} register.  Valid values for
+@var{width} are 8, 16, 20, 24, 28 and 32 bits.  The default width is
+fixed to 32 bits.  If the width is less than 32, the compiler does not
+attempt to transform loops in your program to use the zero-delay loop
+mechanism unless it is known that the @code{lp_count} register can
+hold the required loop-counter value.  Depending on the width
+specified, the compiler and run-time library might continue to use the
+loop mechanism for various needs.  This option defines macro
+@code{__ARC_LPC_WIDTH__} with the value of @var{width}.
+
 @end table
 
 The following options are passed through to the assembler, and also

gcc/testsuite/ChangeLog

 2017-09-01  Claudiu Zissulescu  <claziss@synopsys.com>
 
+	* gcc.target/arc/loop-1.c: Deleted.
+
+2017-09-01  Claudiu Zissulescu  <claziss@synopsys.com>
+
 	* gcc.target/arc/arc.exp: Test also cpp files.
 	* gcc.target/arc/tdelay_slots.cpp: New test.
 

gcc/testsuite/gcc.target/arc/loop-1.c

-/* { dg-do compile } */
-/* { dg-options "-O2" } */
-
-/* This case would fail to make use of the zero-overhead loop
-   instruction at one time due to a bug.  */
-
-extern char a[];
-
-struct some_t
-{
-  struct
-  {
-    int aaa;
-    short bbb;
-    char ccc;
-    char ddd;
-  } ppp[8];
-
-  int www[1];
-};
-
-int b;
-
-void
-some_function ()
-{
-  struct some_t *tmp = (struct some_t *) a;
-
-  while ((*tmp).ppp[b].ccc)
-    while(0);
-
-  for (; b; b++)
-    {
-      if (tmp->ppp[b].ccc)
-        {
-          int c = tmp->ppp[b].bbb;
-          int d = tmp->ppp[b].aaa;
-          int e = d - tmp->www[c];
-          if (e)
-            tmp->ppp[b].ddd = 1;
-        }
-    }
-}
-
-/* { dg-final { scan-assembler "\[^\n\]+lp \\.L__GCC__" } } */