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  1. 10 Jan, 2019 21 commits
    • gcc/ChangeLog: · 280d970b 
      2019-01-10  Tamar Christina  <tamar.christina@arm.com>

	* config/aarch64/aarch64-builtins.c
	(aarch64_init_builtins): Move aarch64_init_fcmla_laneq_builtins...
	(aarch64_init_simd_builtins): ...Here.

From-SVN: r267824
      Tamar Christina committed
    • re PR rtl-optimization/87305 (Segfault in end_hard_regno in… · 7e4d17a8 
      re PR rtl-optimization/87305 (Segfault in end_hard_regno in setup_live_pseudos_and_spill_after_risky_transforms on aarch64 big-endian)

2019-01-10  Vladimir Makarov  <vmakarov@redhat.com>

	PR rtl-optimization/87305
	* lra-assigns.c
	(setup_live_pseudos_and_spill_after_risky_transforms): Check
	allocation for big endian pseudos used as paradoxical subregs and
	spill them if it is wrong.
	* lra-constraints.c (lra_constraints): Add a comment.

2019-01-10  Vladimir Makarov  <vmakarov@redhat.com>

	PR rtl-optimization/87305
	* gcc.target/aarch64/pr87305.c: New.

From-SVN: r267823
      Vladimir Makarov committed
    • re PR tree-optimization/88792 (wrong-code in RPO VN since r263875) · f25507d0 
      2019-01-10  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/88792
	* tree-ssa-pre.c (get_representative_for): Do not return a
	value-number here.

	* gcc.dg/torture/pr88792.c: New testcase.

From-SVN: r267821
      Richard Biener committed
    • re PR fortran/86322 (ICE in reference_record with data statement) · bebf94af 
      2019-01-10  Steven G. Kargl  <kargl@gcc.gnu.org>

	PR fortran/86322
	* decl.c (top_var_list): Set locus of expr.
	(gfc_match_data): Detect pointer on non-rightmost part-refs.

2019-01-10  Steven G. Kargl  <kargl@gcc.gnu.org>

	PR fortran/86322
	* gfortran.dg/pr86322_1.f90: New test.
	* gfortran.dg/pr86322_2.f90: Ditto.
	* gfortran.dg/pr86322_3.f90: Ditto.

From-SVN: r267820
      Steven G. Kargl committed
    • [Committed, AArch64] Disable tests for ilp32. · 8b530f81 
      Currently Return Address Signing is only supported in lp64. Thus the
tests that I added recently (that enables return address signing by the
mbranch-protection=standard option), should also be exempted from testing in
ilp32. This patch adds the needed dg-require-effective-target directive in the
tests.

*** gcc/testsuite/ChangeLog ***

2019-01-10  Sudakshina Das  <sudi.das@arm.com>

	* gcc.target/aarch64/bti-1.c: Exempt for ilp32.
	* gcc.target/aarch64/bti-2.c: Likewise.
	* gcc.target/aarch64/bti-3.c: Likewise.

Committed as obvious.

From-SVN: r267818
      Sudakshina Das committed
    • re PR middle-end/84877 (Local stack copy of BLKmode parameter on the stack is… · d9e91ebb 
      re PR middle-end/84877 (Local stack copy of BLKmode parameter on the stack is not aligned when the requested alignment exceeds MAX_SUPPORTED_STACK_ALIGNMENT)

	PR middle-end/84877
	PR bootstrap/88450
	* function.c (assign_stack_local_1): Revert the 2018-11-21 changes.
	(assign_parm_setup_block): Do the argument slot realignment here
	instead.

From-SVN: r267812
      Jakub Jelinek committed
    • Fix filesystem::last_write_time failure with 32-bit time_t · 174f1d26 
      	* testsuite/27_io/filesystem/operations/last_write_time.cc: Fix
	test failures on targets with 32-bit time_t.

From-SVN: r267811
      Jonathan Wakely committed
    • Define __cpp_lib_erase_if feature test macro · 45a8d80f 
      The C++2a draft specifies the value 201811L for this, but as an
extension we return the number of elements erased. This is expected to
be standardised, so the macro has the value 201900L until a proper value
is specified in the draft.

	* include/bits/erase_if.h: Define __cpp_lib_erase_if.
	* include/std/deque: Likewise.
	* include/std/forward_list: Likewise.
	* include/std/list: Likewise.
	* include/std/string: Likewise.
	* include/std/vector: Likewise.
	* include/std/version: Likewise.
	* testsuite/21_strings/basic_string/erasure.cc: Test macro.
	* testsuite/23_containers/deque/erasure.cc: Likewise.
	* testsuite/23_containers/forward_list/erasure.cc: Likewise.
	* testsuite/23_containers/list/erasure.cc: Likewise.
	* testsuite/23_containers/map/erasure.cc: Likewise.
	* testsuite/23_containers/set/erasure.cc: Likewise.
	* testsuite/23_containers/unordered_map/erasure.cc: Likewise.
	* testsuite/23_containers/unordered_set/erasure.cc: Likewise.
	* testsuite/23_containers/vector/erasure.cc: Likewise.

From-SVN: r267810
      Jonathan Wakely committed
    • Check AI_NUMERICSERV is defined before using it · cbe0bca4 
      The AI_NUMERICSERV constant is missing from old Darwin systems, so only
use it if it's supported.

	* include/experimental/internet [AI_NUMERICSERV]
	(resolver_base::numeric_service): Define conditionally.
	* testsuite/experimental/net/internet/resolver/base.cc: Test it
	conditionally.
	* testsuite/experimental/net/internet/resolver/ops/lookup.cc:
	Likewise.

From-SVN: r267809
      Jonathan Wakely committed
    • Implement LWG 2221: formatted output operator for nullptr · c3799b16 
      2019-01-10  Ville Voutilainen  <ville.voutilainen@gmail.com>
	    Jonathan Wakely  <jwakely@redhat.com>

	Implement LWG 2221
	* config/abi/pre/gnu.ver (GLIBCXX_3.4): Tighten patterns.
	(GLIBCXX_3.4.26): Add new exports.
	* include/Makefile.am: Add ostream-inst.cc. Move string-inst.cc to
	correct list of sources.
	* include/Makefile.in: Regenerate.
	* include/std/ostream (operator<<(nullptr_t)): New member function.
	* src/c++17/ostream-inst.cc: New file.
	* testsuite/27_io/basic_ostream/inserters_other/char/lwg2221.cc: New
	test.

Co-Authored-By: Jonathan Wakely <jwakely@redhat.com>

From-SVN: r267808
      Ville Voutilainen committed
    • Add testcase from PR71959 · e222497d 
      	libgomp/

	PR lto/71959
	* testsuite/libgomp.oacc-c++/pr71959-aux.cc: New.
	* testsuite/libgomp.oacc-c++/pr71959.C: New.

Co-Authored-By: Julian Brown <julian@codesourcery.com>

From-SVN: r267806
      Nathan Sidwell committed
    • ARM: fix -masm-syntax-unified (PR88648) · ae8792cb 
      This allows to use unified asm syntax when compiling for the
ARM instruction. This matches documentation and seems what the
initial patch was intended doing when the flag got added.

2019-01-10  Stefan Agner  <stefan@agner.ch>

	PR target/88648
	* config/arm/arm.c (arm_option_override_internal): Force
	opts->x_inline_asm_unified to true only if TARGET_THUMB2_P.

	* gcc.target/arm/pr88648-asm-syntax-unified.c: Add test to
	check if -masm-syntax-unified gets applied properly.

From-SVN: r267804
      Stefan Agner committed
    • Include name of test in filesystem-test.XXXXXX filenames · 7c4979b2 
      Also fix some tests that were not cleaning up after themselves, as
identified by the change to nonexistent_path.

	* testsuite/util/testsuite_fs.h (nonexistent_path): Include name
	of the source file containing the caller.
	* testsuite/27_io/filesystem/iterators/directory_iterator.cc: Remove
	directories created by test.
	* testsuite/27_io/filesystem/iterators/recursive_directory_iterator.cc:
	Likewise.
	* testsuite/experimental/filesystem/iterators/directory_iterator.cc:
	Likewise.
	* testsuite/experimental/filesystem/iterators/
	recursive_directory_iterator.cc: Likewise.

From-SVN: r267801
      Jonathan Wakely committed
    • re PR tree-optimization/88775 (Optimize std::string assignment) · 6cdf1946 
      	PR tree-optimization/88775
	* include/bits/stl_function.h (greater<_Tp*>::operator(),
	less<_Tp*>::operator(), greater_equal<_Tp*>::operator(),
	less_equal<_Tp*>::operator()): Use __builtin_is_constant_evaluated
	instead of __builtin_constant_p if available.  Don't bother with
	the pointer comparison in C++11 and earlier.

From-SVN: r267800
      Jakub Jelinek committed
    • re PR c/88568 ('dllimport' no longer implies 'extern' in C) · dbf02a2c 
      	PR c/88568
	* attribs.c (handle_dll_attribute): Clear TREE_STATIC after setting
	DECL_EXTERNAL.

	* gcc.dg/pr88568.c: New test.

From-SVN: r267799
      Jakub Jelinek committed
    • Fix formatting · aa6c5afe 
      From-SVN: r267797
      Eric Botcazou committed
    • arm-builtins.c (enum arm_type_qualifiers): Add qualifier_lane_pair_index. · c2b7062d 
      2019-01-10  Tamar Christina  <tamar.christina@arm.com>

	* config/arm/arm-builtins.c
	(enum arm_type_qualifiers): Add qualifier_lane_pair_index.
	(MAC_LANE_PAIR_QUALIFIERS): New.
	(arm_expand_builtin_args): Use it.
	(arm_expand_builtin_1): Likewise.
	* config/arm/arm-protos.h (neon_vcmla_lane_prepare_operands): New.
	* config/arm/arm.c (neon_vcmla_lane_prepare_operands): New.
	* config/arm/arm-c.c (arm_cpu_builtins): Add __ARM_FEATURE_COMPLEX.
	* config/arm/arm_neon.h:
	(vcadd_rot90_f16): New.
	(vcaddq_rot90_f16): New.
	(vcadd_rot270_f16): New.
	(vcaddq_rot270_f16): New.
	(vcmla_f16): New.
	(vcmlaq_f16): New.
	(vcmla_lane_f16): New.
	(vcmla_laneq_f16): New.
	(vcmlaq_lane_f16): New.
	(vcmlaq_laneq_f16): New.
	(vcmla_rot90_f16): New.
	(vcmlaq_rot90_f16): New.
	(vcmla_rot90_lane_f16): New.
	(vcmla_rot90_laneq_f16): New.
	(vcmlaq_rot90_lane_f16): New.
	(vcmlaq_rot90_laneq_f16): New.
	(vcmla_rot180_f16): New.
	(vcmlaq_rot180_f16): New.
	(vcmla_rot180_lane_f16): New.
	(vcmla_rot180_laneq_f16): New.
	(vcmlaq_rot180_lane_f16): New.
	(vcmlaq_rot180_laneq_f16): New.
	(vcmla_rot270_f16): New.
	(vcmlaq_rot270_f16): New.
	(vcmla_rot270_lane_f16): New.
	(vcmla_rot270_laneq_f16): New.
	(vcmlaq_rot270_lane_f16): New.
	(vcmlaq_rot270_laneq_f16): New.
	(vcadd_rot90_f32): New.
	(vcaddq_rot90_f32): New.
	(vcadd_rot270_f32): New.
	(vcaddq_rot270_f32): New.
	(vcmla_f32): New.
	(vcmlaq_f32): New.
	(vcmla_lane_f32): New.
	(vcmla_laneq_f32): New.
	(vcmlaq_lane_f32): New.
	(vcmlaq_laneq_f32): New.
	(vcmla_rot90_f32): New.
	(vcmlaq_rot90_f32): New.
	(vcmla_rot90_lane_f32): New.
	(vcmla_rot90_laneq_f32): New.
	(vcmlaq_rot90_lane_f32): New.
	(vcmlaq_rot90_laneq_f32): New.
	(vcmla_rot180_f32): New.
	(vcmlaq_rot180_f32): New.
	(vcmla_rot180_lane_f32): New.
	(vcmla_rot180_laneq_f32): New.
	(vcmlaq_rot180_lane_f32): New.
	(vcmlaq_rot180_laneq_f32): New.
	(vcmla_rot270_f32): New.
	(vcmlaq_rot270_f32): New.
	(vcmla_rot270_lane_f32): New.
	(vcmla_rot270_laneq_f32): New.
	(vcmlaq_rot270_lane_f32): New.
	(vcmlaq_rot270_laneq_f32): New.
	* config/arm/arm_neon_builtins.def (vcadd90, vcadd270, vcmla0, vcmla90,
	vcmla180, vcmla270, vcmla_lane0, vcmla_lane90, vcmla_lane180, vcmla_lane270,
	vcmla_laneq0, vcmla_laneq90, vcmla_laneq180, vcmla_laneq270,
	vcmlaq_lane0, vcmlaq_lane90, vcmlaq_lane180, vcmlaq_lane270): New.
	* config/arm/neon.md (neon_vcmla_lane<rot><mode>,
	neon_vcmla_laneq<rot><mode>, neon_vcmlaq_lane<rot><mode>): New.
	* config/arm/arm.c (arm_arch8_3, arm_arch8_4): New.
	* config/arm/arm.h (TARGET_COMPLEX, arm_arch8_3, arm_arch8_4): New.
	(arm_option_reconfigure_globals): Use them.
	* config/arm/iterators.md (VDF, VQ_HSF): New.
	(VCADD, VCMLA): New.
	(VF_constraint, rot, rotsplit1, rotsplit2): Add V4HF and V8HF.
	* config/arm/neon.md (neon_vcadd<rot><mode>, neon_vcmla<rot><mode>): New.
	* config/arm/unspecs.md (UNSPEC_VCADD90, UNSPEC_VCADD270,
	UNSPEC_VCMLA, UNSPEC_VCMLA90, UNSPEC_VCMLA180, UNSPEC_VCMLA270): New.

gcc/testsuite/ChangeLog:

2019-01-10  Tamar Christina  <tamar.christina@arm.com>

	* gcc.target/aarch64/advsimd-intrinsics/vector-complex.c: Add AArch32 regexpr.
	* gcc.target/aarch64/advsimd-intrinsics/vector-complex_f16.c: Likewise.

From-SVN: r267796
      Tamar Christina committed
    • aarch64-builtins.c (enum aarch64_type_qualifiers): Add qualifier_lane_pair_index. · 9d63f43b 
      gcc/ChangeLog:

2019-01-10  Tamar Christina  <tamar.christina@arm.com>

	* config/aarch64/aarch64-builtins.c (enum aarch64_type_qualifiers): Add qualifier_lane_pair_index.
	(emit-rtl.h): Include.
	(TYPES_QUADOP_LANE_PAIR): New.
	(aarch64_simd_expand_args): Use it.
	(aarch64_simd_expand_builtin): Likewise.
	(AARCH64_SIMD_FCMLA_LANEQ_BUILTINS, aarch64_fcmla_laneq_builtin_datum): New.
	(FCMLA_LANEQ_BUILTIN, AARCH64_SIMD_FCMLA_LANEQ_BUILTIN_BASE,
	AARCH64_SIMD_FCMLA_LANEQ_BUILTINS, aarch64_fcmla_lane_builtin_data,
	aarch64_init_fcmla_laneq_builtins, aarch64_expand_fcmla_builtin): New.
	(aarch64_init_builtins): Add aarch64_init_fcmla_laneq_builtins.
	(aarch64_expand_buildin): Add AARCH64_SIMD_BUILTIN_FCMLA_LANEQ0_V2SF,
	AARCH64_SIMD_BUILTIN_FCMLA_LANEQ90_V2SF, AARCH64_SIMD_BUILTIN_FCMLA_LANEQ180_V2SF,
 	AARCH64_SIMD_BUILTIN_FCMLA_LANEQ2700_V2SF, AARCH64_SIMD_BUILTIN_FCMLA_LANEQ0_V4HF,
	AARCH64_SIMD_BUILTIN_FCMLA_LANEQ90_V4HF, AARCH64_SIMD_BUILTIN_FCMLA_LANEQ180_V4HF,
	AARCH64_SIMD_BUILTIN_FCMLA_LANEQ270_V4HF.
	* config/aarch64/iterators.md (FCMLA_maybe_lane): New.
	* config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Add __ARM_FEATURE_COMPLEX.
	* config/aarch64/aarch64-simd-builtins.def (fcadd90, fcadd270, fcmla0, fcmla90,
	fcmla180, fcmla270, fcmla_lane0, fcmla_lane90, fcmla_lane180, fcmla_lane270,
	fcmla_laneq0, fcmla_laneq90, fcmla_laneq180, fcmla_laneq270,
	fcmlaq_lane0, fcmlaq_lane90, fcmlaq_lane180, fcmlaq_lane270): New.
	* config/aarch64/aarch64-simd.md (aarch64_fcmla_lane<rot><mode>,
	aarch64_fcmla_laneq<rot>v4hf, aarch64_fcmlaq_lane<rot><mode>,aarch64_fcadd<rot><mode>,
	aarch64_fcmla<rot><mode>): New.
	* config/aarch64/arm_neon.h:
	(vcadd_rot90_f16): New.
	(vcaddq_rot90_f16): New.
	(vcadd_rot270_f16): New.
	(vcaddq_rot270_f16): New.
	(vcmla_f16): New.
	(vcmlaq_f16): New.
	(vcmla_lane_f16): New.
	(vcmla_laneq_f16): New.
	(vcmlaq_lane_f16): New.
	(vcmlaq_rot90_lane_f16): New.
	(vcmla_rot90_laneq_f16): New.
	(vcmla_rot90_lane_f16): New.
	(vcmlaq_rot90_f16): New.
	(vcmla_rot90_f16): New.
	(vcmlaq_laneq_f16): New.
	(vcmla_rot180_laneq_f16): New.
	(vcmla_rot180_lane_f16): New.
	(vcmlaq_rot180_f16): New.
	(vcmla_rot180_f16): New.
	(vcmlaq_rot90_laneq_f16): New.
	(vcmlaq_rot270_laneq_f16): New.
	(vcmlaq_rot270_lane_f16): New.
	(vcmla_rot270_laneq_f16): New.
	(vcmlaq_rot270_f16): New.
	(vcmla_rot270_f16): New.
	(vcmlaq_rot180_laneq_f16): New.
	(vcmlaq_rot180_lane_f16): New.
	(vcmla_rot270_lane_f16): New.
	(vcadd_rot90_f32): New.
	(vcaddq_rot90_f32): New.
	(vcaddq_rot90_f64): New.
	(vcadd_rot270_f32): New.
	(vcaddq_rot270_f32): New.
	(vcaddq_rot270_f64): New.
	(vcmla_f32): New.
	(vcmlaq_f32): New.
	(vcmlaq_f64): New.
	(vcmla_lane_f32): New.
	(vcmla_laneq_f32): New.
	(vcmlaq_lane_f32): New.
	(vcmlaq_laneq_f32): New.
	(vcmla_rot90_f32): New.
	(vcmlaq_rot90_f32): New.
	(vcmlaq_rot90_f64): New.
	(vcmla_rot90_lane_f32): New.
	(vcmla_rot90_laneq_f32): New.
	(vcmlaq_rot90_lane_f32): New.
	(vcmlaq_rot90_laneq_f32): New.
	(vcmla_rot180_f32): New.
	(vcmlaq_rot180_f32): New.
	(vcmlaq_rot180_f64): New.
	(vcmla_rot180_lane_f32): New.
	(vcmla_rot180_laneq_f32): New.
	(vcmlaq_rot180_lane_f32): New.
	(vcmlaq_rot180_laneq_f32): New.
	(vcmla_rot270_f32): New.
	(vcmlaq_rot270_f32): New.
	(vcmlaq_rot270_f64): New.
	(vcmla_rot270_lane_f32): New.
	(vcmla_rot270_laneq_f32): New.
	(vcmlaq_rot270_lane_f32): New.
	(vcmlaq_rot270_laneq_f32): New.
	* config/aarch64/aarch64.h (TARGET_COMPLEX): New.
	* config/aarch64/iterators.md (UNSPEC_FCADD90, UNSPEC_FCADD270,
	UNSPEC_FCMLA, UNSPEC_FCMLA90, UNSPEC_FCMLA180, UNSPEC_FCMLA270): New.
	(FCADD, FCMLA): New.
	(rot): New.
	* config/arm/types.md (neon_fcadd, neon_fcmla): New.

gcc/testsuite/ChangeLog:

2019-01-10  Tamar Christina  <tamar.christina@arm.com>

	* gcc.target/aarch64/advsimd-intrinsics/vector-complex.c: New test.
	* gcc.target/aarch64/advsimd-intrinsics/vector-complex_f16.c: New test.

From-SVN: r267795
      Tamar Christina committed
    • target-supports.exp (check_effective_target_arm_v8_3a_complex_neon_ok_nocache, [...]): New. · 90c3d78f 
      gcc/testsuite/ChangeLog:

2019-01-10  Tamar Christina  <tamar.christina@arm.com>

	* lib/target-supports.exp
	(check_effective_target_arm_v8_3a_complex_neon_ok_nocache,
	check_effective_target_arm_v8_3a_complex_neon_ok,
	add_options_for_arm_v8_3a_complex_neon,
	check_effective_target_arm_v8_3a_complex_neon_hw,
	check_effective_target_vect_complex_rot_N): New.

From-SVN: r267794
      Tamar Christina committed
    • re PR fortran/88376 (ICE in is_illegal_recursion, at fortran/resolve.c:1689) · 8c94b8da 
      2019-01-09  Steven G. Kargl  <kargl@gcc.gnu.org>

	PR fortran/88376
	* resolve.c (is_illegal_recursion): Remove an assert().

2019-01-09  Steven G. Kargl  <kargl@gcc.gnu.org>

	PR fortran/88376
	* gfortran.dg/pr88376.f90: New test.

From-SVN: r267793
      Steven G. Kargl committed
    • Daily bump. · 3856c6bb 
      From-SVN: r267792
      GCC Administrator committed
  3. 09 Jan, 2019 19 commits
    • re PR go/86343 (types built by GO share TYPE_FIELDS in unsupported way) · eea11d66 
      	PR go/86343
	* go-gcc.cc (Gcc_backend::set_placeholder_struct_type): Go back to
	build_distinct_type_copy, but copy the fields so that they have
	the right DECL_CONTEXT.

From-SVN: r267789
      Ian Lance Taylor committed
    • libphobos: Merge phobos upstream b022e552a · 9fa27ed0 
      This removes updates the removal date of all deprecations in phobos.
Many of the marked functions have passed their end dates, and are now
absent in upstream.

Reviewed-on: https://github.com/dlang/phobos/pull/6828

From-SVN: r267788
      Iain Buclaw committed
    • PR other/16615 [5/5] · 9ed7e53d 
      2019-01-09  Sandra Loosemore  <sandra@codesourcery.com>

	PR other/16615 [5/5]

	gcc/po/
	* gcc.pot: Regenerate.

From-SVN: r267787
      Sandra Loosemore committed
    • PR other/16615 [4/5] · 155ed511 
      2019-01-09  Sandra Loosemore  <sandra@codesourcery.com>

	PR other/16615 [4/5]

	gcc/
	* config/pa/pa.c: Change "can not" to "cannot".
	* gimple-ssa-evrp-analyze.c: Likewise.
	* ipa-icf.c: Likewise.
	* ipa-polymorphic-call.c: Likewise.
	* ipa-pure-const.c: Likewise.
	* lra-constraints.c: Likewise.
	* lra-remat.c: Likewise.
	* reload1.c: Likewise.
	* reorg.c: Likewise.
	* tree-ssa-uninit.c: Likewise.

	gcc/ada/
	* exp_ch11.adb: Change "can not" to "cannot".
	* sem_ch4.adb: Likewise.

	gcc/fortran/
	* expr.c: Change "can not" to "cannot".

	libobjc/
	* objc/runtime.h: Change "can not" to "cannot".

From-SVN: r267786
      Sandra Loosemore committed
    • PR other/16615 [3/5] · 430002e1 
      2019-01-09  Sandra Loosemore  <sandra@codesourcery.com>

	PR other/16615 [3/5]

	gcc/testsuite/
	* g++.dg/lto/odr-1_1.C: Update diagnostic message patterns to replace
	"can not" with "cannot".
	* gfortran.dg/common_15.f90: Likewise.
	* gfortran.dg/derived_result_2.f90: Likewise.
	* gfortran.dg/do_check_6.f90: Likewise.
	* gfortran.dg/namelist_args.f90: Likewise.
	* gfortran.dg/negative_unit_check.f90: Likewise.
	* gfortran.dg/pure_formal_3.f90: Likewise.
	* obj-c++.dg/attributes/method-attribute-2.mm: Likewise.
	* obj-c++.dg/exceptions-3.mm: Likewise.
	* obj-c++.dg/exceptions-4.mm: Likewise.
	* obj-c++.dg/exceptions-5.mm: Likewise.
	* obj-c++.dg/property/at-property-23.mm: Likewise.
	* obj-c++.dg/property/dotsyntax-17.mm: Likewise.
	* obj-c++.dg/property/property-neg-7.mm: Likewise.
	* objc.dg/attributes/method-attribute-2.m: Likewise.
	* objc.dg/exceptions-3.m: Likewise.
	* objc.dg/exceptions-4.m: Likewise.
	* objc.dg/exceptions-5.m: Likewise.
	* objc.dg/param-1.m: Likewise.
	* objc.dg/property/at-property-23.m: Likewise.
	* objc.dg/property/dotsyntax-17.m: Likewise.
	* objc.dg/property/property-neg-7.m: Likewise.

From-SVN: r267785
      Sandra Loosemore committed
    • PR other/16615 [2/5] · adcb167e 
      2019-01-09  Sandra Loosemore  <sandra@codesourcery.com>

	PR other/16615 [2/5]

	include/
	* libiberty.h: Mechanically replace "can not" with "cannot".
	* plugin-api.h: Likewise.

	libiberty/
	* cp-demangle.c: Mechanically replace "can not" with "cannot".
	* floatformat.c: Likewise.
	* strerror.c: Likewise.

From-SVN: r267784
      Sandra Loosemore committed
    • PR other/16615 [1/5] · 67914693 
      2019-01-09  Sandra Loosemore  <sandra@codesourcery.com>

	PR other/16615 [1/5]

	contrib/
	* mklog: Mechanically replace "can not" with "cannot".

	gcc/
	* Makefile.in: Mechanically replace "can not" with "cannot".
	* alias.c: Likewise.
	* builtins.c: Likewise.
	* calls.c: Likewise.
	* cgraph.c: Likewise.
	* cgraph.h: Likewise.
	* cgraphclones.c: Likewise.
	* cgraphunit.c: Likewise.
	* combine-stack-adj.c: Likewise.
	* combine.c: Likewise.
	* common/config/i386/i386-common.c: Likewise.
	* config/aarch64/aarch64.c: Likewise.
	* config/alpha/sync.md: Likewise.
	* config/arc/arc.c: Likewise.
	* config/arc/predicates.md: Likewise.
	* config/arm/arm-c.c: Likewise.
	* config/arm/arm.c: Likewise.
	* config/arm/arm.h: Likewise.
	* config/arm/arm.md: Likewise.
	* config/arm/cortex-r4f.md: Likewise.
	* config/csky/csky.c: Likewise.
	* config/csky/csky.h: Likewise.
	* config/darwin-f.c: Likewise.
	* config/epiphany/epiphany.md: Likewise.
	* config/i386/i386.c: Likewise.
	* config/i386/sol2.h: Likewise.
	* config/m68k/m68k.c: Likewise.
	* config/mcore/mcore.h: Likewise.
	* config/microblaze/microblaze.md: Likewise.
	* config/mips/20kc.md: Likewise.
	* config/mips/sb1.md: Likewise.
	* config/nds32/nds32.c: Likewise.
	* config/nds32/predicates.md: Likewise.
	* config/pa/pa.c: Likewise.
	* config/rs6000/e300c2c3.md: Likewise.
	* config/rs6000/rs6000.c: Likewise.
	* config/s390/s390.h: Likewise.
	* config/sh/sh.c: Likewise.
	* config/sh/sh.md: Likewise.
	* config/spu/vmx2spu.h: Likewise.
	* cprop.c: Likewise.
	* dbxout.c: Likewise.
	* df-scan.c: Likewise.
	* doc/cfg.texi: Likewise.
	* doc/extend.texi: Likewise.
	* doc/fragments.texi: Likewise.
	* doc/gty.texi: Likewise.
	* doc/invoke.texi: Likewise.
	* doc/lto.texi: Likewise.
	* doc/md.texi: Likewise.
	* doc/objc.texi: Likewise.
	* doc/rtl.texi: Likewise.
	* doc/tm.texi: Likewise.
	* dse.c: Likewise.
	* emit-rtl.c: Likewise.
	* emit-rtl.h: Likewise.
	* except.c: Likewise.
	* expmed.c: Likewise.
	* expr.c: Likewise.
	* fold-const.c: Likewise.
	* genautomata.c: Likewise.
	* gimple-fold.c: Likewise.
	* hard-reg-set.h: Likewise.
	* ifcvt.c: Likewise.
	* ipa-comdats.c: Likewise.
	* ipa-cp.c: Likewise.
	* ipa-devirt.c: Likewise.
	* ipa-fnsummary.c: Likewise.
	* ipa-icf.c: Likewise.
	* ipa-inline-transform.c: Likewise.
	* ipa-inline.c: Likewise.
	* ipa-polymorphic-call.c: Likewise.
	* ipa-profile.c: Likewise.
	* ipa-prop.c: Likewise.
	* ipa-pure-const.c: Likewise.
	* ipa-reference.c: Likewise.
	* ipa-split.c: Likewise.
	* ipa-visibility.c: Likewise.
	* ipa.c: Likewise.
	* ira-build.c: Likewise.
	* ira-color.c: Likewise.
	* ira-conflicts.c: Likewise.
	* ira-costs.c: Likewise.
	* ira-int.h: Likewise.
	* ira-lives.c: Likewise.
	* ira.c: Likewise.
	* ira.h: Likewise.
	* loop-invariant.c: Likewise.
	* loop-unroll.c: Likewise.
	* lower-subreg.c: Likewise.
	* lra-assigns.c: Likewise.
	* lra-constraints.c: Likewise.
	* lra-eliminations.c: Likewise.
	* lra-lives.c: Likewise.
	* lra-remat.c: Likewise.
	* lra-spills.c: Likewise.
	* lra.c: Likewise.
	* lto-cgraph.c: Likewise.
	* lto-streamer-out.c: Likewise.
	* postreload-gcse.c: Likewise.
	* predict.c: Likewise.
	* profile-count.h: Likewise.
	* profile.c: Likewise.
	* recog.c: Likewise.
	* ree.c: Likewise.
	* reload.c: Likewise.
	* reload1.c: Likewise.
	* reorg.c: Likewise.
	* resource.c: Likewise.
	* rtl.def: Likewise.
	* rtl.h: Likewise.
	* rtlanal.c: Likewise.
	* sched-deps.c: Likewise.
	* sched-ebb.c: Likewise.
	* sched-rgn.c: Likewise.
	* sel-sched-ir.c: Likewise.
	* sel-sched.c: Likewise.
	* shrink-wrap.c: Likewise.
	* simplify-rtx.c: Likewise.
	* symtab.c: Likewise.
	* target.def: Likewise.
	* toplev.c: Likewise.
	* tree-call-cdce.c: Likewise.
	* tree-cfg.c: Likewise.
	* tree-complex.c: Likewise.
	* tree-core.h: Likewise.
	* tree-eh.c: Likewise.
	* tree-inline.c: Likewise.
	* tree-loop-distribution.c: Likewise.
	* tree-nrv.c: Likewise.
	* tree-profile.c: Likewise.
	* tree-sra.c: Likewise.
	* tree-ssa-alias.c: Likewise.
	* tree-ssa-dce.c: Likewise.
	* tree-ssa-dom.c: Likewise.
	* tree-ssa-forwprop.c: Likewise.
	* tree-ssa-loop-im.c: Likewise.
	* tree-ssa-loop-ivcanon.c: Likewise.
	* tree-ssa-loop-ivopts.c: Likewise.
	* tree-ssa-loop-niter.c: Likewise.
	* tree-ssa-phionlycprop.c: Likewise.
	* tree-ssa-phiopt.c: Likewise.
	* tree-ssa-propagate.c: Likewise.
	* tree-ssa-threadedge.c: Likewise.
	* tree-ssa-threadupdate.c: Likewise.
	* tree-ssa-uninit.c: Likewise.
	* tree-ssanames.c: Likewise.
	* tree-streamer-out.c: Likewise.
	* tree.c: Likewise.
	* tree.h: Likewise.
	* vr-values.c: Likewise.

	gcc/ada/
	* exp_ch9.adb: Mechanically replace "can not" with "cannot".
	* libgnat/s-regpat.ads: Likewise.
	* par-ch4.adb: Likewise.
	* set_targ.adb: Likewise.
	* types.ads: Likewise.

	gcc/cp/
	* cp-tree.h: Mechanically replace "can not" with "cannot".
	* parser.c: Likewise.
	* pt.c: Likewise.

	gcc/fortran/
	* class.c: Mechanically replace "can not" with "cannot".
	* decl.c: Likewise.
	* expr.c: Likewise.
	* gfc-internals.texi: Likewise.
	* intrinsic.texi: Likewise.
	* invoke.texi: Likewise.
	* io.c: Likewise.
	* match.c: Likewise.
	* parse.c: Likewise.
	* primary.c: Likewise.
	* resolve.c: Likewise.
	* symbol.c: Likewise.
	* trans-array.c: Likewise.
	* trans-decl.c: Likewise.
	* trans-intrinsic.c: Likewise.
	* trans-stmt.c: Likewise.

	gcc/go/
	* go-backend.c: Mechanically replace "can not" with "cannot".
	* go-gcc.cc: Likewise.

	gcc/lto/
	* lto-partition.c: Mechanically replace "can not" with "cannot".
	* lto-symtab.c: Likewise.
	* lto.c: Likewise.

	gcc/objc/
	* objc-act.c: Mechanically replace "can not" with "cannot".

	libbacktrace/
	* backtrace.h: Mechanically replace "can not" with "cannot".

	libgcc/
	* config/c6x/libunwind.S: Mechanically replace "can not" with
	"cannot".
	* config/tilepro/atomic.h: Likewise.
	* config/vxlib-tls.c: Likewise.
	* generic-morestack-thread.c: Likewise.
	* generic-morestack.c: Likewise.
	* mkmap-symver.awk: Likewise.

	libgfortran/
	* caf/single.c: Mechanically replace "can not" with "cannot".
	* io/unit.c: Likewise.

	libobjc/
	* class.c: Mechanically replace "can not" with "cannot".
	* objc/runtime.h: Likewise.
	* sendmsg.c: Likewise.

	liboffloadmic/
	* include/coi/common/COIResult_common.h: Mechanically replace
	"can not" with "cannot".
	* include/coi/source/COIBuffer_source.h: Likewise.

	libstdc++-v3/
	* include/ext/bitmap_allocator.h: Mechanically replace "can not"
	with "cannot".

From-SVN: r267783
      Sandra Loosemore committed
    • re PR fortran/68426 (Simplification of SPREAD with a derived type element is unimplemented) · ee0b3cea 
      2019-01-09  Thomas Koenig  <tkoenig@gcc.gnu.org>

	PR fortran/68426
	* simplify.c (gfc_simplify_spread): Also simplify if the
	type of source is an EXPR_STRUCTURE.

2019-01-09  Thomas Koenig  <tkoenig@gcc.gnu.org>

	PR fortran/68426
	* gfortran.dg/spread_simplify_1.f90: New test.

From-SVN: r267781
      Thomas Koenig committed
    • i386-protos.h (ix86_expand_xorsign): New prototype. · 33142cf9 
      	* config/i386/i386-protos.h (ix86_expand_xorsign): New prototype.
	(ix86_split_xorsign): Ditto.
	* config/i386/i386.c (ix86_expand_xorsign): New function.
	(ix86_split_xorsign): Ditto.
	* config/i386/i386.md (UNSPEC_XORSIGN): New unspec.
	(xorsign<mode>3): New expander.
	(xorsign<mode>3_1): New insn_and_split pattern.
	* config/i386/sse.md (xorsign<mode>3): New expander.

testsuite/ChangeLog:

	* lib/target-supports.exp
	(check_effective_target_xorsign): Add i?86-*-* and x86_64-*-* targets.
	* gcc.target/i386/xorsign.c: New test.

From-SVN: r267779
      Uros Bizjak committed
    • Merge dmd upstream 6d5b853d3 · f3ed896c 
      Updates the copyright years of all d/dmd sources.

Reviewed-on: https://github.com/dlang/dmd/pull/9181

From-SVN: r267778
      Iain Buclaw committed
    • sparc.md (*tablejump_sp32): Merge into... · c1c9fcb6 
      	* config/sparc/sparc.md (*tablejump_sp32): Merge into...
	(*tablejump_sp64): Likewise.
	(*tablejump<P:mode>): ...this.
	(*call_address_sp32): Merge into...
	(*call_address_sp64): Likewise.
	(*call_address<P:mode>): ...this.
	(*call_symbolic_sp32): Merge into...
	(*call_symbolic_sp64): Likewise.
	(*call_symbolic<P:mode>): ...this.
	(call_value): Remove constraint and add predicate.
	(*call_value_address_sp32): Merge into...
	(*call_value_address_sp64): Likewise.
	(*call_value_address<P:mode>): ...this.
	(*call_value_symbolic_sp32): Merge into...
	(*call_value_symbolic_sp64): Likewise.
	(*call_value_symbolic<P:mode>): ...this.
	(*sibcall_symbolic_sp32): Merge into...
	(*sibcall_symbolic_sp64): Likewise.
	(*sibcall_symbolic<P:mode>): ...this.
	(sibcall_value): Remove constraint and add predicate.
	(*sibcall_value_symbolic_sp32): Merge into...
	(*sibcall_value_symbolic_sp64): Likewise.
	(*sibcall_value_symbolic<P:mode>): ...this.
	(window_save): Minor tweak.
	(*branch_sp32): Merge into...
	(*branch_sp64): Likewise.
	(*branch<P:mode>): ...this.

From-SVN: r267774
      Eric Botcazou committed
    • re PR target/84010 (problematic TLS code generation on 64-bit SPARC) · 4e8e8a9f 
      	PR target/84010
	* config/sparc/sparc.c (sparc_legitimize_tls_address): Only use Pmode
	consistently in TLS address generation and adjust code to the renaming
	of patterns.  Mark calls to __tls_get_addr as const.
	* config/sparc/sparc.md (tgd_hi22): Turn into...
	(tgd_hi22<P:mode>): ...this and use Pmode throughout.
	(tgd_lo10): Turn into...
	(tgd_lo10<P:mode>): ...this and use Pmode throughout.
	(tgd_add32): Merge into...
	(tgd_add64): Likewise.
	(tgd_add<P:mode>): ...this and use Pmode throughout.
	(tldm_hi22): Turn into...
	(tldm_hi22<P:mode>): ...this and use Pmode throughout.
	(tldm_lo10): Turn into...
	(tldm_lo10<P:mode>): ...this and use Pmode throughout.
	(tldm_add32): Merge into...
	(tldm_add64): Likewise.
	(tldm_add<P:mode>): ...this and use Pmode throughout.
	(tldm_call32): Merge into...
	(tldm_call64): Likewise.
	(tldm_call<P:mode>): ...this and use Pmode throughout.
	(tldo_hix22): Turn into...
	(tldo_hix22<P:mode>): ...this and use Pmode throughout.
	(tldo_lox10): Turn into...
	(tldo_lox10<P:mode>): ...this and use Pmode throughout.
	(tldo_add32): Merge into...
	(tldo_add64): Likewise.
	(tldo_add<P:mode>): ...this and use Pmode throughout.
	(tie_hi22): Turn into...
	(tie_hi22<P:mode>): ...this and use Pmode throughout.
	(tie_lo10): Turn into...
	(tie_lo10<P:mode>): ...this and use Pmode throughout.
	(tie_ld64): Use DImode throughout.
	(tie_add32): Merge into...
	(tie_add64): Likewise.
	(tie_add<P:mode>): ...this and use Pmode throughout.
	(tle_hix22_sp32): Merge into...
	(tle_hix22_sp64): Likewise.
	(tle_hix22<P:mode>): ...this and use Pmode throughout.
	(tle_lox22_sp32): Merge into...
	(tle_lox22_sp64): Likewise.
	(tle_lox22<P:mode>): ...this and use Pmode throughout.
	(*tldo_ldub_sp32): Merge into...
	(*tldo_ldub_sp64): Likewise.
	(*tldo_ldub<P:mode>): ...this and use Pmode throughout.
	(*tldo_ldub1_sp32): Merge into...
	(*tldo_ldub1_sp64): Likewise.
	(*tldo_ldub1<P:mode>): ...this and use Pmode throughout.
	(*tldo_ldub2_sp32): Merge into...
	(*tldo_ldub2_sp64): Likewise.
	(*tldo_ldub2<P:mode>): ...this and use Pmode throughout.
	(*tldo_ldsb1_sp32): Merge into...
	(*tldo_ldsb1_sp64): Likewise.
	(*tldo_ldsb1<P:mode>): ...this and use Pmode throughout.
	(*tldo_ldsb2_sp32): Merge into...
	(*tldo_ldsb2_sp64): Likewise.
	(*tldo_ldsb2<P:mode>): ...this and use Pmode throughout.
	(*tldo_ldub3_sp64): Use DImode throughout.
	(*tldo_ldsb3_sp64): Likewise.
	(*tldo_lduh_sp32): Merge into...
	(*tldo_lduh_sp64): Likewise.
	(*tldo_lduh<P:mode>): ...this and use Pmode throughout.
	(*tldo_lduh1_sp32): Merge into...
	(*tldo_lduh1_sp64): Likewise.
	(*tldo_lduh1<P:mode>): ...this and use Pmode throughout.
	(*tldo_ldsh1_sp32): Merge into...
	(*tldo_ldsh1_sp64): Likewise.
	(*tldo_ldsh1<P:mode>): ...this and use Pmode throughout.
	(*tldo_lduh2_sp64): Use DImode throughout.
	(*tldo_ldsh2_sp64): Likewise.
	(*tldo_lduw_sp32): Merge into...
	(*tldo_lduw_sp64): Likewise.
	(*tldo_lduw<P:mode>): ...this and use Pmode throughout.
	(*tldo_lduw1_sp64): Use DImode throughout.
	(*tldo_ldsw1_sp64): Likewise.
	(*tldo_ldx_sp64): Likewise.
	(*tldo_stb_sp32): Merge into...
	(*tldo_stb_sp64): Likewise.
	(*tldo_stb<P:mode>): ...this and use Pmode throughout.
	(*tldo_sth_sp32): Merge into...
	(*tldo_sth_sp64): Likewise.
	(*tldo_sth<P:mode>): ...this and use Pmode throughout.
	(*tldo_stw_sp32): Merge into...
	(*tldo_stw_sp64): Likewise.
	(*tldo_stw<P:mode>): ...this and use Pmode throughout.
	(*tldo_stx_sp64): Use DImode throughout.

From-SVN: r267771
      Eric Botcazou committed
    • [AArch64, 6/6] Enable BTI: Add configure option. · c7ff4f0f 
      This patch is part of a series that enables ARMv8.5-A in GCC and
adds Branch Target Identification Mechanism.

This patch is adding a new configure option for enabling BTI and
Return Address Signing by default.

*** gcc/ChangeLog ***

2018-01-09  Sudakshina Das  <sudi.das@arm.com>

	* config/aarch64/aarch64.c (aarch64_override_options): Add case to
	check configure option to set BTI and Return Address Signing.
	* configure.ac: Add --enable-standard-branch-protection and
	--disable-standard-branch-protection.
	* configure: Regenerated.
	* doc/install.texi: Document the same.

*** gcc/testsuite/ChangeLog ***

2018-01-09  Sudakshina Das  <sudi.das@arm.com>

	* gcc.target/aarch64/bti-1.c: Update test to not add command line
	option when configure with bti.
	* gcc.target/aarch64/bti-2.c: Likewise.
	* lib/target-supports.exp
	(check_effective_target_default_branch_protection):
	Add configure check for --enable-standard-branch-protection.

From-SVN: r267770
      Sudakshina Das committed
    • [AArch64, 5/6] Enable BTI : Add new pass for BTI. · b5f794b4 
      This patch is part of a series that enables ARMv8.5-A in GCC and
adds Branch Target Identification Mechanism.

This patch adds a new pass called "bti" which is triggered by the command
line argument -mbranch-protection whenever "bti" is turned on.

The pass iterates through the instructions and adds appropriated BTI
instructions based on the following:
  * Add a new "BTI C" at the beginning of a function, unless its already
    protected by a "PACIASP". We exempt the functions that are only called
    directly.
  * Add a new "BTI J" for every target of an indirect jump, jump table
    targets, non-local goto targets or labels that might be referenced by
    variables, constant pools, etc (NOTE_INSN_DELETED_LABEL).

Since we have already changed the use of indirect tail calls to only x16 and
x17, we do not have to use "BTI JC".
(check patch 3/6).

*** gcc/ChangeLog ***

2018-01-09  Sudakshina Das  <sudi.das@arm.com>
	    Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>

	* config.gcc (aarch64*-*-*): Add aarch64-bti-insert.o.
	* gcc/config/aarch64/aarch64.h: Update comment for TRAMPOLINE_SIZE.
	* config/aarch64/aarch64.c (aarch64_asm_trampoline_template): Update
	if bti is enabled.
	* config/aarch64/aarch64-bti-insert.c: New file.
	* config/aarch64/aarch64-passes.def (INSERT_PASS_BEFORE): Insert bti
	pass.
	* config/aarch64/aarch64-protos.h (make_pass_insert_bti): Declare the
	new bti pass.
	* config/aarch64/aarch64.md (unspecv): Add UNSPECV_BTI_NOARG,
	UNSPECV_BTI_C, UNSPECV_BTI_J and UNSPECV_BTI_JC.
	(bti_noarg, bti_j, bti_c, bti_jc): New define_insns.
	* config/aarch64/t-aarch64: Add rule for aarch64-bti-insert.o.

*** gcc/testsuite/ChangeLog ***

2018-01-09  Sudakshina Das  <sudi.das@arm.com>

	* gcc.target/aarch64/bti-1.c: New test.
	* gcc.target/aarch64/bti-2.c: New test.
	* gcc.target/aarch64/bti-3.c: New test.
	* lib/target-supports.exp
	(check_effective_target_aarch64_bti_hw): Add new check for BTI hw.

Co-Authored-By: Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>

From-SVN: r267769
      Sudakshina Das committed
    • [AArch64, 4/6] Enable BTI: Add new <type> to -mbranch-protection. · 30afdf34 
      This patch is part of a series that enables ARMv8.5-A in GCC and
adds Branch Target Identification Mechanism.

This pass updates the CLI of -mbranch-protection to add "bti" as a new
type of branch protection and also add it its definition of "none" and
"standard". The option does not really do anything functional.
The functional changes are in the next patch. I am initializing the target
variable aarch64_enable_bti to 2 since I am also adding a configure option
in a later patch and a value different from 0 and 1 would help identify if its
already been updated.

*** gcc/ChangeLog ***

2018-01-09  Sudakshina Das  <sudi.das@arm.com>

	* config/aarch64/aarch64-protos.h (aarch64_bti_enabled): Declare.
	* config/aarch64/aarch64.c (aarch64_handle_no_branch_protection):
	Disable bti for -mbranch-protection=none.
	(aarch64_handle_standard_branch_protection): Enable bti for
	-mbranch-protection=standard.
	(aarch64_handle_bti_protection): Enable bti for "bti" in the string to
	-mbranch-protection.
	(aarch64_bti_enabled): Check if bti is enabled.
	* config/aarch64/aarch64.opt: Declare target variable.
	* doc/invoke.texi: Add bti to the -mbranch-protection documentation.

From-SVN: r267768
      Sudakshina Das committed
    • [AArch64, 3/6] Restrict indirect tail calls to x16 and x17 · 901e66e0 
      This patch is part of a series that enables ARMv8.5-A in GCC and
adds Branch Target Identification Mechanism.

This patch changes the registers that are allowed for indirect tail calls.
We are choosing to restrict these to only x16 or x17.

Indirect tail calls are special in a way that they convert a call statement
(BLR instruction) to a jump statement (BR instruction). For the best possible
use of Branch Target Identification Mechanism, we would like to place a
"BTI C" (call) at the beginning of the function which is only
compatible with BLRs and BR X16/X17. In order to make indirect tail calls
compatible with this scenario, we are restricting the TAILCALL_ADDR_REGS.

In order to use x16/x17 for this purpose, we also had to change the use
of these registers in the epilogue/prologue handling. For this purpose
we are now using x12 and x13 named as EP0_REGNUM and EP1_REGNUM as
scratch registers for epilogue and prologue.

*** gcc/ChangeLog***

2018-01-09  Sudakshina Das  <sudi.das@arm.com>

	* config/aarch64/aarch64.c (aarch64_expand_prologue): Use new
	epilogue/prologue scratch registers EP0_REGNUM and EP1_REGNUM.
	(aarch64_expand_epilogue): Likewise.
	(aarch64_output_mi_thunk): Likewise
	* config/aarch64/aarch64.h (REG_CLASS_CONTENTS): Change
	TAILCALL_ADDR_REGS to x16 and x17.
	* config/aarch64/aarch64.md: Define EP0_REGNUM and EP1_REGNUM.

*** gcc/testsuite/ChangeLog ***

2018-01-09  Sudakshina Das  <sudi.das@arm.com>

	* gcc.target/aarch64/test_frame_17.c: Update to check for EP0_REGNUM
	instead of IP0_REGNUM and add test case.

From-SVN: r267767
      Sudakshina Das committed
    • [AArch64, 2/6] Add new arch command line feaures from ARMv8.5-A · 9b4247de 
      This patch is part of a series that enables ARMv8.5-A in GCC and
adds Branch Target Identification Mechanism.

This patch add all the command line feature that are added by ARMv8.5.
Optional extensions to armv8.5-a:
+rng : Random number Generation Instructions.
+memtag : Memory Tagging Extension.

ARMv8.5-A features that are optional to older arch:
+sb : Speculation barrier instruction.
+ssbs: Speculative Store Bypass Safe instruction.
+predres: Execution and Data Prediction Restriction instructions.

All of the above only effect the assembler and have already gone in the
trunk of binutils.

*** gcc/ChangeLog ***

2018-01-09  Sudakshina Das  <sudi.das@arm.com>

	* config/aarch64/aarch64-option-extensions.def: Define
	AARCH64_OPT_EXTENSION for memtag, rng, sb, ssbs and predres.
	* gcc/config/aarch64/aarch64.h (AARCH64_FL_RNG): New.
	(AARCH64_FL_MEMTAG, ARCH64_FL_SB, AARCH64_FL_SSBS): New.
	(AARCH64_FL_PREDRES): New.
	(AARCH64_FL_FOR_ARCH8_5): Add AARCH64_FL_SB, AARCH64_FL_SSBS and
	AARCH64_FL_PREDRES by default.
	* gcc/doc/invoke.texi: Document rng, memtag, sb, ssbs and predres.

From-SVN: r267766
      Sudakshina Das committed
    • [AArch64, 1/6] Enable ARMv8.5-A in gcc · 59beeb62 
      This patch is part of a series that enables ARMv8.5-A in GCC and
adds Branch Target Identification Mechanism.

*** gcc/ChangeLog ***

2018-01-09  Sudakshina Das  <sudi.das@arm.com>

	* config/aarch64/aarch64-arches.def: Define AARCH64_ARCH for
	ARMv8.5-A.
	* gcc/config/aarch64/aarch64.h (AARCH64_FL_V8_5): New.
	(AARCH64_FL_FOR_ARCH8_5, AARCH64_ISA_V8_5): New.
	* gcc/doc/invoke.texi: Document ARMv8.5-A.

From-SVN: r267765
      Sudakshina Das committed
    • [Aarch64][SVE] Add copysign and xorsign support · 6c9c7b73 
      This patch adds support for copysign and xorsign builtins to SVE. With the new
expands, they can be vectorized using bitwise logical operations.

I tested this patch in an aarch64 machine bootstrapping the compiler and
running the checks.

2019-01-09  Alejandro Martinez  <alejandro.martinezvicente@arm.com>

	* config/aarch64/aarch64-sve.md (copysign<mode>3): New define_expand.
	(xorsign<mode>3): Likewise.

2019-01-09  Alejandro Martinez  <alejandro.martinezvicente@arm.com>

	* gcc.target/aarch64/sve/copysign_1.c: New test for SVE vectorized
	copysign.
	* gcc.target/aarch64/sve/copysign_1_run.c: Likewise.
	* gcc.target/aarch64/sve/xorsign_1.c: New test for SVE vectorized
	xorsign.
	* gcc.target/aarch64/sve/xorsign_1_run.c: Likewise.

From-SVN: r267764
      Alejandro Martinez committed