gcc/fortran/
	* openmp.c (match_oacc_clause_gang): Rename to ...
	(match_oacc_clause_gwv): this.  Add support for OpenACC worker and
	vector clauses.
	(gfc_match_omp_clauses): Use match_oacc_clause_gwv for
	OMP_CLAUSE_{GANG,WORKER,VECTOR}.  Propagate any MATCH_ERRORs for
	invalid OMP_CLAUSE_{ASYNC,WAIT,GANG,WORKER,VECTOR} clauses.
	(gfc_match_oacc_wait): Propagate MATCH_ERROR for invalid
	oacc_expr_lists.  Adjust the first and needs_space arguments to
	gfc_match_omp_clauses.

	gcc/testsuite/
	* gfortran.dg/goacc/asyncwait-2.f95: Updated expected diagnostics.
	* gfortran.dg/goacc/asyncwait-3.f95: Likewise.
	* gfortran.dg/goacc/asyncwait-4.f95: Add test coverage.

From-SVN: r237854

2016-06-29  Richard Biener  <rguenther@suse.de>

	PR middle-end/15256
	* gcc.dg/tree-ssa/forwprop-34.c: New testcase.

From-SVN: r237852

This makes things consistent across big.LITTLE cores, improves performance of
benchmarks with tight loops and reduces performance variations due to small
changes in code layout.

    gcc/
        * config/aarch64/aarch64.c (cortexa53_tunings):
        Increase loop alignment to 8.  Set function alignment to 16.
        (cortexa35_tunings): Likewise.
        (cortexa57_tunings): Increase loop alignment to 8.
        (cortexa72_tunings): Likewise.
        (cortexa73_tunings): Likewise.

From-SVN: r237851

	PR ada/48835
	PR ada/61954
	* gcc-interface/gigi.h (enum standard_datatypes): Add ADT_realloc_decl
	(realloc_decl): New macro.
	* gcc-interface/decl.c (gnat_to_gnu_entity) <E_Variable>: Use local
	variable for the entity type and translate it as void pointer if the
	entity has convention C.
	(gnat_to_gnu_entity) <E_Function>: If this is not a definition and the
	external name matches that of malloc_decl or realloc_decl, return the
	correspoding node directly.
	(gnat_to_gnu_subprog_type): Likewise for parameter and return types.
	* gcc-interface/trans.c (gigi): Initialize void_list_node here, not...
	Initialize realloc_decl.
	* gcc-interface/utils.c (install_builtin_elementary_types): ...here.
	(build_void_list_node): Delete.
	* gcc-interface/utils2.c (known_alignment) <CALL_EXPR>: Return the
	alignment of the system allocator for malloc_decl and realloc_decl.
	Do not take alignment from void pointer types either.

From-SVN: r237850

testsuite/
	* gcc.target/arm/aapcs/neon-vect10.c: Require
	-mfloat-ab=hard.  Replace arm_neon_fp16_ok with arm_neon_fp16_hw.
	* gcc.target/arm/aapcs/neon-vect9.c: Likewise.
	* gcc.target/arm/aapcs/vfp18.c: Likewise.
	* gcc.target/arm/aapcs/vfp19.c: Likewise.
	* gcc.target/arm/aapcs/vfp20.c: Likewise.
	* gcc.target/arm/aapcs/vfp21.c: Likewise.
	* gcc.target/arm/fp16-aapcs-1.c: Require
	-mfloat-ab=hard.  Also simplify the test.
	* gcc.target/arm/fp16-aapcs-2.c: New.

From-SVN: r237849

	* gcc-interface/misc.c (LANG_HOOKS_WARN_UNUSED_GLOBAL_DECL): Reorder.
	(LANG_HOOKS_INIT_TS): Likewise.

From-SVN: r237848

gcc/
	* doc/sourcebuild.texi (Effective-Target keywords): Add entries
	for arm_fp16_ok and arm_fp16_hw.
	(Add Options): Add entries for arm_fp16, arm_fp16_ieee and
	arm_fp16_alternative.

testsuite/
	* lib/target-supports.exp (add_options_for arm_fp16): Reword
	comment.
	(add_options_for_arm_fp16_ieee): New.
	(add_options_for_arm_fp16_alternative): New.
	(effective_target_arm_fp16_ok_nocache): Add to comment.  Fix a
	long-line.
	(effective_target_arm_fp16_hw): New.

From-SVN: r237847

gcc/

	PR tree-optimization/71655
	* tree-vect-stmts.c (vectorizable_comparison): Swap definition
	types when swapping operands.

gcc/testsuite/

	PR tree-optimization/71655
	* g++.dg/pr71655.C: New test.

From-SVN: r237846

	PR middle-end/71585
	* common.opt (flag_stack_protect): Mark the flag as optimization
	flag.
	* ipa-inline-transform.c (inline_call): Remove unnecessary call
	of build_optimization_node.
	* gcc.dg/pr71585.c: New test.
	* gcc.dg/pr71585-2.c: New test.
	* gcc.dg/pr71585-3.c: New test.

From-SVN: r237845

gcc/

2016-06-29  Yuri Rumyantsev  <ysrumyan@gmail.com>

	PR tree-optimization/70729
	* tree-ssa-loop-im.c (ref_indep_loop_p_1): Consider memory reference as
	independent in loops having positive safelen value.
	* tree-vect-loop.c (vect_transform_loop): Clear-up safelen value since
	it may be not valid after vectorization.

gcc/testsuite/

2016-06-29  Yuri Rumyantsev  <ysrumyan@gmail.com>

	PR tree-optimization/70729
	* g++.dg/vect/pr70729.cc: New test.

From-SVN: r237844

	gcc/c/
	* c-parser.c (c_parser_pragma) <PRAGMA_OMP_CANCELLATION_POINT>:
	Move pragma context checking into...
	(c_parser_omp_cancellation_point): ... here, and improve
	diagnostic messages.
	* c-typeck.c (c_finish_omp_cancel)
	(c_finish_omp_cancellation_point): Improve diagnostic messages.
	gcc/cp/
	* parser.c (cp_parser_pragma) <PRAGMA_OMP_CANCELLATION_POINT>:
	Move pragma context checking into...
	(cp_parser_omp_cancellation_point): ... here, and improve
	diagnostic messages.
	* semantics.c (finish_omp_cancel, finish_omp_cancellation_point):
	Improve diagnostic messages.
	gcc/testsuite/
	* c-c++-common/gomp/cancel-1.c: Extend.

From-SVN: r237843

	gcc/c-family/
	* c-pragma.h (enum pragma_kind): Rename
	PRAGMA_OMP_DECLARE_REDUCTION to PRAGMA_OMP_DECLARE.  Adjust all
	users.

From-SVN: r237842

	PR tree-optimization/71625
	* tree-ssa-strlen.c (get_addr_stridx): Add PTR argument.  Assume list
	is sorted by ascending list->offset.  If PTR is non-NULL and there is
	previous strinfo, call get_stridx_plus_constant.
	(get_stridx): Pass exp as second argument to get_addr_stridx.
	(addr_stridxptr): Add missing list = list->next, so that there can be
	more than one entries in the list.  Bump limit from 16 to 32.  Ensure
	the list is sorted by ascending list->offset.
	(get_stridx_plus_constant): Adjust so that it can be also called with
	ADDR_EXPR instead of SSA_NAME as PTR.
	(handle_char_store): Pass NULL_TREE as second argument to
	get_addr_stridx.

	* gcc.dg/strlenopt-28.c: New test.

From-SVN: r237841

2016-06-29  Richard Biener  <rguenther@suse.de>

	PR rtl-optimization/68961
	* simplify-rtx.c (simplify_subreg): Handle VEC_CONCAT like CONCAT.

From-SVN: r237840

2016-06-29  Richard Biener  <rguenther@suse.de>

	PR middle-end/71002
	* alias.c (component_uses_parent_alias_set_from): Handle
	type punning through union accesses by using the union alias set.
	* gimple.c (gimple_get_alias_set): Remove union type punning case.

	c-family/
	* c-common.c (c_common_get_alias_set): Remove union type punning case.
	
	fortran/
	* f95-lang.c (LANG_HOOKS_GET_ALIAS_SET): Remove (un-)define.
	(gfc_get_alias_set): Remove.

	* g++.dg/torture/pr71002.C: Adjust testcase.

From-SVN: r237839

2016-07-29  Richard Biener  <rguenther@suse.de>

	* match.pd ((T)(T2)x -> (T)x): Remove restriction on final
	precision not matching mode precision.

From-SVN: r237838

	* config/pa/pa.md (call_symref_64bit_post_reload): Don't call
	pa_output_arg_descriptor.
	(call_val_symref_64bit_post_reload): Likewise.
	(call_val_powf_64bit_post_reload): Likewise.
	(sibcall_internal_symref_64bit): Likewise.
	(sibcall_value_internal_symref_64bit): Likewise.

From-SVN: r237837

From-SVN: r237836

	PR c/71685
	* c-typeck.c (c_build_qualified_type): Don't clear
	C_TYPE_INCOMPLETE_VARS for the main variant.

	* gcc.dg/pr71685.c: New test.

From-SVN: r237830

gcc/c/ChangeLog:

	PR c/71552
	* c-typeck.c (output_init_element): Diagnose incompatible types
	before non-constant initializers.

gcc/testsuite/ChangeLog:

	PR c/71552
	* gcc.dg/init-bad-9.c: New test.

From-SVN: r237829

2016-06-28  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>

	* gcc.target/powerpc/abs128-1.c: Require VSX.
	* gcc.target/powerpc/copysign128-1.c: Likewise.
	* gcc.target/powerpc/inf128-1.c: Likewise.
	* gcc.target/powerpc/nan128-1.c: Likewise.

From-SVN: r237828

re PR middle-end/71626 (ICE at -O1 and above on x86_64-linux-gnu (in output_constant_pool_2, at varasm.c:3837))

	PR middle-end/71626
	* config/i386/i386.c (ix86_expand_vector_move): For SUBREG of
	a constant, force its SUBREG_REG into memory or register instead
	of whole op1.

	* gcc.c-torture/execute/pr71626-1.c: New test.
	* gcc.c-torture/execute/pr71626-2.c: New test.

From-SVN: r237826

	PR target/58655
	* config/avr/avr.opt (-mfract-convert-truncate): Update description.
	* doc/invoke.texi (AVR Options): Document it.

From-SVN: r237825

gcc/ChangeLog
	* config/tilegx/linux.h: Do not include arch/icache.h
	(CLEAR_INSN_CACHE): Provide inlined definition directly.
	* config/tilepro/linux.h: Do not include arch/icache.h
	(CLEAR_INSN_CACHE): Provide inlined definition directly.

libgcc/ChangeLog
	* config/tilepro/atomic.h: Do not include arch/spr_def.h and
	asm/unistd.h.
	(SPR_CMPEXCH_VALUE): Define for tilegx.
	(__NR_FAST_cmpxchg): Define for tilepro.
	(__NR_FAST_atomic_update): Define for tilepro.
	(__NR_FAST_cmpxchg64): Define for tilepro.

From-SVN: r237824

	PR target/71656
	* gcc.target/powerpc/pr71656-2.c: Fix syntax errors.

From-SVN: r237823

This patch fixes a bug in the bswap pass.  In big-endian BIT_FIELD_REF uses
big-endian bit numbering so we need to adjust the bit position.
The existing version could potentially generate incorrect code however GCC
doesn't emit a BIT_FIELD_REF to access the low byte in a register, so the
symbolic number never matches in big-endian.

    gcc/
	* tree-ssa-math-opts.c (find_bswap_or_nop_1): Adjust bitnumbering
	for big-endian BIT_FIELD_REF.

From-SVN: r237822

	* config/rs6000/rs6000.md ('type' attribute): Add htmsimple/dfp types.
	('size' attribute): Add '128'.
	Include power9.md.
	(*mov<mode>_hardfloat32, *mov<mode>_hardfloat64, *movdi_internal32,
	*movdi_internal64, *movdf_update1): Set size attribute to '64'.
	(add<mode>3, sub<mode>3, mul<mode>3, div<mode>3, sqrt<mode>2,
	copysign<mode>3, neg<mode>2_hw, abs<mode>2_hw, *nabs<mode>2_hw,
	*fma<mode>4_hw, *fms<mode>4_hw, *nfma<mode>4_hw, *nfms<mode>4_hw,
	extend<SFDF:mode><IEEE128:mode>2_hw, trunc<mode>df2_hw,
	*xscvqp<su>wz_<mode>, *xscvqp<su>dz_<mode>, *xscv<su>dqp_<mode>,
	*trunc<mode>df2_odd): Set size attribute to '128'.
	(*cmp<mode>_hw): Change type to veccmp and set size attribute to '128'.
	* config/rs6000/power6.md (power6-fp): Include dfp type.
	* config/rs6000/power7.md (power7-fp): Likewise.
	* config/rs6000/power8.md (power8-fp): Likewise.
	* config/rs6000/power9.md: New file.
	* config/rs6000/t-rs6000 (MD_INCLUDES): Add power9.md.
	* config/rs6000/htm.md (*tabort, *tabort<wd>c, *tabort<wd>ci,
	*trechkpt, *treclaim, *tsr, *ttest): Change type attribute to
	htmsimple.
	* config/rs6000/dfp.md (extendsddd2, truncddsd2, extendddtd2,
	trunctddd2, adddd3, addtd3, subdd3, subtd3, muldd3, multd3, divdd3,
	divtd3, *cmpdd_internal1, *cmptd_internal1, floatdidd2, floatditd2,
	ftruncdd2, fixdddi2, ftrunctd2, fixtddi2, dfp_ddedpd_<mode>,
	dfp_denbcd_<mode>, dfp_dxex_<mode>, dfp_diex_<mode>, dfp_dscli_<mode>,
	dfp_dscri_<mode>): Change type attribute to dfp.
	* config/rs6000/crypto.md (crypto_vshasigma<CR_char>): Change type
	attribute to vecsimple.
	* config/rs6000/rs6000.c (power9_cost): Update costs, cache size
	and prefetch streams.
	(rs6000_option_override_internal): Remove temporary code setting
	tuning to power8.  Don't set rs6000_sched_groups for power9.
	(last_scheduled_insn): Change to rtx_insn *.
	(divide_cnt, vec_load_pendulum): New variables.
	(rs6000_adjust_cost): Add Power9 to test for store->load separation.
	(rs6000_issue_rate): Set issue rate for Power9.
	(is_power9_pairable_vec_type): New.
	(power9_sched_reorder2): New.
	(rs6000_sched_reorder2): Call new function for Power9 specific
	reordering.
	(insn_must_be_first_in_group): Remove Power9.
	(insn_must_be_last_in_group): Likewise.
	(force_new_group): Likewise.
	(rs6000_sched_init): Fix initialization of last_scheduled_insn.
	Initialize divide_cnt/vec_load_pendulum.
	(_rs6000_sched_context, rs6000_init_sched_context,
	rs6000_set_sched_context): Handle context save/restore of new
	variables.

From-SVN: r237820

tree-ssa-alias.c (nonoverlapping_component_refs_of_decl_p): Properly handle DECL_BIT_FIELD_REPRESENTATIVE occuring as COMPONENT_REF operand.

2016-06-28  Richard Biener  <rguenther@suse.de>

	* tree-ssa-alias.c (nonoverlapping_component_refs_of_decl_p):
	Properly handle DECL_BIT_FIELD_REPRESENTATIVE occuring as
	COMPONENT_REF operand.
	(nonoverlapping_component_refs_p): Likewise.
	* stor-layout.c (start_bitfield_representative): Mark
	DECL_BIT_FIELD_REPRESENTATIVE as DECL_NONADDRESSABLE_P.

From-SVN: r237818

	* Makefile.in: Don't cat ../stage_current if it does not exist.
c/
	* Make-lang.in: Don't cat ../stage_current if it does not exist.
cp/
	* Make-lang.in: Don't cat ../stage_current if it does not exist.
lto/
	* Make-lang.in: Don't cat ../stage_current if it does not exist.

From-SVN: r237817

	* doc/extend.texi (__builtin_add_overflow_p): Clarify behavior when
	last argument is a bit-field.

From-SVN: r237816

re PR rtl-optimization/71673 (FAIL: c-c++-common/torture/builtin-arith-overflow-p-19.c -O2  (internal compiler error))

	PR rtl-optimization/71673
	* internal-fn.c (expand_arith_overflow_result_store): Use
	OPTAB_LIB_WIDEN instead of OPTAB_DIRECT as last argument to
	expand_simple_binop.

From-SVN: r237815

	PR middle-end/66867
	* builtins.c (expand_ifn_atomic_compare_exchange_into_call,
	expand_ifn_atomic_compare_exchange): New functions.
	* internal-fn.c (expand_ATOMIC_COMPARE_EXCHANGE): New function.
	* tree.h (build_call_expr_internal_loc): Rename to ...
	(build_call_expr_internal_loc_array): ... this.  Fix up type of
	last argument.
	* internal-fn.def (ATOMIC_COMPARE_EXCHANGE): New internal fn.
	* predict.c (expr_expected_value_1): Handle IMAGPART_EXPR of
	ATOMIC_COMPARE_EXCHANGE result.
	* builtins.h (expand_ifn_atomic_compare_exchange): New prototype.
	* gimple-fold.h (optimize_atomic_compare_exchange_p,
	fold_builtin_atomic_compare_exchange): New prototypes.
	* gimple-fold.c (optimize_atomic_compare_exchange_p,
	fold_builtin_atomic_compare_exchange): New functions..
	* tree-ssa.c (execute_update_addresses_taken): If
	optimize_atomic_compare_exchange_p, ignore &var in 2nd argument
	of call when finding addressable vars, and if such var becomes
	non-addressable, call fold_builtin_atomic_compare_exchange.

From-SVN: r237814

The splitter for ashdi3_extswsli_dot for cr0 with memory uses emit_insn
gen_ashdi3_extswsli_dot, which does not work because that emits a scratch,
while the splitter runs after reload so there should be a real register
instead.  We can laboriously fix that up, or emit using
gen_ashdi3_extswsli_dot2 instead.  This patch does the latter.


	PR target/71670
	* config/rs6000/rs6000.md (ashdi3_extswsli_dot): Use
	gen_ashdi3_extswsli_dot2 instead of gen_ashdi3_extswsli_dot.

gcc/testsuite/
	PR target/71670
	* gcc.target/powerpc/pr71670.c: New testcase.

From-SVN: r237813

	* config/rs6000/rs6000.md ('type' attribute): Add
	veclogical,veccmpfx,vecexts,vecmove insn types.
	(*abs<mode>2_fpr, *nabs<mode>2_fpr, *neg<mode>2_fpr, *extendsfdf2_fpr,
	copysign<mode>3_fcpsgn, trunc<mode>df2_internal1, neg<mode>2_internal,
	p8_fmrgow_<mode>, pack<mode>): Change type to fpsimple.
	(*xxsel<mode>, copysign<mode>3_hard, neg<mode>2_hw, abs<mode>2_hw,
	*nabs<mode>2_hw): Change type to vecmove.
	(*and<mode>3_internal, *bool<mode>3_internal, *boolc<mode>3_internal,
	*boolcc<mode>3_internal, *eqv<mode>3_internal,
	*one_cmpl<mode>3_internal, *ieee_128bit_vsx_neg<mode>2_internal,
	*ieee_128bit_vsx_abs<mode>2_internal,
	*ieee_128bit_vsx_nabs<mode>2_internal, extendkftf2, trunctfkf2,
	*ieee128_mfvsrd_64bit, *ieee128_mfvsrd_32bit, *ieee128_mtvsrd_64bit,
	*ieee128_mtvsrd_32bit): Change type to veclogical.
	(mov<mode>_hardfloat, *mov<mode>_hardfloat32, *mov<mode>_hardfloat64,
	*movdi_internal32, *movdi_internal64): Update insn types.
	* config/rs6000/vsx.md (*vsx_le_undo_permute_<mode>,
	vsx_extract_<mode>): Change type to veclogical.
	(*vsx_xxsel<mode>, *vsx_xxsel<mode>_uns): Change type to vecmove.
	(vsx_sign_extend_qi_<mode>, *vsx_sign_extend_hi_<mode>,
	*vsx_sign_extend_si_v2di): Change type to vecexts.
	* config/rs6000/altivec.md (*altivec_mov<mode>, *altivec_movti): Change
	type to veclogical.
	(*altivec_eq<mode>, *altivec_gt<mode>, *altivec_gtu<mode>,
	*altivec_vcmpequ<VI_char>_p, *altivec_vcmpgts<VI_char>_p,
	*altivec_vcmpgtu<VI_char>_p): Change type to veccmpfx.
	(*altivec_vsel<mode>, *altivec_vsel<mode>_uns): Change type to vecmove.
	* config/rs6000/dfp.md (*negdd2_fpr, *absdd2_fpr, *nabsdd2_fpr,
	negtd2, *abstd2_fpr, *nabstd2_fpr): Change type to fpsimple.
	* config/rs6000/40x.md (ppc405-float): Add fpsimple.
	* config/rs6000/440.md (ppc440-fp): Add fpsimple.
	* config/rs6000/476.md (ppc476-fp): Add fpsimple.
	* config/rs6000/601.md (ppc601-fp): Add fpsimple.
	* config/rs6000/603.md (ppc603-fp): Add fpsimple.
	* config/rs6000/6xx.md (ppc604-fp): Add fpsimple.
	* config/rs6000/7xx.md (ppc750-fp): Add fpsimple.
	(ppc7400-vecsimple): Add veclogical, vecmove, veccmpfx.
	* config/rs6000/7450.md (ppc7450-fp): Add fpsimple.
	(ppc7450-vecsimple): Add veclogical, vecmove.
	(ppc7450-veccmp): Add veccmpfx.
	* config/rs6000/8540.md (ppc8540_simple_vector): Add veclogical,
	vecmove.
	(ppc8540_vector_compare): Add veccmpfx.
	* config/rs6000/a2.md (ppca2-fp): Add fpsimple.
	* config/rs6000/cell.md (cell-fp): Add fpsimple.
	(cell-vecsimple): Add veclogical, vecmove.
	(cell-veccmp): Add veccmpfx.
	* config/rs6000/e300c2c3.md (ppce300c3_fp): Add fpsimple.
	* config/rs6000/e6500.md (e6500_vecsimple): Add veclogical, vecmove,
	veccmpfx.
	* config/rs6000/mpc.md (mpccore-fp): Add fpsimple.
	 * config/rs6000/power4.md (power4-fp): Add fpsimple.
	(power4-vecsimple): Add veclogical, vecmove.
	(power4-veccmp): Add veccmpfx.
	* config/rs6000/power5.md (power5-fp): Add fpsimple.
	* config/rs6000/power6.md (power6-fp): Add fpsimple.
	(power6-vecsimple): Add veclogical, vecmove.
	(power6-veccmp): Add veccmpfx.
	* config/rs6000/power7.md (power7-fp): Add fpsimple.
	(power7-vecsimple): Add veclogical, vecmove, veccmpfx.
	* config/rs6000/power8.md (power8-fp): Add fpsimple.
	(power8-vecsimple): Add veclogical, vecmove, veccmpfx.
	* config/rs6000/rs64.md (rs64a-fp): Add fpsimple.
	* config/rs6000/titan.md (titan_fp): Add fpsimple.
	* config/rs6000/xfpu.md (fp-default, fp-addsub-s, fp-addsub-d): Add
	fpsimple.
	* config/rs6000/rs6000.c (rs6000_adjust_cost): Add TYPE_FPSIMPLE.

From-SVN: r237812

gcc/
	PR target/71656
	* config/rs6000/rs6000-cpus.def (ISA_3_0_MASKS_SERVER): Add
	OPTION_MASK_P9_DFORM_VECTOR.
	* config/rs6000/rs6000.c (rs6000_option_override_internal): Do not
	disable -mpower9-dform-vector when using reload.
	(quad_address_p): Remove 'gpr_p' argument and all associated code.
	New 'strict' argument.  Update all callers.  Add strict addressing
	support.
	(rs6000_legitimate_offset_address_p): Remove call to
	virtual_stack_registers_memory_p.
	(rs6000_legitimize_reload_address): Add quad address support.
	(rs6000_legitimate_address_p): Move call to quad_address_p above
	call to virtual_stack_registers_memory_p.  Adjust quad_address_p args
	to account for new strict usage.
	(rs6000_output_move_128bit): Adjust quad_address_p args to account
	for new strict usage.
	* config/rs6000/predicates.md (quad_memory_operand): Likewise.

gcc/testsuite/
	PR target/71656
	* gcc.target/powerpc/pr71656-1.c: New test.
	* gcc.target/powerpc/pr71656-2.c: New test.

From-SVN: r237811

From-SVN: r237810

vsx.md (UNSPEC_P9_MEMORY): New unspec to support loading and storing byte/half-word values in the vector...

[gcc]
2016-06-27  Michael Meissner  <meissner@linux.vnet.ibm.com>

	* config/rs6000/vsx.md (UNSPEC_P9_MEMORY): New unspec to support
	loading and storing byte/half-word values in the vector registers.
	(vsx_sign_extend_hi_<mode>): Enable the generator function.
	(p9_lxsi<wd>zx): New insns to load zero-extended bytes and
	half-words on ISA 3.0 to the vector registers.
	(p9_stxsi<wd>zx): New insns to store zero-extended bytes and
	half-words on ISA 3.0 from the vector registers.
	* config/rs6000/rs6000.md (FP_ISA3): New iterator to optimize
	converting char/half-word items to floating point on ISA 3.0.
	(float<QHI:mode><FP_ISA3:mode>2): On ISA 3.0 generate the lxsihzx
	and lxsibzx instructions if we are converting an 8-bit or 16-bit
	item from memory to floating point.
	(float<QHI:mode><FP_ISA3:mode>2_internal): Likewise.
	(floatuns<QHI:mode><FP_ISA3:mode>2): Likewise.
	(floatuns<QHI:mode><FP_ISA3:mode>2_internal): Likewise.
	(fix_trunc<SFDF:mode><QHI:mode>2): On ISA 3.0 generate the stxsihx
	and stxsibx instructions to store floating point values converted
	to 8 or 16-bit integers.
	(fixuns_trunc<mode>si2): Likewise.

[gcc/testsuite]
2016-06-27  Michael Meissner  <meissner@linux.vnet.ibm.com>

	* gcc.target/powerpc/p9-fpcvt-1.c: New test to test ISA 3.0 load
	byte/half-word to vector registers and store byte/half-word from
	vector register instructions.
	* gcc.target/powerpc/p9-fpcvt-2.c: Likewise.

From-SVN: r237806

re PR libstdc++/71640 (include/c++/7.0.0/bits/hashtable.h:293:7: error: too many template parameters in template redeclaration)

2016-06-27  François Dumont  <fdumont@gcc.gnu.org>

	PR libstdc++/71640
	* include/bits/hashtable.h: Remove _Unique_keya parameter in _Insert
	friend declaration.

From-SVN: r237803

2016-06-27  Christophe Lyon  <christophe.lyon@linaro.org>

	* gcc.target/aarch64/advsimd-intrinsics/vget_lane.c: Add ifdef
	around fp16 code.
	* gcc.target/aarch64/advsimd-intrinsics/vreinterpret.c: Likewise.
	* gcc.target/aarch64/advsimd-intrinsics/vreinterpret_p128.c: Likewise.
	* gcc.target/aarch64/advsimd-intrinsics/vreinterpret_p64.c: Likewise.
	* gcc.target/aarch64/advsimd-intrinsics/vstX_lane.c: Likewise.
	* gcc.target/aarch64/advsimd-intrinsics/vld2_lane_f16_indices_1.c:
	Add arm_neon_fp16_ok effective target.
	* gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_f16_indices_1.c: Likewise.
	* gcc.target/aarch64/advsimd-intrinsics/vld3_lane_f16_indices_1.c: Likewise.
	* gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_f16_indices_1.c: Likewise.
	* gcc.target/aarch64/advsimd-intrinsics/vld4_lane_f16_indices_1.c: Likewise.
	* gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_f16_indices_1.c: Likewise.
	* gcc.target/aarch64/advsimd-intrinsics/vst2_lane_f16_indices_1.c: Likewise.
	* gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_f16_indices_1.c: Likewise.
	* gcc.target/aarch64/advsimd-intrinsics/vst3_lane_f16_indices_1.c: Likewise.
	* gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_f16_indices_1.c: Likewise.
	* gcc.target/aarch64/advsimd-intrinsics/vst4_lane_f16_indices_1.c: Likewise.
	* gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_f16_indices_1.c: Likewise.

From-SVN: r237798

From-SVN: r237797