2016-11-25  Jakub Jelinek  <jakub@redhat.com>
	    Prathamesh Kulkarni  <prathamesh.kulkarni@linaro.org>

	PR middle-end/78501
	* tree-vrp.c (extract_range_basic): Check for ptrdiff_type_node to be
	non null and it's precision matches precision of lhs's type.

Co-Authored-By: Prathamesh Kulkarni <prathamesh.kulkarni@linaro.org>

From-SVN: r242858

From-SVN: r242857

gcc/testsuite/ChangeLog:

	PR tree-optimization/78476
	* gcc.dg/tree-ssa/builtin-sprintf-5.c: New test.

gcc/ChangeLog:

	PR tree-optimization/78476
	* gimple-ssa-sprintf.c (struct pass_sprintf_length::call_info):
	Add a member.
	(handle_gimple_call): Adjust signature.
	(try_substitute_return_value): Remove calls to bounded functions
	with zero buffer size whose result is known.
	(pass_sprintf_length::execute): Adjust call to handle_gimple_call.

From-SVN: r242854

	* varasm.c (assemble_start_function): Wrap align_log definition in
	ASM_OUTPUT_MAX_SKIP_ALIGN.

From-SVN: r242853

	* config/i386/i386.md (wide AND insn to QImode splitter): Use
	explicit mode macros.
	(wide OR insn to QImode splitter): Ditto.

From-SVN: r242852

	* config.guess: Import latest version.
	* config.sub: Likewise.

From-SVN: r242851

From-SVN: r242850

2016-11-24  Vladimir Makarov  <vmakarov@redhat.com>

	PR rtl-optimization/77541
	* lra-constraints.c (struct input_reload): Add field match_p.
	(get_reload_reg): Check modes of input reloads to generate unique
	value reload pseudo.
	(match_reload): Add input reload pseudo for the current insn.

2016-11-24  Vladimir Makarov  <vmakarov@redhat.com>

	PR rtl-optimization/77541
	* gcc.target/i386/pr77541.c: New.

From-SVN: r242848

2016-11-24  Steven G. Kargl  <kargl@gcc.gnu.org>

	PR fortran/78500
	* expr.c (gfc_check_vardef_contextm): Fix NULL pointer dereference.
	* interface.c (matching_typebound_op): Ditto.

2016-11-24  Steven G. Kargl  <kargl@gcc.gnu.org>

	PR fortran/78500
	* gfortran.dg/class_result_4.f90: New test.

From-SVN: r242846

gcc/

	* config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Update
	__FLT_EVAL_METHOD__ and __FLT_EVAL_METHOD_C99__ when we switch
	architecture levels.
	* config/aarch64/aarch64.c (aarch64_promoted_type): Only promote
	the aarch64_fp16_type_node, not all HFmode types.
	(aarch64_libgcc_floating_mode_supported_p): Support HFmode.
	(aarch64_scalar_mode_supported_p): Likewise.
	(aarch64_excess_precision): New.
	(TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P): Define.
	(TARGET_SCALAR_MODE_SUPPORTED_P): Likewise.
	(TARGET_C_EXCESS_PRECISION): Likewise.

gcc/testsuite/

	* gcc.target/aarch64/_Float16_1.c: New.
	* gcc.target/aarch64/_Float16_2.c: Likewise.
	* gcc.target/aarch64/_Float16_3.c: Likewise.

From-SVN: r242845

gcc/

	* config/aarch64/aarch64-c.c (aarch64_scalar_mode_supported_p): New.
	(TARGET_SCALAR_MODE_SUPPORTED_P): Define.

libgcc/

	* config/aarch64/sfp-machine.h (_FP_NANFRAC_H): Define.
	(_FP_NANSIGN_H): Likewise.
	* config/aarch64/t-softfp (softfp_extensions): Add hftf.
	(softfp_truncations): Add tfhf.
	(softfp_extras): Add required conversion functions.

From-SVN: r242844

gcc/

	* config/aarch64/aarch64.md (<optab>sihf2): Convert to expand.
	(<optab>dihf2): Likewise.
	(aarch64_fp16_<optab><mode>hf2): New.

gcc/testsuite/

	* gcc.target/aarch64/floatdihf2_1.c: New.

From-SVN: r242843

	PR target/67822
	* config/nvptx/mkoffload.c (main): Allow -fopenmp.

From-SVN: r242842

	* common/config/sparc/sparc-common.c (sparc_option_optimization_table):
	Enable REE at -O2 and higher.
	* config/sparc/sparc.c (sparc_option_override): Disable it by default
	in 32-bit mode.

From-SVN: r242841

	PR target/48863
	PR inline-asm/70184
	* tree-ssa-ter.c (temp_expr_table): Add reg_vars_cnt field.
	(new_temp_expr_table): Initialise reg_vars_cnt.
	(free_temp_expr_table): Release reg_vars_cnt.
	(process_replaceable): Add reg_vars_cnt argument, set reg_vars_cnt
	field of TAB.
	(find_replaceable_in_bb): Use the above to record register variable
	write occurrences and cancel replacement across them.

	* gcc.target/arm/pr48863.c: New test.

From-SVN: r242840

	PR rtl-optimization/78437
	* ree.c (get_uses): New function.
	(combine_reaching_defs): When a copy is needed, return false if any
	reaching use of the source register reads it in a mode larger than
	the mode it is set in and WORD_REGISTER_OPERATIONS is true.

From-SVN: r242839

	* gimple-pretty-print.c (dump_edge_probability): New function.
	(dump_gimple_switch): Dump label edge probabilities.
	(dump_gimple_cond): Likewise.
	(dump_gimple_label): Dump
	(dump_gimple_bb_header): Dump basic block frequency.
	(pp_cfg_jump): Replace e->dest argument with e.
	(dump_implicit_edges): Likewise.
	* tree-ssa-loop-ivopts.c (get_scaled_computation_cost_at):
	Use gimple_bb (at) instead of at->bb.
	* gcc.dg/builtin-unreachable-6.c: Update test to not to scan
	parts for frequencies/probabilities.
	* gcc.dg/pr34027-1.c: Likewise.
	* gcc.dg/strict-overflow-2.c: Likewise.
	* gcc.dg/tree-ssa/20040703-1.c: Likewise.
	* gcc.dg/tree-ssa/builtin-sprintf-2.c: Likewise.
	* gcc.dg/tree-ssa/pr32044.c: Likewise.
	* gcc.dg/tree-ssa/vector-3.c: Likewise.
	* gcc.dg/tree-ssa/vrp101.c: Likewise.
	* gcc.dg/tree-ssa/dump-2.c: New test.

From-SVN: r242837

gcc/
	* common.opt (flimit-function-alignment): New.
	* doc/invoke.texi (-flimit-function-alignment): Document.
	* emit-rtl.h (struct rtl_data): Add max_insn_address field.
	* final.c (shorten_branches): Set it.
	* varasm.c (assemble_start_function): Limit alignment if
	requested.

gcc/testsuite/
	* gcc.target/i386/align-limit.c: New test.

From-SVN: r242836

re PR tree-optimization/71595 (ICE on valid code at -O2 and -O3 on x86_64-linux-gnu: in check_loop_closed_ssa_use, at tree-ssa-loop-manip.c:704)

2016-11-24  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/71595
	* cfgloopmanip.h (remove_path): Add irred_invalidated and
	loop_closed_ssa_invalidated parameters, defaulted to NULL.
	* cfgloopmanip.c (remove_path): Likewise, pass them along to
	called functions.  Only fix irred flags if the caller didn't
	request state.
	* tree-ssa-loop-ivcanon.c (unloop_loops): Use add_bb_to_loop.
	(unloop_loops): Pass irred_invalidated and loop_closed_ssa_invalidated
	to remove_path.

	* gcc.dg/torture/pr71595.c: New testcase.

From-SVN: r242835

	PR rtl-optimization/78120
	* ifcvt.c (noce_conversion_profitable_p): Check original cost in all
	cases, and additionally test against max_seq_cost for speed
	optimization.
	(noce_process_if_block): Compute an estimate for the original cost when
	optimizing for speed, using the minimum of then and else block costs.

testsuite/
	PR rtl-optimization/78120
	* gcc.target/i386/pr78120.c: New test.

From-SVN: r242834

	PR rtl-optimization/78120
	* rtlanal.c (insn_rtx_cost): Use set_rtx_cost.

From-SVN: r242833

	PR rtl-optimization/78120
	* config/i386/i386.c (ix86_rtx_costs): Fully handle SETs.

From-SVN: r242832

	* match.pd: Refine type conversion in result expr for below pattern:
	(cond (cmp (convert1? x) c1) (convert2? x) c2) -> (minmax (x c)).

From-SVN: r242831

	PR middle-end/78429
	* tree.h (wi::fits_to_boolean_p): New predicate.
	(wi::fits_to_tree_p): Use it for boolean types.
	* tree.c (int_fits_type_p): Likewise.

From-SVN: r242829

	PR bootstrap/78493
	* parser.c (cp_parser_range_for): Use safe_push instead of quick_push.
	PR bootstrap/78493
	* g++.dg/cpp1z/decomp18.C: New test.

From-SVN: r242828

2016-11-23  Naveen H.S  <Naveen.Hurugalawadi@caviumnetworks.com>

	* gcc.target/aarch64/ldp_stp_1.c : Add -mcpu=generic.
	* gcc.target/aarch64/store-pair-1.c : Likewise.

From-SVN: r242827

2016-11-23  Richard Biener  <rguenther@suse.de>

	PR middle-end/71762
	* match.pd ((~X & Y) -> X < Y, (X & ~Y) -> Y < X,
	(~X | Y) -> X <= Y, (X | ~Y) -> Y <= X): Remove.

	* gcc.dg/torture/pr71762-1.c: New testcase.
	* gcc.dg/torture/pr71762-2.c: Likewise.
	* gcc.dg/torture/pr71762-3.c: Likewise.
	* gcc.dg/tree-ssa/forwprop-28.c: XFAIL.

From-SVN: r242822

2016-11-23  Naveen H.S  <Naveen.Hurugalawadi@caviumnetworks.com>

	* gcc.target/aarch64/fmaxmin.c : Add -fno-vect-cost-model.
	* gcc.target/aarch64/fmul_fcvt_2.c : Likewise.
	* gcc.target/aarch64/vect-abs-compile.c : Likewise.
	* gcc.target/aarch64/vect-clz.c : Likewise.
	* gcc.target/aarch64/vect-fcm-eq-d.c : Likewise.
	* gcc.target/aarch64/vect-fcm-ge-d.c : Likewise.
	* gcc.target/aarch64/vect-fcm-gt-d.c : Likewise.
	* gcc.target/aarch64/vect-fmovd-zero.c : Likewise.
	* gcc.target/aarch64/vect-fmovd.c : Likewise.
	* gcc.target/aarch64/vect-fmovf-zero.c : Likewise.
	* gcc.target/aarch64/vect-fmovf.c : Likewise.
	* gcc.target/aarch64/vect_ctz_1.c : Likewise.

From-SVN: r242821

	* print-tree.c (struct bucket): Remove.
	(print_node): Add new argument which drives whether a tree node
	is printed briefly or not.
	(debug_tree): Replace a custom hash table with hash_set<T>.
	* print-tree.h (print_node): Add the argument.

From-SVN: r242820

2016-11-24  Chung-Lin Tang  <cltang@codesourcery.com>

	* config/nios2/nios2.c (nios2_init_libfuncs): Add ATTRIBUTE_UNUSED.

From-SVN: r242819

gcc/
	PR target/78458
	* config/rs6000/rs6000.h (HARD_REGNO_CALLER_SAVE_MODE): Return MODE
	if it is at least NREGS wide.

gcc/testsuite/
	PR target/78458
	* gcc.target/powerpc/pr78458.c: New.

From-SVN: r242818

From-SVN: r242817

Given my previous fix for a missing insn pattern for e500, building
glibc runs into an assembler error "Error: operand out of range (256
is not between 0 and 248)".  This comes from an insn:

(insn 115 1209 1210 (set (reg:DF 27 27 [orig:294 _129 ] [294])
        (subreg:DF (mem/c:TI (plus:SI (reg/f:SI 1 1)
                    (const_int 256 [0x100])) [14 %sfp+256 S16 A128]) 0)) 1909 {*frob_df_ti}
     (nil))

This patch adjusts the offset handling for TImode - and TDmode and
PTImode in case such subregs can arise for them - to be the same as
for TFmode, so that proper SPE offset checks are made in the
TARGET_E500_DOUBLE case.

This allows the glibc build to complete.  Testing shows 372 FAILs
across the gcc, g++ and libstdc++ testsuites; more cleanup is
certainly needed, but this gets to the point where the toolchain at
least builds so it's possible to compare test results when fixing
bugs.

	* config/rs6000/rs6000.c (rs6000_legitimate_offset_address_p): For
	TARGET_E500_DOUBLE. handle TDmode, TImode and PTImode the same as
	TFmode, IFmode and KFmode.

From-SVN: r242814

Building glibc for powerpc-linux-gnuspe --enable-e500-double, given
the patch <https://gcc.gnu.org/ml/gcc-patches/2016-11/msg02404.html>
applied, fails with errors such as:

../sysdeps/ieee754/ldbl-128ibm/s_modfl.c: In function '__modfl':
../sysdeps/ieee754/ldbl-128ibm/s_modfl.c:91:1: error: unrecognizable insn:
 }
 ^
(insn 31 30 32 2 (set (reg:DF 203)
        (subreg:DF (reg:TI 202) 8)) "../sysdeps/ieee754/ldbl-128ibm/s_modfl.c":44 -1
     (nil))
../sysdeps/ieee754/ldbl-128ibm/s_modfl.c:91:1: internal compiler error: in extract_insn, at recog.c:2311

This patch adds an insn pattern similar to various patterns already
present to handle extracting such a subreg.  This allows the glibc
build to get further, until it runs into an assembler error for which
I have another patch.

gcc:
	* config/rs6000/spe.md (*frob_<SPE64:mode>_ti_8): New insn
	pattern.

gcc/testsuite:
	* gcc.c-torture/compile/20161123-1.c: New test.

From-SVN: r242813

As reported in https://gcc.gnu.org/ml/gcc-patches/2016-11/msg02388.html .

Changing the mode of a hard register can lead to problems, or at least
it can make worse code if the result will need reloads.


	* combine.c (change_zero_ext): Only change the mode of a hard register
	destination if can_change_dest_mode holds for that.

From-SVN: r242812

From-SVN: r242810

From-SVN: r242809

From-SVN: r242807

From-SVN: r242804

2016-11-07  Bernd Edlinger  <bernd.edlinger@hotmail.de>

	* opth-gen.awk: Use unsigned shifts for bit masks.  Allow all bits
	to be used.  Add brackets around macro argument.

From-SVN: r242803