gcc/
	* config/nds32/nds32-cost.c (rtx_cost_model_t): New structure.
	(insn_size_16bit, insn_size_32bit): New variables for cost evaluation.
	(nds32_rtx_costs_impl): Simplify.
	(nds32_address_cost_impl): Simplify.
	(nds32_init_rtx_costs): New function.
	(nds32_rtx_costs_speed_prefer): Likewise.
	(nds32_rtx_costs_size_prefer): Likewise.
	(nds32_address_cost_speed_prefer): Likewise.
	(nds32_address_cost_speed_fwprop): Likewise.
	(nds32_address_cost_size_prefer): Likewise.
	* config/nds32/nds32-protos.h (nds32_init_rtx_costs): Declare.
	* config/nds32/nds32.c (nds32_option_override): Use
	nds32_init_rtx_costs function.

Co-Authored-By: Chung-Ju Wu <jasonwucj@gmail.com>

From-SVN: r260411

From-SVN: r260410

gcc/
	* config/nds32/nds32.c (nds32_asm_file_start): Output pipeline model.
	* config/nds32/nds32.h (TARGET_PIPELINE_N7): Define.
	(TARGET_PIPELINE_N8): Likewise.
	(TARGET_PIPELINE_N10): Likewise.
	(TARGET_PIPELINE_N13): Likewise.
	(TARGET_PIPELINE_GRAYWOLF): Likewise.

From-SVN: r260409

From-SVN: r260408

	* pt.c (tsubst_pack_expansion): Sorry rather than abort
	on __integer_pack as subexpression of pattern.

From-SVN: r260404

gcc/
	* config/nds32/nds32-fpu.md: Update copyright year.

From-SVN: r260402

gcc/
	* config/nds32/nds32.h (ASM_SPEC): Adjust spec rule.

From-SVN: r260401

gcc/
	* config/nds32/nds32.c
	(nds32_md_asm_adjust): Consider flag_inline_asm_r15 variable.
	* config/nds32/nds32.opt (minline-asm-r15): New option.

From-SVN: r260400

gcc/
	* common/config/nds32/nds32-common.c (TARGET_DEFAULT_TARGET_FLAGS): Add
	MASK_HW_ABS.
	* config/nds32/nds32.md (abssi2): New pattern.

From-SVN: r260398

	* config/i386/i386.md (rex64namesuffix): New mode attribute.
	* config/i386/sse.md (sse_cvtsi2ss<rex64namesuffix><round_name>):
	Merge insn pattern from sse_cvtsi2ss<round_name> and
	sse_cvtsi2ssq<round_name> using SWI48 mode iterator.
	(sse_cvtss2si<rex64namesuffix><round_name>): Merge insn pattern
	from sse_cvtss2si<round_name> and sse_cvtss2siq<round_name>
	using SWI48 mode iterator.
	(sse_cvtss2si<rex64namesuffix>_2): Merge insn pattern from
	sse_cvtss2si_2 and sse_cvtss2siq_2 using SWI48 mode iterator.
	(sse_cvttss2si<rex64namesuffix><round_saeonly_name>): Merge insn
	pattern from sse_cvttss2si<round_saeonly_name>
	and sse_cvttss2siq<round_saeonly_name> using SWI48 mode iterator.
	(avx512f_vcvtss2usi<rex64namesuffix><round_name>): Merge insn pattern
	from avx512f_vcvtss2usi<round_name> and avx512f_vcvtss2usiq<round_name>
	using SWI48 mode iterator.
	(avx512f_vcvttss2usi<rex64namesuffix><round_saeonly_name>): Merge
	insn pattern from avx512f_vcvttss2usi<round_saeonly_name> and
	avx512f_vcvttss2usiq<round_saeonly_name> using SWI48 mode iterator.
	(avx512f_vcvtsd2usi<rex64namesuffix><round_name>): Merge insn pattern
	from avx512f_vcvtsd2usi<round_name> and avx512f_vcvtsd2usiq<round_name>
	using SWI48 mode iterator.
	(avx512f_vcvttsd2usi<rex64namesuffix><round_saeonly_name>): Merge
	insn pattern from avx512f_vcvttsd2usi<round_saeonly_name> and
	avx512f_vcvttsd2usiq<round_saeonly_name> using SWI48 mode iterator.
	(sse2_cvtsd2si<rex64namesuffix><round_name>): Merge insn pattern from
	sse2_cvtsd2si<round_name> and sse2_cvtsd2siq<round_name> using
	SWI48 mode iterator.
	(sse2_cvtsd2si<rex64namesuffix>_2): Merge insn pattern from
	sse2_cvtsd2si_2 and sse2_cvtsd2siq_2 using SWI48 mode iterator.
	(sse_cvttsd2si<rex64namesuffix><round_saeonly_name>): Merge insn
	pattern from sse_cvttsd2si<round_saeonly_name>
	and sse_cvttsd2siq<round_saeonly_name> using SWI48 mode iterator.

From-SVN: r260397

gcc/
	* config/nds32/nds32-md-auxiliary.c
	(nds32_valid_smw_lwm_base_p): Refine.
	(nds32_output_smw_single_word): Refine.
	(nds32_output_smw_double_word): New.
	* config/nds32/nds32-protos.h (nds32_output_smw_double_word): New.

From-SVN: r260396

gcc/
	* config/nds32/nds32-md-auxiliary.c (nds32_output_stack_push): Refine.
	(nds32_output_stack_pop): Refine.
	(nds32_expand_unaligned_load): Refine.
	(nds32_expand_unaligned_store): Refine.

From-SVN: r260394

gcc/
	* config/nds32/constants.md: Add TP_REGNUM constant.
	(unspec_element): Add UNSPEC_GOTINIT, UNSPEC_GOT, UNSPEC_GOTOFF,
	UNSPEC_PLT, UNSPEC_TLSGD, UNSPEC_TLSLD, UNSPEC_TLSIE, UNSPEC_TLSLE and
	UNSPEC_ADD32.
	* config/nds32/nds32-doubleword.md: Consider flag_pic.
	* config/nds32/nds32-dspext.md (mov<mode>): Expand TLS and PIC cases.
	* config/nds32/nds32-predicates.c (nds32_const_unspec_p): New.
	* config/nds32/nds32-md-auxiliary.c: Implementation that support TLS
	and PIC code generation.
	* config/nds32/nds32-protos.h: Declarations that support TLS and PIC
	code generation.
	* config/nds32/nds32-relax-opt.c: Consider TLS and PIC for relax
	optimization.
	* config/nds32/nds32.md: Support TLS and PIC.
	* config/nds32/nds32.c: Support TLS and PIC.
	* config/nds32/nds32.h (nds32_relax_insn_type): New enum type.
	* config/nds32/predicates.md (nds32_nonunspec_symbolic_operand): New
	predicate.

Co-Authored-By: Chung-Ju Wu <jasonwucj@gmail.com>

From-SVN: r260393

2018-05-19  Paul Thomas  <pault@gcc.gnu.org>

	PR fortran/82923
	PR fortran/66694
	PR fortran/82617
	* trans-array.c (gfc_alloc_allocatable_for_assignment): Set the
	charlen backend_decl of the rhs expr to ss->info->string_length
	so that the value in the current scope is used.

2018-05-19  Paul Thomas  <pault@gcc.gnu.org>

	PR fortran/82923
	* gfortran.dg/allocate_assumed_charlen_4.f90: New test. Note
	that the patch fixes PR66694 & PR82617, although the testcases
	are not explicitly included.

From-SVN: r260392

gcc/
	* config/nds32/nds32-predicates.c (const_vector_to_hwint): Use machine
	mode with E_ prefix.

From-SVN: r260391

	* config/nds32/constants.md (unspec_element): Add UNSPEC_ICT.
	* config/nds32/nds32-md-auxiliary.c
	(symbolic_reference_mentioned_p): New.
	(nds32_legitimize_ict_address): New.
	(nds32_expand_ict_move): New.
	(nds32_indirect_call_referenced_p): New.
	(nds32_symbol_binds_local_p): Delete.
	(nds32_long_call_p): Modify.
	* config/nds32/nds32-opts.h (nds32_ict_model_type): New enum type.
	* config/nds32/nds32-protos.h
	(symbolic_reference_mentioned_p): Declare.
	(nds32_legitimize_ict_address): Declare.
	(nds32_expand_ict_move): Declare.
	(nds32_indirect_call_referenced_p): Declare.
	* config/nds32/nds32-relax-opt.c (nds32_ict_const_p): New.
	(nds32_relax_group): Use nds32_ict_const_p as condition.
	* config/nds32/nds32.c (nds32_attribute_table): Add "indirect_call".
	(nds32_asm_file_start): Output ict_model directive in asm code.
	(nds32_legitimate_address_p): Consider indirect call.
	(nds32_print_operand): Consider indirect call.
	(nds32_print_operand_address): Consider indirect call.
	(nds32_insert_attributes): Handle "indirect_call" attribute.
	(TARGET_LEGITIMATE_ADDRESS_P): Define.
	(TARGET_LEGITIMATE_CONSTANT_P): Define.
	(TARGET_CANNOT_FORCE_CONST_MEM): Define.
	(TARGET_DELEGITIMIZE_ADDRESS): Define.
	(TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA): Define.
	* config/nds32/nds32.h (SYMBOLIC_CONST_P): Define.
	(TARGET_ICT_MODEL_SMALL): Define.
	(TARGET_ICT_MODEL_LARGE): Define.
	* config/nds32/nds32.md (movsi): Consider ict model.
	(call, call_value): Consider ict model.
	(sibcall, sibcall_value): Consider ict model.
	* config/nds32/nds32.opt (mict-model): New option.
	* config/nds32/predicates.md (nds32_symbolic_operand): Consider ict
	model.

Co-Authored-By: Chung-Ju Wu <jasonwucj@gmail.com>

From-SVN: r260390

	* src/c++11/codecvt.cc (__codecvt_utf8_base<wchar_t>::do_in)
	[__SIZEOF_WCHAR_T__==2 && __BYTE_ORDER__!=__ORDER_BIG_ENDIAN__]: Set
	little_endian element in bitmask.
	* testsuite/22_locale/codecvt/codecvt_utf8/69703.cc: Run all tests.
	* testsuite/22_locale/codecvt/codecvt_utf8/wchar_t/1.cc: New.

From-SVN: r260389

From-SVN: r260388

	Kito Cheng <kito.cheng@gmail.com>
	Monk Chiang  <sh.chiang04@gmail.com>

	gcc/
	* common/config/riscv/riscv-common.c (riscv_parse_arch_string):
	Add support to parse rv32e*.  Clear MASK_RVE for rv32i and rv64i.
	* config.gcc (riscv*-*-*): Add support for rv32e* and ilp32e.
	* config/riscv/riscv-c.c (riscv_cpu_cpp_builtins): Define
	__riscv_32e when TARGET_RVE.  Handle ABI_ILP32E as soft-float ABI.
	* config/riscv/riscv-opts.h (riscv_abi_type): Add ABI_ILP32E.
	* config/riscv/riscv.c (riscv_compute_frame_info): When TARGET_RVE,
	compute save_libcall_adjustment properly.
	(riscv_option_override): Call error if TARGET_RVE and not ABI_ILP32E.
	(riscv_conditional_register_usage): Handle TARGET_RVE and ABI_ILP32E.
	* config/riscv/riscv.h (UNITS_PER_FP_ARG): Handle ABI_ILP32E.
	(STACK_BOUNDARY, ABI_STACK_BOUNDARY): Handle TARGET_RVE.
	(GP_REG_LAST, MAX_ARGS_IN_REGISTERS): Likewise.
	(ABI_SPEC): Handle mabi=ilp32e.
	* config/riscv/riscv.opt (abi_type): Add ABI_ILP32E.
	(RVE): Add RVE mask.
	* doc/invoke.texi (RISC-V options) <-mabi>: Add ilp32e info.
	<-march>: Add rv32e as an example.

	gcc/testsuite/
	* gcc.dg/stack-usage-1.c: Add support for rv32e.

	libgcc/
	* config/riscv/save-restore.S: Add support for rv32e.

Co-Authored-By: Jim Wilson <jimw@sifive.com>
Co-Authored-By: Monk Chiang <sh.chiang04@gmail.com>

From-SVN: r260384

2018-05-18  Marc Glisse  <marc.glisse@inria.fr>

	PR c++/82899
gcc/
	* tree-ssa-structalias.c (create_variable_info_for_1): Extra argument.
	(intra_create_variable_infos): Handle C++ constructors.

gcc/testsuite/
	* g++.dg/pr82899.C: New testcase.

From-SVN: r260383

	* include/bits/stl_tree.h
	(_Rb_tree_impl(_Rb_tree_impl&&, _Node_allocator&&)): New.
	(_Rb_tree(_Rb_tree&&, _Node_allocator&&, true_type)): New, use latter.
	(_Rb_tree(_Rb_tree&&, _Node_allocator&&, false_type)): New.
	(_Rb_tree(_Rb_tree&&, _Node_allocator&&)): Adapt, use latters.
	* include/debug/map.h
	(map(map&&, const_allocator_type&)): Add noexcept qualitication.
	* include/debug/multimap.h
	(multimap(multimap&&, const_allocator_type&)): Likewise.
	* include/debug/set.h
	(set(set&&, const_allocator_type&)): Likewise.
	* include/debug/multiset.h
	(multiset(multiset&&, const_allocator_type&)): Likewise.
	* testsuite/23_containers/map/cons/noexcept_default_construct.cc:
	Add checks.
	* testsuite/23_containers/map/cons/noexcept_move_construct.cc:
	Add checks.
	* testsuite/23_containers/multimap/cons/noexcept_default_construct.cc:
	Add checks.
	* testsuite/23_containers/multimap/cons/noexcept_move_construct.cc:
	Add checks.
	* testsuite/23_containers/multiset/cons/noexcept_default_construct.cc:
	Add checks.
	* testsuite/23_containers/multiset/cons/noexcept_move_construct.cc:
	Add checks.
	* testsuite/23_containers/set/cons/noexcept_default_construct.cc:
	Add checks.
	* testsuite/23_containers/set/cons/noexcept_move_construct.cc:
	Add checks.

From-SVN: r260382

gcc/c-family/
	* c.opt (Wdeprecated-copy): New flag.
gcc/cp/
	* call.c (build_over_call): Warn about deprecated trivial fns.
	* class.c (classtype_has_user_copy_or_dtor): New.
	(type_build_ctor_call): Check TREE_DEPRECATED.
	(type_build_dtor_call): Likewise.
	* decl2.c (cp_warn_deprecated_use): Move from tree.c.
	Add checks.  Return bool.  Handle -Wdeprecated-copy.
	(mark_used): Use it.
	* decl.c (grokdeclarator): Remove redundant checks.
	* typeck2.c (build_functional_cast): Likewise.
	* method.c (lazily_declare_fn): Mark deprecated copy ops.
	* init.c (build_aggr_init): Only set TREE_USED if there are
	side-effects.
libitm/
	* beginend.cc (save): Disable -Werror=deprecated-copy.

From-SVN: r260381

	* include/bits/stl_deque.h (_Deque_iterator): Constrain constructor
	for conversion to const_iterator.  Add defaulted copy ops.
	* libsupc++/new (bad_alloc): Add defaulted copy ops.
	* libsupc++/exception.h (exception): Add defaulted copy ops.
	* include/std/system_error (system_error): Add defaulted copy ops.
	* include/std/stdexcept (domain_error, invalid_argument)
	(length_error, out_of_range, range_error, overflow_error)
	(underflow_error): Add defaulted copy ops.
	* include/bits/stl_iterator.h (reverse_iterator): Add defaulted
	copy assignment.
	* include/bits/allocator.h (allocator): Add defaulted copy assignment.
	* include/ext/throw_allocator.h (condition_base): Add defaulted
	default and copy ctor and copy assignment.

From-SVN: r260380

2018-05-18  Martin Liska  <mliska@suse.cz>

	* gcc.dg/pr68766.c: Change pruned output.

From-SVN: r260379

2018-05-18  Martin Liska  <mliska@suse.cz>

	* passes.def: Remove a redundant pass.

From-SVN: r260378

re PR bootstrap/85838 (-Wmaybe-uninitialized warning in sparc.c (sparc_expand_builtin) breaks SPARC bootstrap)

	PR bootstrap/85838
	* config/sparc/sparc.c (sparc_expand_builtin): Always initialize op[0].

From-SVN: r260374

In C++11 and C++14 any odr-use of these constants requires a definition
at namespace-scope.  In C++17 they are implicitly inline and so the
namespace-scope redeclarations are redundant (and allowing them is
deprecated).

	PR libstdc++/85098
	* include/bits/regex.h [__cplusplus < 201703L] (basic_regex::icase)
	(basic_regex::nosubs, basic_regex::optimize, basic_regex::collate)
	(basic_regex::ECMAScript, basic_regex::basic, basic_regex::extended)
	(basic_regex::awk, basic_regex::grep, basic_regex::egrep): Add
	definitions.
	* include/bits/regex_automaton.h (_NFA::_M_insert_state): Adjust
	whitespace.
	* include/bits/regex_compiler.tcc (__INSERT_REGEX_MATCHER): Add
	braces around body of do-while.
	* testsuite/28_regex/basic_regex/85098.cc: New

From-SVN: r260371

PR c++/85782

	gcc/cp/
	* cp-gimplify.c (cp_genericize_r): Call genericize_omp_for_stmt for
	OACC_LOOPs.

	gcc/testsuite/
	* c-c++-common/goacc/pr85782.c: New test.

	libgomp/
	* testsuite/libgomp.oacc-c-c++-common/pr85782.c: New test.

From-SVN: r260369

*** gcc/testsuite/ChangeLog ***

2018-05-18  Sudakshina Das  <sudi.das@arm.com>

	* gcc.target/aarch64/sve/slp_5.c: Remove xfail for tld1d and tld2d.

From-SVN: r260365

We deprecated architecture versions earlier than Armv4T in GCC 6 [1].
This patch removes support for architectures lower than Armv4.
That is the -march values armv2, armv2a, armv3, armv3m are removed
with this patch.  I did not remove armv4 because it's a bit more
involved code-wise and there has been some pushback on the implications
for -mcpu=strongarm support.

Removing armv3m and earlier though is pretty straightforward.
This allows us to get rid of the armv3m and mode32 feature bits
in arm-cpus.in as they can be assumed to be universally available.

Consequently the mcpu values arm2, arm250, arm3, arm6, arm60, arm600, arm610, arm620, arm7, arm7d, arm7di, arm70, arm700, arm700i, arm710, arm720, arm710c, arm7100, arm7500, arm7500fe, arm7m, arm7dm, arm7dm are now also removed.

Bootstrapped and tested on arm-none-linux-gnueabihf and on arm-none-eabi
with an aprofile multilib configuration (which builds quite a lot of library
configurations).

[1] https://gcc.gnu.org/gcc-6/changes.html#arm 

	* config/arm/arm-cpus.in (armv3m, mode32): Delete features.
	(ARMv4): Update.
	(ARMv2, ARMv3, ARMv3m): Delete fgroups.
	(ARMv6m): Update.
	(armv2, armv2a, armv3, armv3m): Delete architectures.
	(arm2, arm250, arm3, arm6, arm60, arm600, arm610, arm620,
	arm7, arm7d, arm7di, arm70, arm700, arm700i, arm710, arm720,
	arm710c, arm7100, arm7500, arm7500fe, arm7m, arm7dm, arm7dmi):
	Delete cpus.
	* config/arm/arm.md (maddsidi4): Remove check for arm_arch3m.
	(*mulsidi3adddi): Likewise.
	(mulsidi3): Likewise.
	(*mulsidi3_nov6): Likewise.
	(umulsidi3): Likewise.
	(umulsidi3_nov6): Likewise.
	(umaddsidi4): Likewise.
	(*umulsidi3adddi): Likewise.
	(smulsi3_highpart): Likewise.
	(*smulsi3_highpart_nov6): Likewise.
	(umulsi3_highpart): Likewise.
	(*umulsi3_highpart_nov6): Likewise.
	* config/arm/arm.h (arm_arch3m): Delete.
	* config/arm/arm.c (arm_arch3m): Delete.
	(arm_option_override_internal): Update armv3-related comment.
	(arm_configure_build_target): Delete use of isa_bit_mode32.
	(arm_option_reconfigure_globals): Delete set of arm_ach3m.
	(arm_rtx_costs_internal): Delete check of arm_arch3m.
	* config/arm/arm-fixed.md (mulsq3): Delete check for arm_arch3m.
	(mulsa3): Likewise.
	(mulusa3): Likewise.
	* config/arm/arm-protos.h (arm_arch3m): Delete.
	* config/arm/arm-tables.opt: Regenerate.
	* config/arm/arm-tune.md: Likewise.
	* config/arm/t-arm-elf (all_early_nofp): Delete mentions of
	deleted architectures.

	* gcc.target/arm/pr62554.c: Delete.
	* gcc.target/arm/pr69610-1.c: Likewise.
	* gcc.target/arm/pr69610-2.c: Likewise.

From-SVN: r260363

The -march=armv5 and armv5e options have been deprecated in GCC 7 [1].
This patch removes support for them.
It's mostly mechanical stuff. The functionality that was previously
gated on arm_arch5 is now gated on arm_arch5t and the functionality
that was gated on arm_arch5e is now gated on arm_arch5te.

A path in TARGET_OS_CPP_BUILTINS for VxWorks is now unreachable and
therefore is deleted.

References to armv5 and armv5e are deleted/updated throughout the
source tree and testsuite.

Bootstrapped and tested on arm-none-linux-gnueabihf.
Also built a cc1 for arm-wrs-vxworks as a sanity check.

        * config/arm/arm-cpus.in (armv5, armv5e): Delete features.
        (armv5t, armv5te): New features.
        (ARMv5, ARMv5e): Delete fgroups.
        (ARMv5t, ARMv5te): Adjust for above changes.
        (ARMv6m): Likewise.
        (armv5, armv5e): Delete arches.
        * config/arm/arm.md (*call_reg_armv5): Use arm_arch5t instead of
        arm_arch5.
        (*call_reg_arm): Likewise.
        (*call_value_reg_armv5): Likewise.
        (*call_value_reg_arm): Likewise.
        (*call_symbol): Likewise.
        (*call_value_symbol): Likewise.
        (*sibcall_insn): Likewise.
        (*sibcall_value_insn): Likewise.
        (clzsi2): Likewise.
        (prefetch): Likewise.
        (define_split and define_peephole2 dependent on arm_arch5):
        Likewise.
        * config/arm/arm.h (TARGET_LDRD): Use arm_arch5te instead of
        arm_arch5e.
        (TARGET_ARM_QBIT): Likewise.
        (TARGET_DSP_MULTIPLY): Likewise.
        (enum base_architecture): Delete BASE_ARCH_5, BASE_ARCH_5E.
        (arm_arch5, arm_arch5e): Delete.
        (arm_arch5t, arm_arch5te): Declare.
        * config/arm/arm.c (arm_arch5, arm_arch5e): Delete.
        (arm_arch5t): Declare.
        (arm_option_reconfigure_globals): Update for the above.
        (arm_options_perform_arch_sanity_checks): Update comment, replace
        use of arm_arch5 with arm_arch5t.
        (use_return_insn): Likewise.
        (arm_emit_call_insn): Likewise.
        (output_return_instruction): Likewise.
        (arm_final_prescan_insn): Likewise.
        (arm_coproc_builtin_available): Likewise.
        * config/arm/arm-c.c (arm_cpu_builtins): Replace arm_arch5 and
        arm_arch5e with arm_arch5t and arm_arch5te.
        * config/arm/arm-protos.h (arm_arch5, arm_arch5e): Delete.
        (arm_arch5t, arm_arch5te): Declare.
        * config/arm/arm-tables.opt: Regenerate.
        * config/arm/t-arm-elf: Remove references to armv5, armv5e.
        * config/arm/t-multilib: Likewise.
        * config/arm/thumb1.md (*call_reg_thumb1_v5): Check arm_arch5t
        instead of arm_arch5.
        (*call_reg_thumb1): Likewise.
        (*call_value_reg_thumb1_v5): Likewise.
        (*call_value_reg_thumb1): Likewise.
        * config/arm/vxworks.h (TARGET_OS_CPP_BUILTINS): Remove now
        unreachable path.
        * doc/invoke.texi (ARM Options): Remove references to armv5, armv5e.

        * gcc.target/arm/pr40887.c: Update comment.
        * lib/target-supports.exp: Don't generate effective target checks
        and related helpers for armv5.  Update comment.
        * gcc.target/arm/armv5_thumb_isa.c: Delete.
        * gcc.target/arm/di-longlong64-sync-withhelpers.c: Update effective
        target check and options.

        * config/arm/libunwind.S: Update comment relating to armv5.

From-SVN: r260362

2018-05-18  Martin Liska  <mliska@suse.cz>

	PR gcov-profile/84846
	* gcov.c (print_usage): Add new -t option.
	(process_args): Handle the option.
	(generate_results): Use stdout as output when requested by
	the option.
2018-05-18  Martin Liska  <mliska@suse.cz>

	PR gcov-profile/84846
	* doc/gcov.texi: Document -t option of gcov tool.

From-SVN: r260361

2018-05-18  Martin Liska  <mliska@suse.cz>

	PR gcov-profile/84846
	* coverage.c (coverage_init): Write PWD to .gcno file.
	* doc/gcov.texi: Document how working directory is printed.
	* gcov-dump.c (dump_gcov_file): Print PWD.
	* gcov.c (output_intermediate_file): Likewise.
	(read_graph_file): Read PWD string.
	(output_lines): Print PWD.

From-SVN: r260359

2018-05-18  Prathamesh Kulkarni  <prathamesh.kulkarni@linaro.org>

	PR middle-end/85817
	* ipa-pure-const.c (malloc_candidate_p): Remove the check integer_zerop
	for retval and return false if all args to phi are zero.	

testsuite/
	* gcc.dg/tree-ssa/pr83648.c: Change scan-tree-dump to
	scan-tree-dump-not for h.

From-SVN: r260358

2018-05-18  Richard Biener  <rguenther@suse.de>

	* gimple-ssa-evrp.c (class evrp_folder): Add simplify_stmt_using_ranges
	method.
	(evrp_dom_walker::before_dom_children): Call it.

	* gcc.dg/tree-ssa/pr21559.c: Adjust.
	* gcc.dg/tree-ssa/pr45397.c: Likewise.
	* gcc.dg/tree-ssa/pr61839_1.c: Likewise.
	* gcc.dg/tree-ssa/pr61839_2.c: Likewise.
	* gcc.dg/tree-ssa/pr61839_4.c: Likewise.
	* gcc.dg/tree-ssa/vrp17.c: Likewise.
	* gcc.dg/tree-ssa/vrp18.c: Likewise.
	* gcc.dg/tree-ssa/vrp23.c: Likewise.
	* gcc.dg/tree-ssa/vrp24.c: Likewise.
	* gcc.dg/tree-ssa/vrp58.c: Likewise.
	* gcc.dg/vrp-min-max-1.c: Likewise.
	* gcc.dg/vrp-min-max-3.c: New testcase.

From-SVN: r260357

tree-dfa.c (get_ref_base_and_extent): Use range-info to refine results when processing array refs with variable index.

2018-05-18  Richard Biener  <rguenther@suse.de>

	* tree-dfa.c (get_ref_base_and_extent): Use range-info to refine
	results when processing array refs with variable index.

	* gcc.dg/tree-ssa/ssa-dse-35.c: New testcase.
	* gcc.dg/graphite/scop-10.c: Adjust to avoid dead code.
	* gcc.dg/graphite/scop-6.c: Likewise.
	* gcc.dg/graphite/scop-7.c: Likewise.
	* gcc.dg/graphite/scop-8.c: Likewise.
	* gcc.dg/graphite/scop-9.c: Likewise.

From-SVN: r260354

2018-05-18  Toon Moene  <toon@moene.org>

	* doc/invoke.texi: Move -floop-unroll-and-jam documentation
	directly after that of -floop-interchange. Indicate that both
	options are enabled by default when specifying -O3.

From-SVN: r260352

We've a deficiency in our vec_set family of patterns.
We don't support directly loading a vector lane using LD1 for V2DImode and all the vector floating-point modes.
We do do it correctly for the other integer vector modes (V4SI, V8HI etc) though.

The alternatives on the relative floating-point patterns only allow a register-to-register INS instruction.
That means if we want to load a value into a vector lane we must first load it into a scalar register and then
perform an INS, which is wasteful.

There is also an explicit V2DI vec_set expander dangling around for no reason that I can see. It seems to do the
exact same things as the other vec_set expanders. This patch removes that.
It now unifies all vec_set expansions into a single "vec_set<mode>" define_expand using the catch-all VALL_F16 iterator. 

With this patch we avoid loading values into scalar registers and then doing an explicit INS on them to move them into
the desired vector lanes. For example for:

typedef float v4sf __attribute__ ((vector_size (16)));
typedef long long v2di __attribute__ ((vector_size (16)));

v2di
foo_v2di (long long *a, long long *b)
{
  v2di res = { *a, *b };
  return res;
}

v4sf
foo_v4sf (float *a, float *b, float *c, float *d)
{
  v4sf res = { *a, *b, *c, *d };
  return res;
}

we currently generate:

foo_v2di:
        ldr     d0, [x0]
        ldr     x0, [x1]
        ins     v0.d[1], x0
        ret

foo_v4sf:
        ldr     s0, [x0]
        ldr     s3, [x1]
        ldr     s2, [x2]
        ldr     s1, [x3]
        ins     v0.s[1], v3.s[0]
        ins     v0.s[2], v2.s[0]
        ins     v0.s[3], v1.s[0]
        ret

but with this patch we generate the much cleaner:
foo_v2di:
        ldr     d0, [x0]
        ld1     {v0.d}[1], [x1]
        ret

foo_v4sf:
        ldr     s0, [x0]
        ld1     {v0.s}[1], [x1]
        ld1     {v0.s}[2], [x2]
        ld1     {v0.s}[3], [x3]
        ret


	* config/aarch64/aarch64-simd.md (vec_set<mode>): Use VALL_F16 mode
	iterator.  Delete separate integer-mode vec_set<mode> expander.
	(aarch64_simd_vec_setv2di): Delete.
	(vec_setv2di): Delete.
	(aarch64_simd_vec_set<mode>): Delete all other patterns with that name.
	Use VALL_F16 mode iterator.  Add LD1 alternative and use vwcore for
	the "w, r" alternative.

	* gcc.target/aarch64/vect-init-ld1.c: New test.

From-SVN: r260351

2018-05-18  Martin Liska  <mliska@suse.cz>

	* passes.def: Add pass_lower_switch and pass_lower_switch_O0.
	* tree-pass.h (make_pass_lower_switch_O0): New function.
	* tree-switch-conversion.c (node_has_low_bound): Remove.
	(node_has_high_bound): Likewise.
	(node_is_bounded): Likewise.
	(class pass_lower_switch): Make it a template type and create
	two instances.
	(pass_lower_switch::execute): Add template argument.
	(make_pass_lower_switch): New function.
	(make_pass_lower_switch_O0): New function.
	(do_jump_if_equal): Remove.
	(emit_case_nodes): Simplify to just handle all 3 cases and leave
	all the hard work to tree optimization passes.
2018-05-18  Martin Liska  <mliska@suse.cz>

	* gcc.dg/tree-ssa/vrp104.c: Adjust dump file that is scanned.
	* gcc.dg/tree-prof/update-loopch.c: Likewise.

From-SVN: r260350

2018-05-18  Martin Liska  <mliska@suse.cz>

	* dbgcnt.c (limit_low): Renamed from limit.
	(limit_high): New variable.
	(dbg_cnt_is_enabled): Check for upper limit.
	(dbg_cnt): Adjust dumping.
	(dbg_cnt_set_limit_by_index): Add new argument for high
	value.
	(dbg_cnt_set_limit_by_name): Likewise.
	(dbg_cnt_process_single_pair): Parse new format.
	(dbg_cnt_process_opt): Use strtok.
	(dbg_cnt_list_all_counters): Remove 'value' and add
	'limit_high'.
	* doc/invoke.texi: Document changes.
2018-05-18  Martin Liska  <mliska@suse.cz>

	* gcc.dg/ipa/ipa-icf-39.c: New test.
	* gcc.dg/pr68766.c: Adjust pruned output.

From-SVN: r260349