Skip to content

R
riscv-gcc-1
Switch branch/tag
  1. 26 Feb, 2019 25 commits
  3. 25 Feb, 2019 15 commits
    • re PR c/89495 (gcc/c-family/c-format.c:1272:20: runtime error: signed integer… · 7da73ba7 
      re PR c/89495 (gcc/c-family/c-format.c:1272:20: runtime error: signed integer overflow: 214748365 * 10 cannot be represented in type 'int')

	PR c/89495
	* c-format.c (maybe_read_dollar_number): Compute nargnum in
	HOST_WIDE_INT type to avoid overflows and change overflow_flag
	checking.

From-SVN: r269198
      Jakub Jelinek committed
    • re PR c/77754 (internal compiler error : tree code 'call_expr' is not supported in LTO streams) · 79695450 
      	PR c/77754
	* gcc.c-torture/compile/pr77754-1.c: New test.
	* gcc.c-torture/compile/pr77754-2.c: New test.
	* gcc.c-torture/compile/pr77754-3.c: New test.
	* gcc.c-torture/compile/pr77754-4.c: New test.
	* gcc.c-torture/compile/pr77754-5.c: New test.
	* gcc.c-torture/compile/pr77754-6.c: New test.

From-SVN: r269197
      Jakub Jelinek committed
    • c.opt (Wmissing-attributes): Clean up doc string. · d3a02ae5 
      2019-02-25  Sandra Loosemore  <sandra@codesourcery.com>
	    Martin Sebor  <msebor@gmail.com>

	gcc/
	* c-family/c.opt (Wmissing-attributes): Clean up doc string.
	* common.opt (Wattribute-alias): Likewise.
	* doc/invoke.texi (Option Summary): List general form of
	-Wattribute-alias=.  List positive form of -Wmissing-attributes.
	(-Wmissing-attributes): Invert entry, rewrite and correct default.
	Add cross-references.
	(-Wattribute-alias): Rewrite and correct default.  Mention
	considered attributes (same as for -Wmissing-attributes).

Co-Authored-By: Martin Sebor <msebor@gmail.com>

From-SVN: r269196
      Sandra Loosemore committed
    • [rs6000] PR89338, PR89339: Fix compat vector intrinsics for BE and 32-bit · db739d3c 
      Test FAILS: sse2-cvtpd2dq-1, sse2-cvtpd2ps, sse2-cvttpd2dq on powerpc64
(big-endian).

_mm_cvtpd_epi32, _mm_cvtpd_ps, _mm_cvttpd_epi32: Type conversion from
vector doubleword type to vector word type leaves the results in even
lanes in big endian mode.

Test FAILS: sse-cvtss2si-1, sse-cvtss2si-2, sse-movmskb-1 on powerpc
(32-bit big-endian).

Incorrect type for interpreting the result from mfvsrd instruction leads
to incorrect results.  Also, mfvsrd instruction only works as expected in
64-bit mode or for 32-bit quantities in 32-bit mode.  A more general,
if slower, solution is needed for 32-bit mode.

2019-02-25  Paul A. Clarke  <pc@us.ibm.com>

[gcc]

	* config/rs6000/emmintrin.h (_mm_cvtpd_epi32): Fix big endian.
	(_mm_cvtpd_ps): Likewise.
	(_mm_cvttpd_epi32): Likewise.

	PR target/89338
	* config/rs6000/xmmintrin.h (_mm_cvtss_f32):  Fix type mismatch.
	(_mm_cvt_ss2si): Fix type mismatch and 32-bit.

	PR target/89339
	* config/rs6000/xmmintrin.h (_mm_movemask_pi8): Fix 32-bit.

From-SVN: r269195
      Paul A. Clarke committed
    • * fr.po: Update. · b5c44c57 
      From-SVN: r269194
      Joseph Myers committed
    • AArch64: Fix command line options canonicalization version #2. (PR target/88530) · 4ca82fc9 
      Commandline options on AArch64 don't get canonicalized into the smallest
possible set before output to the assembler. This means that overlapping feature
sets are emitted with superfluous parts.

Normally this isn't an issue, but in the case of crypto we have retro-actively
split it into aes and sha2. We need to emit only +crypto to the assembler
so old assemblers continue to work.

Because of how -mcpu=native and -march=native work they end up enabling all
feature bits. Instead we need to get the smallest possible set, which would also
fix the problem with older the assemblers and the retro-active split.

The function that handles this is called quite often.  It is called for any
push/pop options or attribute that changes arch, cpu etc.  In order to not make
this search for the smallest set too expensive we sort the options based on the
number of features (bits) they enable.  This allows us to process the list
linearly instead of quadratically (Once we have enabled a feature, we know that
anything else that enables it can be ignored.  By sorting we'll get the biggest
groups first and thus the smallest combination of commandline flags).

The Option handling structures have been extended to have a boolean to indicate
whether the option is synthetic, with that I mean if the option flag itself
enables a new feature.

e.g. +crypto isn't an actual feature, it just enables other features, but others
like +rdma enable multiple dependent features but is itself also a feature.

There are two ways to solve this.

1) Either have the options that are feature bits also turn themselves on, e.g.
   change rdma to turn on FP, SIMD and RDMA as dependency bits.

2) Make a distinction between these two different type of features and have the
   framework handle it correctly.

Even though it's more code I went for the second approach, as it's the one
that'll be less fragile (people can't forget it) and gives the least surprises.

Effectively this patch changes the following:

The values before the => are the old compiler and after the => the new code.

-march=armv8.2-a+crypto+sha2 => -march=armv8.2-a+crypto
-march=armv8.2-a+sha2+aes => -march=armv8.2-a+crypto

The remaining behaviors stay the same.

gcc/ChangeLog:

	PR target/88530
	* common/config/aarch64/aarch64-common.c
	(struct aarch64_option_extension): Add is_synthetic.
	(all_extensions): Use it.
	(TARGET_OPTION_INIT_STRUCT): Define hook.
	(struct gcc_targetm_common): Moved to end.
	(all_extensions_by_on): New.
	(opt_ext_cmp, typedef opt_ext): New.
	(aarch64_option_init_struct): New.
	(aarch64_contains_opt): New.
	(aarch64_get_extension_string_for_isa_flags): Output smallest set.
	* config/aarch64/aarch64-option-extensions.def
	(AARCH64_OPT_EXTENSION): Explicitly include AES and SHA2 in crypto.
	(fp, simd, crc, lse, fp16, rcpc, rdma, dotprod, aes, sha2, sha3,
	sm4, fp16fml, sve, profile, rng, memtag, sb, ssbs, predres):
	Set is_synthetic to false.
	(crypto): Set is_synthetic to true.
	* config/aarch64/driver-aarch64.c (AARCH64_OPT_EXTENSION): Add
	SYNTHETIC.

gcc/testsuite/ChangeLog:

	PR target/88530
	* gcc.target/aarch64/options_set_1.c: New test.
	* gcc.target/aarch64/options_set_2.c: New test.
	* gcc.target/aarch64/options_set_3.c: New test.
	* gcc.target/aarch64/options_set_4.c: New test.
	* gcc.target/aarch64/options_set_5.c: New test.
	* gcc.target/aarch64/options_set_6.c: New test.
	* gcc.target/aarch64/options_set_7.c: New test.
	* gcc.target/aarch64/options_set_8.c: New test.
	* gcc.target/aarch64/options_set_9.c: New test.

From-SVN: r269193
      Tamar Christina committed
    • Arm: Update Armv8.4-a's FP16 FML intrinsics · 99cf78cf 
      This patch updates the Armv8.4-a FP16 FML intrinsics's suffixes from u32 to f16
to be more consistent with the naming convention for intrinsics.

The specifications for these intrinsics have not been published yet so we do
not need to maintain the old names.

The patch was created with the following script:

grep -lIE "(vfml[as].+)_u32" -r gcc/ | grep -iEv ".+Changelog.*" \
  | xargs sed -i -E -e "s/(vfml[as].+)_u32/\1_f16/g" 

gcc/ChangeLog:

	* config/arm/arm_neon.h (vfmlal_low_u32, vfmlsl_low_u32,
	vfmlal_high_u32, vfmlsl_high_u32, vfmlalq_low_u32, vfmlslq_low_u32,
	vfmlalq_high_u32, vfmlslq_high_u32, vfmlal_lane_low_u32,
	vfmlal_lane_high_u32, vfmlalq_laneq_low_u32, vfmlalq_lane_low_u32,
	vfmlal_laneq_low_u32, vfmlalq_laneq_high_u32, vfmlalq_lane_high_u32,
	vfmlal_laneq_high_u32, vfmlsl_lane_low_u32, vfmlsl_lane_high_u32,
	vfmlslq_laneq_low_u32, vfmlslq_lane_low_u32, vfmlsl_laneq_low_u32,
	vfmlslq_laneq_high_u32, vfmlslq_lane_high_u32, vfmlsl_laneq_high_u32):
	Rename ...
	(vfmlal_low_f16, vfmlsl_low_f16, vfmlal_high_f16, vfmlsl_high_f16,
	vfmlalq_low_f16, vfmlslq_low_f16, vfmlalq_high_f16, vfmlslq_high_f16,
	vfmlal_lane_low_f16, vfmlal_lane_high_f16, vfmlalq_laneq_low_f16,
	vfmlalq_lane_low_f16, vfmlal_laneq_low_f16, vfmlalq_laneq_high_f16,
	vfmlalq_lane_high_f16, vfmlal_laneq_high_f16, vfmlsl_lane_low_f16,
	vfmlsl_lane_high_f16, vfmlslq_laneq_low_f16, vfmlslq_lane_low_f16,
	vfmlsl_laneq_low_f16, vfmlslq_laneq_high_f16, vfmlslq_lane_high_f16,
	vfmlsl_laneq_high_f16): ... To this.
	* config/arm/neon.md: Update comments.

gcc/testsuite/ChangeLog:

	* gcc.target/arm/simd/fp16fml_high.c (test_vfmlal_high_u32,
	test_vfmlalq_high_u32, test_vfmlsl_high_u32, test_vfmlslq_high_u32):
	Rename ....
	(test_vfmlal_high_f16, test_vfmlalq_high_f16, test_vfmlsl_high_f16,
	test_vfmlslq_high_f16): ... To this.
	* gcc.target/arm/simd/fp16fml_lane_high.c (test_vfmlal_lane_high_u32,
	tets_vfmlsl_lane_high_u32, test_vfmlal_laneq_high_u32,
	test_vfmlsl_laneq_high_u32, test_vfmlalq_lane_high_u32,
	test_vfmlslq_lane_high_u32, test_vfmlalq_laneq_high_u32,
	test_vfmlslq_laneq_high_u32): Rename ...
	(test_vfmlal_lane_high_f16, tets_vfmlsl_lane_high_f16,
	test_vfmlal_laneq_high_f16, test_vfmlsl_laneq_high_f16,
	test_vfmlalq_lane_high_f16, test_vfmlslq_lane_high_f16,
	test_vfmlalq_laneq_high_f16, test_vfmlslq_laneq_high_f16): ... To this.
	* gcc.target/arm/simd/fp16fml_lane_low.c (test_vfmlal_lane_low_u32,
	test_vfmlsl_lane_low_u32, test_vfmlal_laneq_low_u32,
	test_vfmlsl_laneq_low_u32, test_vfmlalq_lane_low_u32,
	test_vfmlslq_lane_low_u32, test_vfmlalq_laneq_low_u32,
	test_vfmlslq_laneq_low_u32): Rename ...
	(test_vfmlal_lane_low_f16, test_vfmlsl_lane_low_f16,
	test_vfmlal_laneq_low_f16, test_vfmlsl_laneq_low_f16,
	test_vfmlalq_lane_low_f16, test_vfmlslq_lane_low_f16,
	test_vfmlalq_laneq_low_f16, test_vfmlslq_laneq_low_f16): ... To this.
	* gcc.target/arm/simd/fp16fml_low.c (test_vfmlal_low_u32,
	test_vfmlalq_low_u32, test_vfmlsl_low_u32, test_vfmlslq_low_u32):
	Rename ...
	(test_vfmlal_low_f16, test_vfmlalq_low_f16, test_vfmlsl_low_f16,
	test_vfmlslq_low_f16): ... To this.

From-SVN: r269192
      Tamar Christina committed
    • AArch64: Update Armv8.4-a's FP16 FML intrinsics · 9d04c986 
      This patch updates the Armv8.4-a FP16 FML intrinsics's suffixes from u32 to f16
to be more consistent with the naming convention for intrinsics.

The specifications for these intrinsics have not been published yet so we do
not need to maintain the old names.

The patch was created with the following script:

grep -lIE "(vfml[as].+)_u32" -r gcc/ | grep -iEv ".+Changelog.*" \
  | xargs sed -i -E -e "s/(vfml[as].+)_u32/\1_f16/g"

gcc/ChangeLog:

	* config/aarch64/arm_neon.h (vfmlal_low_u32, vfmlsl_low_u32,
	vfmlalq_low_u32, vfmlslq_low_u32, vfmlal_high_u32, vfmlsl_high_u32,
	vfmlalq_high_u32, vfmlslq_high_u32, vfmlal_lane_low_u32,
	vfmlsl_lane_low_u32, vfmlal_laneq_low_u32, vfmlsl_laneq_low_u32,
	vfmlalq_lane_low_u32, vfmlslq_lane_low_u32, vfmlalq_laneq_low_u32,
	vfmlslq_laneq_low_u32, vfmlal_lane_high_u32, vfmlsl_lane_high_u32,
	vfmlal_laneq_high_u32, vfmlsl_laneq_high_u32, vfmlalq_lane_high_u32,
	vfmlslq_lane_high_u32, vfmlalq_laneq_high_u32, vfmlslq_laneq_high_u32):
	Rename ...
	(vfmlal_low_f16, vfmlsl_low_f16, vfmlalq_low_f16, vfmlslq_low_f16,
	vfmlal_high_f16, vfmlsl_high_f16, vfmlalq_high_f16, vfmlslq_high_f16,
	vfmlal_lane_low_f16, vfmlsl_lane_low_f16, vfmlal_laneq_low_f16,
	vfmlsl_laneq_low_f16, vfmlalq_lane_low_f16, vfmlslq_lane_low_f16,
	vfmlalq_laneq_low_f16, vfmlslq_laneq_low_f16, vfmlal_lane_high_f16,
	vfmlsl_lane_high_f16, vfmlal_laneq_high_f16, vfmlsl_laneq_high_f16,
	vfmlalq_lane_high_f16, vfmlslq_lane_high_f16, vfmlalq_laneq_high_f16,
	vfmlslq_laneq_high_f16): ... To this.

gcc/testsuite/ChangeLog:

	* gcc.target/aarch64/fp16_fmul_high.h (test_vfmlal_high_u32,
	test_vfmlalq_high_u32, test_vfmlsl_high_u32, test_vfmlslq_high_u32):
	Rename ...
	(test_vfmlal_high_f16, test_vfmlalq_high_f16, test_vfmlsl_high_f16,
	test_vfmlslq_high_f16): ... To this.
	* gcc.target/aarch64/fp16_fmul_lane_high.h (test_vfmlal_lane_high_u32,
	tets_vfmlsl_lane_high_u32, test_vfmlal_laneq_high_u32,
	test_vfmlsl_laneq_high_u32, test_vfmlalq_lane_high_u32,
	test_vfmlslq_lane_high_u32, test_vfmlalq_laneq_high_u32,
	test_vfmlslq_laneq_high_u32): Rename ...
	(test_vfmlal_lane_high_f16, tets_vfmlsl_lane_high_f16,
	test_vfmlal_laneq_high_f16, test_vfmlsl_laneq_high_f16,
	test_vfmlalq_lane_high_f16, test_vfmlslq_lane_high_f16,
	test_vfmlalq_laneq_high_f16, test_vfmlslq_laneq_high_f16): ... To this.
	* gcc.target/aarch64/fp16_fmul_lane_low.h (test_vfmlal_lane_low_u32,
	test_vfmlsl_lane_low_u32, test_vfmlal_laneq_low_u32,
	test_vfmlsl_laneq_low_u32, test_vfmlalq_lane_low_u32,
	test_vfmlslq_lane_low_u32, test_vfmlalq_laneq_low_u32,
	test_vfmlslq_laneq_low_u32): Rename ...
	(test_vfmlal_lane_low_f16, test_vfmlsl_lane_low_f16,
	test_vfmlal_laneq_low_f16, test_vfmlsl_laneq_low_f16,
	test_vfmlalq_lane_low_f16, test_vfmlslq_lane_low_f16,
	test_vfmlalq_laneq_low_f16, test_vfmlslq_laneq_low_f16): ... To this.
	* gcc.target/aarch64/fp16_fmul_low.h (test_vfmlal_low_u32,
	test_vfmlalq_low_u32, test_vfmlsl_low_u32, test_vfmlslq_low_u32):
	Rename ...
	(test_vfmlal_low_f16, test_vfmlalq_low_f16, test_vfmlsl_low_f16,
	test_vfmlslq_low_f16): ... To This.
	* lib/target-supports.exp
	(check_effective_target_arm_fp16fml_neon_ok_nocache): Update test.

From-SVN: r269191
      Tamar Christina committed
    • re PR fortran/89282 (Garbage arithmetics results in fortran with -O3 and overloaded operators) · 6388eda0 
      2019-02-25  Dominique d'Humieres  <dominiq@gcc.gnu.org>

	PR fortran/89282
	* gfortran.dg/overload_3.f90: New test.

From-SVN: r269190
      Dominique d'Humieres committed
    • df-scan: fix use of mw_order in df_mw_compare (PR 86096) · 74a4de68 
      	PR rtl-optimization/86096
	* df-scan.c (df_mw_compare): Do not check mw_reg fields when
	comparing mw_order values.

From-SVN: r269189
      Alexander Monakov committed
    • re PR c++/89285 (ICE after casting the this pointer in the constructor in C++17 mode) · ea229aa8 
      	PR c++/89285
	* g++.dg/cpp1y/constexpr-89285-2.C: New test.

From-SVN: r269188
      Jakub Jelinek committed
    • re PR libfortran/89274 (Inconsistent list directed output of INTEGER(16)) · b8f41284 
      2019-02-25  Dominique d'Humieres  <dominiq@gcc.gnu.org>

	PR libfortran/89274
	* gfortran.dg/list_directed_large.f90: New test. 

2019-02-25  Dominique d'Humieres  <dominiq@gcc.gnu.org>

	PR libfortran/89274
	* io/write.c (write_integer): Add width for INTEGER(16).

From-SVN: r269187
      Dominique d'Humieres committed
    • re PR target/89434 (wrong code with -Og and __builtin_mul_overflow()) · 5c561248 
      	PR target/89434
	* config/arm/arm.md (*subsi3_carryin_const): Use
	arm_neg_immediate_operand predicate instead of
	arm_not_immediate_operand, "L" constraint instead of "K" and
	print it using %n2 instead of %B2.
	(*subsi3_carryin_const0): New define_insn.
	(*subsi3_carryin_compare_const): Use const_int_I_operand predicate
	instead of arm_not_operand and "I" constraint instead of "K" and
	print it using %n3 instead of %B2.  Instead of using match_dup 2 add
	another match_operand and in the condition check that it is negation
	of operands[2].
	(*subsi3_carryin_compare_const0): New define_ins.
	(*subdi_di_zesidi): Adjust to use *subsi3_carryin_const0 instead of
	*subsi3_carryin_const.
	(*arm_cmpdi_insn): Fix splitting into *subsi3_carryin_compare_const,
	split into *subsi3_carryin_compare_const0 if the highpart is zero.

	* gcc.c-torture/execute/pr89434.c: New test.

From-SVN: r269186
      Jakub Jelinek committed
    • re PR target/89438 (ICE in glibc/sysdeps/ieee754/dbl-64/e_pow.c (internal… · 4199c859 
      re PR target/89438 (ICE in glibc/sysdeps/ieee754/dbl-64/e_pow.c (internal compiler error: in decompose, at rtl.h:2266))

	PR target/89438
	* config/arm.vfp.md (*negdf2_vfp): Use
	gen_int_mode (0x80000000, SImode) instead of GEN_INT (0x80000000).
	* config/arm/neon.md (neon_copysignf<mode>): Likewise.

	* gcc.dg/pr89438.c: New test.

From-SVN: r269185
      Jakub Jelinek committed
    • Daily bump. · 82eadb94 
      From-SVN: r269183
      GCC Administrator committed