* tree-ssa-loop-niter.c (number_of_iterations_exit): Revert accidental
	commit.

From-SVN: r236847

    
	* Makefile.tpl (configure): Depend on m4 files included.
	* Makefile.in: Regenerate.

From-SVN: r236846

	* dominance.c (verify_dominators): Don't segfault on NULL imm_bb.

From-SVN: r236845

From-SVN: r236844

Follow the same practice as other places in ira.c, where
free_dominance_info is called along with loop_optimizer_finalize.  Not
doing so causes an ICE on gcc-5-branch, so avoid that possibility on
trunk.

	PR rtl-optimization/71275
	* ira.c (ira): Free dominance info.

From-SVN: r236843

From-SVN: r236842

	* doc/xml/manual/abi.xml: Adjust URL to use https.
	* doc/html/manual/*: Regenerate.

From-SVN: r236837

From-SVN: r236836

/cp
2016-05-27  Paolo Carlini  <paolo.carlini@oracle.com>

	PR c++/60385
	* name-lookup.c (push_namespace): Return bool, false when pushdecl
	fails.
	* name-lookup.h (push_namespace): Adjust declaration.
	* parser.c (cp_parser_namespace_definition): Check push_namespace
	return value.

/testsuite
2016-05-27  Paolo Carlini  <paolo.carlini@oracle.com>

	PR c++/60385
	* g++.dg/parse/namespace13.C: New.

From-SVN: r236835

2016-05-27  Thomas Preud'homme  <thomas.preudhomme@arm.com>

    gcc/
    * config/arm/arm.h (TARGET_ARM_V6M): Remove.
    (TARGET_ARM_V7M): Likewise.

From-SVN: r236832

	* tree-ssa-threadedge.c: Remove include of tree-ssa-threadbackward.h.
	(thread_across_edge): Remove calls to find_jump_threads_backwards.
	* passes.def: Add jump threading passes before DOM/VRP.
	* tree-ssa-threadbackward.c (find_jump_threads_backwards): Change
	argument to a basic block from an edge.  Remove tests which are
	handled elsewhere.
	(pass_data_thread_jumps, class pass_thread_jumps): New.
	(pass_thread_jumps::gate, pass_thread_jumps::execute): New.
	(make_pass_thread_jumps): Likewise.
	* tree-pass.h (make_pass_thread_jumps): Declare.

	* gcc.dg/tree-ssa/pr21417.c: Update expected output.
	* gcc.dg/tree-ssa/pr66752-3.c: Likewise.
	* gcc.dg/tree-ssa/pr68198.c: Likewise.
	* gcc.dg/tree-ssa/pr69196-1.c: Likewise.
	* gcc.dg/tree-ssa/pr69270-3.c: Likewise.
	* gcc.dg/tree-ssa/ssa-dom-thread-2b.c: Likewise.
	* gcc.dg/tree-ssa/ssa-dom-thread-2g.c: Likewise.
	* gcc.dg/tree-ssa/ssa-dom-thread-2h.c: Likewise.
	* gcc.dg/tree-ssa/ssa-dom-thread-6.c: Likewise.
	* gcc.dg/tree-ssa/ssa-dom-thread-7.c: Likewise.
	* gcc.dg/tree-ssa/ssa-dom-thread-12.c: Likewise.
	* gcc.dg/tree-ssa/ssa-dom-thread-13.c: Likewise.
	* gcc.dg/tree-ssa/vrp56.c: Likewise.

From-SVN: r236831

	* config/visium/visium-protos.h (split_double_move): Rename into...
	(visium_split_double_move): ...this.
	(visium_split_double_add): Declare.
	* config/visium/visium.c (split_double_move): Rename into...
	(visium_split_double_move): ...this.
	(visium_split_double_add): New function.
	(visium_expand_copysign): Renumber operands for consistency.
	* config/visium/visium.md (DImode move splitter): Adjust to renaming.
	(DFmode move splitter): Likewise.
	(*addi3_insn): Split by means of visium_split_double_add.
	(*adddi3_insn_flags): Delete.
	(*plus_plus_sltu<subst_arith>): New insn.
	(*subdi3_insn): Split by means of visium_split_double_add.
	(subdi3_insn_flags): Delete.
	(*minus_minus_sltu<subst_arith>): New insn.
	(*negdi2_insn): Split by means of visium_split_double_add.
	(*negdi2_insn_flags): Delete.

From-SVN: r236827

/cp
	PR c++/69855
	* name-lookup.c (pushdecl_maybe_friend_1): Push local function
	decls into the global scope after stripping template bits
	and setting DECL_ANTICIPATED.

/testsuite
	PR c++/69855
	* g++.dg/overload/69855.C: New.
	* g++.old-deja/g++.law/missed-error2.C: Adjust.
	* g++.old-deja/g++.pt/crash3.C: Likewise.

From-SVN: r236826

	* configure.ac: Treat a --with-headers option without argument
	the same as the default (i.e. consult sys-include directory).
	* configure: Regenerate.

From-SVN: r236825

From-SVN: r236823

2016-05-24  Ville Voutilainen  <ville.voutilainen@gmail.com>

	PR libstdc++/66338
	* include/std/tuple (_TMC): Add a check for _NotSameTuple.
	* include/std/tuple (tuple(_UElements&&...)): Remove the separate
	check for _NotSameTuple.
	* include/std/tuple (_TMCT): New.
	* include/std/tuple (tuple(const tuple<_UElements...>&)): Use it.
	* include/std/tuple (tuple(tuple<_UElements...>&&)): Likewise.
	* include/std/tuple (tuple(allocator_arg_t, const _Alloc&,
	      const tuple<_UElements...>&)): Likewise.
	* include/std/tuple (tuple(allocator_arg_t, const _Alloc&,
	      tuple<_UElements...>&&)): Likewise.
	* testsuite/20_util/tuple/cons/66338.cc: New.

From-SVN: r236822

	* config/aarch64/aarch64.c (aarch64_fusion_enabled_p): New function.
	* config/aarch64/aarch64-protos.h (aarch64_fusion_enabled_p): Declare
	prototype.
	* config/aarch64/aarch64-simd.md (aarch64_crypto_aes<aesmc_op>v16qi):
	Add "=w,0" alternative.  Enable it when AES/AESMC fusion is enabled.

From-SVN: r236820

gcc/
	PR target/63596
	* config/aarch64/aarch64.c (aarch64_expand_builtin_va_start): Honor
	tree-stdarg analysis results.
	(aarch64_setup_incoming_varargs): Likewise.

gcc/testsuite/
	* gcc.target/aarch64/va_arg_1.c: New testcase.
	* gcc.target/aarch64/va_arg_2.c: Likewise.
	* gcc.target/aarch64/va_arg_3.c: Likewise.

From-SVN: r236819

gcc/
	* config/aarch64/aarch64.c (aarch64_build_builtin_va_list): Initialize
	va_list_gpr_counter_field and va_list_fpr_counter_field.

gcc/testsuite/
	* gcc.dg/tree-ssa/stdarg-2.c: Enable all testcases for AArch64.
	* gcc.dg/tree-ssa/stdarg-3.c: Likewise.
	* gcc.dg/tree-ssa/stdarg-4.c: Likewise.
	* gcc.dg/tree-ssa/stdarg-5.c: Likewise.
	* gcc.dg/tree-ssa/stdarg-6.c: Likewise.

From-SVN: r236818

Remove aarch64_cannot_change_mode_class as the underlying issue
(PR67609) has been resolved.  This avoids a few unnecessary lane
widening operations like:

faddp   d18, v18.2d
mov     d18, v18.d[0]

    gcc/
	PR67609
	* config/aarch64/aarch64.h (CANNOT_CHANGE_MODE_CLASS): Remove.
	* config/aarch64/aarch64.c
	(aarch64_cannot_change_mode_class): Remove function.
	* config/aarch64/aarch64-protos.h
	(aarch64_cannot_change_mode_class): Remove.

From-SVN: r236817

	* cfgloop.c (record_niter_bound): Record likely upper bounds.
	(likely_max_stmt_executions_int, get_likely_max_loop_iterations,
	get_likely_max_loop_iterations_int): New.
	* cfgloop.h (struct loop): Add nb_iterations_likely_upper_bound,
	any_likely_upper_bound.
	(get_likely_max_loop_iterations_int, get_likely_max_loop_iterations):
	Declare.
	* cfgloopmanip.c (copy_loop_info): Copy likely upper bounds.
	* loop-unroll.c (unroll_loop_constant_iterations): Update likely
	upper bound.
	(unroll_loop_constant_iterations): Likewise.
	(unroll_loop_runtime_iterations): Likewise.
	* lto-streamer-in.c (input_cfg): Stream likely upper bounds.
	* lto-streamer-out.c (output_cfg): Likewise.
	* tree-ssa-loop-ivcanon.c (try_peel_loop): Update likely upper
	bounds.
	(canonicalize_loop_induction_variables): Dump likely upper bounds.
	* tree-ssa-loop-niter.c (record_estimate): Record likely upper bounds.
	(likely_max_loop_iterations): New.
	(likely_max_loop_iterations_int): New.
	(likely_max_stmt_executions): New.
	* tree-ssa-loop-niter.h (likely_max_loop_iterations,
	likely_max_loop_iterations_int, likely_max_stmt_executions_int,
	likely_max_stmt_executions): Declare.

From-SVN: r236816

	PR middle-end/71308
	* gimple-fold.c (gimple_fold_call): Check that LHS is not null.

	* g++.dg/torture/pr71308.C: New test.

From-SVN: r236815

gcc/ChangeLog:

2016-05-27  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>

	* config/s390/s390.md (2x risbg splitters): Use
	reg_overlap_mentioned_p instead of rtx_equal_p.

From-SVN: r236814

gcc/ChangeLog:

	* combine.c (make_compound_operation): Take known zero bits into
	account when checking for possible zero_extend.

gcc/testsuite/ChangeLog:

	* gcc.dg/zero_bits_compound-1.c: New test.
	* gcc.dg/zero_bits_compound-2.c: New test.

From-SVN: r236813

	* config/aarch64/aarch64.md (ashl<mode>3, SHORT modes):
	Use const_int_operand for operand 2 predicate.  Simplify expand code
	as a result.

From-SVN: r236812

gcc/

	PR middle-end/71279
	* fold-const.c (fold_ternary_loc): Don't fold VEC_COND_EXPR
	into comparison.

gcc/testsuite/

	PR middle-end/71279
	* gcc.dg/pr71279.c: New test.

From-SVN: r236810

	* config/aarch64/aarch64-modes.def (CC_ZESWP, CC_SESWP): Delete.
	* config/aarch64/aarch64.c (aarch64_select_cc_mode): Remove condition
	that returns CC_SESWPmode and CC_ZESWPmode.
	(aarch64_get_condition_code_1): Remove handling of CC_SESWPmode
	and CC_SESWPmode.
	(aarch64_rtx_costs): Likewise.

From-SVN: r236809

From-SVN: r236804

[gcc]
2016-05-26  Michael Meissner  <meissner@linux.vnet.ibm.com>

	* config/rs6000/rs6000.c (rs6000_emit_p9_fp_minmax): New function
	for ISA 3.0 min/max support.
	(rs6000_emit_p9_fp_cmove): New function for ISA 3.0 floating point
	conditional move support.
	(rs6000_emit_cmove): Call rs6000_emit_p9_fp_minmax and
	rs6000_emit_p9_fp_cmove if the ISA 3.0 instructions are
	available.
	* config/rs6000/rs6000.md (SFDF2): New iterator to allow doing
	conditional moves where the comparison type is different from move
	type.
	(fp_minmax): New code iterator for smin/smax.
	(minmax): New code attributes for min/max.
	(SMINMAX): Likewise.
	(smax<mode>3): Combine min, max insns into one insn using the
	fp_minmax code iterator.  Add support for ISA 3.0 min/max
	instructions that don't need -ffast-math.
	(s<minmax><mode>3): Likewise.
	(smax<mode>3_vsx): Likewise.
	(smin<mode>3): Likewise.
	(s<minmax><mode>3_vsx): Likewise.
	(smin<mode>3_vsx): Likewise.
	(pre-VSX min/max splitters): Likewise.
	(s<minmax><mode>3_fpr): Likewise.
	(movsfcc): Rewrite floating point conditional moves to combine
	SFmode/DFmode into a single insn.
	(mov<mode>cc): Likewise.
	(movdfcc): Likewise.
	(fselsfsf4): Combine FSEL cases into a single insn, using SFDF and
	SFDF2 iterators to handle all combinations.
	(fseldfsf4): Likewise.
	(fsel<SFDF:mode><SFDF2:mode>4): Likewise.
	(fseldfdf4): Likewise.
	(fselsfdf4): Likewise.
	(mov<SFDF:mode><SFDF2:mode>cc_p9): Add support for the ISA 3.0
	comparison instructions that set a 0/-1 mask, and use it for
	floating point conditional move via XXSEL.
	(fpmask<mode>): Likewise.
	(xxsel<mode>): Likewise.
	* config/rs6000/predicates.md (min_max_operator): Delete, no
	longer used.
	(fpmask_comparison_operaton): New insn for ISA 3.0 comparison
	instructions that generate a 0/-1 mask for use with XXSEL.
	* config/rs6000/rs6000.h (TARGET_MINMAX_SF): New helper macros to
	say whether floating point min/max is available, either through
	FSEL, ISA 2.06 min/max, and ISA 3.0 min/max instrucitons.
	(TARGET_MINMAX_DF): Likewise.

[gcc/testsuite]
2016-05-26  Michael Meissner  <meissner@linux.vnet.ibm.com>

	* gcc.target/powerpc/p9-minmax-1.c: New tests for ISA 3.0
	floating point min/max/comparison instructions.
	* gcc.target/powerpc/p9-minmax-2.c: Likewise.

From-SVN: r236795

c-parser.c (c_parser_omp_clause_schedule): Warn if OMP_CLAUSE_SCHEDULE_CHUNK_EXPR is known not to be positive.

	* c-parser.c (c_parser_omp_clause_schedule): Warn if
	OMP_CLAUSE_SCHEDULE_CHUNK_EXPR is known not to be positive.

	* semantics.c (finish_omp_clauses) <case OMP_CLAUSE_SCHEDULE>: Warn
	if OMP_CLAUSE_SCHEDULE_CHUNK_EXPR is known not to be positive.

	* openmp.c (resolve_omp_clauses): Warn if chunk_size is known not to
	be positive.

	* c-c++-common/gomp/schedule-1.c: New test.
	* gfortran.dg/gomp/schedule-1.f90: New test.

	* testsuite/libgomp.c/doacross-1.c (main): Use schedule(static)
	instead of invalid schedule(static, 0).
	* testsuite/libgomp.c/doacross-2.c (main): Likewise.

From-SVN: r236793

gcc/cp/ChangeLog:

	PR c++/70822
	PR c++/70106
	* cp-tree.h (REF_PARENTHESIZED_P): Make this flag apply to
	SCOPE_REFs too.
	* pt.c (tsubst_qualified_id): If REF_PARENTHESIZED_P is set
	on the qualified_id then propagate it to the resulting
	expression.
	(do_auto_deduction): Check REF_PARENTHESIZED_P on SCOPE_REFs
	too.
	* semantics.c (force_paren_expr): If given a SCOPE_REF, just set
	its REF_PARENTHESIZED_P flag.

gcc/testsuite/ChangeLog:

	PR c++/70822
	PR c++/70106
	* g++.dg/cpp1y/auto-fn32.C: New test.
	* g++.dg/cpp1y/paren4.C: New test.

From-SVN: r236792

	PR rtl-optimization/71275
	* ira.c (ira): Call loop_optimizer_init to set up bb_loop_depth
	for update_equiv_regs and combine_and_move_insns.

From-SVN: r236789

	* config/i386/i386.md (*movqi_internal) <attr "isa">: Use
	if_then_else or cond RTXes to calculate attribute value.
	* config/i386/mmx.md (*vec_extractv2sf_1) <attr "prefix_rep">: Ditto.
	<attr "length_immediate>: Ditto.
	(*vec_extractv2sf_1) <attr "length_immediate">: Ditto.
	* config/i386/sse.md (sse_loadlps) <attr "length_immediate">: Ditto.
	(*vec_concatv2sf_sse4_1) <attr "isa">: Ditto.
	<attr "type">: Ditto.
	<attr "prefix_data16">: Ditto.
	<attr "prefix_extra">: Ditto.
	<attr "length_immediate">: Ditto.
	<attr "prefix">: Ditto.
	(vec_set<mode>_0) <attr "isa">: Ditto.
	<attr "prefix_extra">: Ditto.
	<attr "length_immediate">: Ditto.
	<attr "prefix">: Ditto.
	(*vec_interleave_highv2df) <attr "prefix_data16">: Ditto.
	(*vec_interleave_lowv2df) <attr "prefix_data16">: Ditto.
	(sse2_storelpd) <attr "prefix_data16">: Ditto.
	(sse2_loadhpd) <attr "prefix_data16">: Ditto.
	(sse2_loadlpd) <attr "prefix_data16">: Ditto.
	<attr "length_immediate">: Ditto.
	<attr "prefix">: Ditto.
	(sse2_movsd) <attr "length_immediate">: Ditto.
	<attr "prefix">: Ditto.
	(vec_concatv2df)  <attr "isa">: Ditto.
	<attr "prefix">: Ditto.
	(*vec_extractv4si) <attr "prefix_extra">: Ditto.
	(*vec_extractv2di_1) <attr "isa">: Ditto.
	<attr "type">: Ditto.
	<attr "length_immediate">: Ditto.
	<attr "prefix_rex">: Ditto.
	<attr "prefix_extra">: Ditto.
	(*vec_concatv2si_sse4_1) <attr "type">: Ditto.
	<attr "prefix_extra">: Ditto.
	<attr "length_immediate">: Ditto.
	(vec_concatv2di) <attr "isa">: Ditto.
	<attr "prefix_extra">: Ditto.
	<attr "length_immediate">: Ditto.
	<attr "prefix">: Ditto.

From-SVN: r236787

	* tree-ssa-loop-ivopts.c (comp_cost::infinite_cost_p): New
	function.
	(operator+): Likewise.
	(operator-): Likewise.
	(comp_cost::operator+=): Likewise.
	(comp_cost::operator-=): Likewise.
	(comp_cost::operator/=): Likewise.
	(comp_cost::operator*=): Likewise.
	(operator<): Likewise.
	(operator==): Likewise.
	(operator<=): Likewise.
	(new_cost): Remove.
	(infinite_cost_p): Likewise.
	(add_costs): Likewise.
	(sub_costs): Likewise.
	(compare_costs): Likewise.
	(set_group_iv_cost): Use the newly introduced functions.
	(get_address_cost): Likewise.
	(get_shiftadd_cost): Likewise.
	(force_expr_to_var_cost): Likewise.
	(split_address_cost): Likewise.
	(ptr_difference_cost): Likewise.
	(difference_cost): Likewise.
	(get_computation_cost_at): Likewise.
	(determine_group_iv_cost_generic): Likewise.
	(determine_group_iv_cost_address): Likewise.
	(determine_group_iv_cost_cond): Likewise.
	(autoinc_possible_for_pair): Likewise.
	(determine_group_iv_costs): Likewise.
	(cheaper_cost_pair): Likewise.
	(iv_ca_recount_cost): Likewise.
	(iv_ca_set_no_cp): Likewise.
	(iv_ca_set_cp): Likewise.
	(iv_ca_cost): Likewise.
	(iv_ca_new): Likewise.
	(iv_ca_dump): Likewise.
	(iv_ca_narrow): Likewise.
	(iv_ca_prune): Likewise.
	(iv_ca_replace): Likewise.
	(try_add_cand_for): Likewise.
	(try_improve_iv_set): Likewise.
	(find_optimal_iv_set): Likewise.

From-SVN: r236785

tree-ssa-loop-ivopts.c:loop_body_includes_call was treating internal
calls such as IFN_SQRT as clobbering all caller-saved registers, which
I don't think is appropriate for any current internal function.

Tested on aarch64-linux-gnu and x86_64-linux-gnu.

gcc/
	* tree-ssa-loop-ivopts.c (loop_body_includes_call): Don't assume
	that internal functions will clobber all caller-saved registers.

From-SVN: r236780

	* gcc.dg/20060410.c: Xfail on ptx.
	* gcc.dg/torture/c99-contract-1.c: Skip on ptx.
	* c-c++-common/torture/complex-sign-mixed-add.c: Skip on ptx -O0
	* c-c++-common/torture/complex-sign-mixed-sub.c: Skip on ptx -O0
	* gcc.c-torture/execute/pr68185.c: Skip on ptx -O0 & Os.
	* gcc.c-torture/execute/20020529-1.c: Skip on ptx -00.

From-SVN: r236774

	* config/nvptx/free.asm: Delete.
	* config/nvptx/malloc.asm: Delete.
	* config/nvptx/realloc.c: Delete.
	* t-nvptx: Update.

From-SVN: r236773

2016-05-26  Chung-Lin Tang  <cltang@codesourcery.com>

	libgomp/
	* oacc-plugin.h (GOMP_PLUGIN_async_unmap_vars): Add int parameter.
	* oacc-plugin.c (GOMP_PLUGIN_async_unmap_vars): Add 'int async'
	parameter, use to set async stream around call to gomp_unmap_vars,
	call gomp_unmap_vars() with 'do_copyfrom' set to true.
	* plugin/plugin-nvptx.c (struct ptx_event): Add 'int val' field.
	(event_gc): Adjust event handling loop, collect PTX_EVT_ASYNC_CLEANUP
	events and call GOMP_PLUGIN_async_unmap_vars() for each of them.
	(event_add): Add int parameter, initialize 'val' field when
	adding new ptx_event struct.
	(nvptx_evec): Adjust event_add() call arguments.
	(nvptx_host2dev): Likewise.
	(nvptx_dev2host): Likewise.
	(nvptx_wait_async): Likewise.
	(nvptx_wait_all_async): Likewise.
	(GOMP_OFFLOAD_openacc_register_async_cleanup): Add async parameter,
	pass to event_add() call.
	* oacc-host.c (host_openacc_register_async_cleanup): Add 'int async'
	parameter.
	* oacc-mem.c (gomp_acc_remove_pointer): Adjust async case to
	call openacc.register_async_cleanup_func() hook.
	* oacc-parallel.c (GOACC_parallel_keyed): Likewise.
	* target.c (gomp_copy_from_async): Delete function.
	(gomp_map_vars): Remove async_refcount.
	(gomp_unmap_vars): Likewise.
	(gomp_load_image_to_device): Likewise.
	(omp_target_associate_ptr): Likewise.
	* libgomp.h (struct splay_tree_key_s): Remove async_refcount.
	(acc_dispatch_t.register_async_cleanup_func): Add int parameter.
	(gomp_copy_from_async): Remove.

From-SVN: r236772

GCC expands switch statements in a very simplistic way and tries to use a table
expansion even when it is a bad idea for performance or codesize.
GCC typically emits extremely sparse tables that contain mostly default entries
(something which currently cannot be tuned by backends).  Additionally the
computation of the minimum/maximum label offsets is too simplistic so the
tables are often twice as large as necessary.

The cost of a table switch is significant due to the setup overhead, the table
lookup (which due to being sparse and large adds unnecessary cachemisses)
and hard to predict indirect jump.  Therefore it is best to avoid using a table
unless there are many real case labels.

This patch fixes that by setting the default aarch64_case_values_threshold to
16 when the per-CPU tuning is not set.  On SPEC2006 this improves the switch
heavy benchmarks GCC and perlbench both in performance (1-2%) as well as size
(0.5-1% smaller).

    gcc/
	* config/aarch64/aarch64.c (aarch64_case_values_threshold):
	Return a better case_values_threshold when optimizing.

From-SVN: r236771

so increase the cost of integer registers slightly to avoid unnecessary int<->FP
moves. This improves register allocation of scalar SIMD operations.

        * config/aarch64/aarch64-simd.md (aarch64_combinez):
        Add ? to integer variant.
        (aarch64_combinez_be): Likewise.

From-SVN: r236770