Commit 5e4d7abe by Wilco Dijkstra Committed by Wilco Dijkstra

SIMD operations like combine prefer to have their operands in FP registers,

so increase the cost of integer registers slightly to avoid unnecessary int<->FP
moves. This improves register allocation of scalar SIMD operations.

        * config/aarch64/aarch64-simd.md (aarch64_combinez):
        Add ? to integer variant.
        (aarch64_combinez_be): Likewise.

From-SVN: r236770
parent ffa8b552
2016-05-26 Wilco Dijkstra <wdijkstr@arm.com>
* config/aarch64/aarch64-simd.md (aarch64_combinez):
Add ? to integer variant.
(aarch64_combinez_be): Likewise.
2016-05-26 Jakub Jelinek <jakub@redhat.com>
* config/i386/sse.md (*vcvtps2ph_store<mask_name>): Use v constraint
......
......@@ -2622,7 +2622,7 @@
(define_insn "*aarch64_combinez<mode>"
[(set (match_operand:<VDBL> 0 "register_operand" "=w,w,w")
(vec_concat:<VDBL>
(match_operand:VD_BHSI 1 "general_operand" "w,r,m")
(match_operand:VD_BHSI 1 "general_operand" "w,?r,m")
(match_operand:VD_BHSI 2 "aarch64_simd_imm_zero" "Dz,Dz,Dz")))]
"TARGET_SIMD && !BYTES_BIG_ENDIAN"
"@
......@@ -2638,7 +2638,7 @@
[(set (match_operand:<VDBL> 0 "register_operand" "=w,w,w")
(vec_concat:<VDBL>
(match_operand:VD_BHSI 2 "aarch64_simd_imm_zero" "Dz,Dz,Dz")
(match_operand:VD_BHSI 1 "general_operand" "w,r,m")))]
(match_operand:VD_BHSI 1 "general_operand" "w,?r,m")))]
"TARGET_SIMD && BYTES_BIG_ENDIAN"
"@
mov\\t%0.8b, %1.8b
......
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