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riscv-gcc-1
Commit f9610d20 by Uros Bizjak
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i386.c (ix86_trampoline_init): Switch arms of if expr. 

	* config/i386/i386.c (ix86_trampoline_init): Switch arms of if expr.
	Use offset everywhere.  Always assert that offset <= TRAMPOLINE_SIZE.

From-SVN: r176173
parent 4d4a9b72
Showing with 97 additions and 105 deletions
gcc/ChangeLog
2011-07-11 Uros Bizjak <ubizjak@gmail.com>
* config/i386/i386.c (ix86_trampoline_init): Switch arms of if expr.
Use offset everywhere. Always assert that offset <= TRAMPOLINE_SIZE.
2011-07-11 Jakub Jelinek <jakub@redhat.com>
PR debug/49676
......@@ -74,7 +79,7 @@
after induction variable optimization.
2011-07-11 Georg-Johann Lay <avr@gjlay.de>
PR target/39633
* config/avr/avr.c (notice_update_cc): For ashiftrt:QI, only
offsets 1..5 set cc0 in a usable way.
......@@ -191,8 +196,7 @@
PR debug/49676
* dwarf2out.c (size_of_int_loc_descriptor): New function.
(address_of_int_loc_descriptor): Use it.
(scompare_loc_descriptor): Optimize EQ/NE comparison with
constant.
(scompare_loc_descriptor): Optimize EQ/NE comparison with constant.
2011-07-09 Richard Henderson <rth@redhat.com>
......@@ -249,8 +253,7 @@
PR target/49621
* config/rs6000/rs6000.c (rs6000_emit_vector_cond_expr): Use
CONST0_RTX (dest_mode) instead of const0_rtx as second operand
of NE.
CONST0_RTX (dest_mode) instead of const0_rtx as second operand of NE.
* config/rs6000/vector.md (vector_select_<mode>,
vector_select_<mode>_uns): Change second operand of NE to
CONST0_RTX (<MODE>mode) instead of const0_rtx.
......@@ -266,7 +269,7 @@
continue from loop, add one more assert.
2011-07-08 Georg-Johann Lay <avr@gjlay.de>
PR target/46779
* config/avr/avr.c (avr_hard_regno_mode_ok): Rewrite.
In particular, allow 8-bit values in r28 and r29.
......@@ -347,8 +350,7 @@
* optabs.c (expand_binop): Tighten conditions for doubleword
expansions.
(widen_bswap): Assert that mode bitsize and precision are the
same.
(widen_bswap): Assert that mode bitsize and precision are the same.
* stor-layout.c (get_best_mode): Skip modes that have lower
precision than bitsize.
* recog.c (simplify_while_replacing): Assert that bitsize and
......@@ -545,8 +547,7 @@
2011-07-07 Joseph Myers <joseph@codesourcery.com>
* config/i386/t-crtpic, config/i386/t-svr3dbx, config/pa/t-pa:
Remove.
* config/i386/t-crtpic, config/i386/t-svr3dbx, config/pa/t-pa: Remove.
2011-07-07 Bernd Schmidt <bernds@codesourcery.com>
......@@ -574,8 +575,7 @@
2011-07-07 H.J. Lu <hongjiu.lu@intel.com>
* config.gcc: Support --with-multilib-list for x86 Linux
targets.
* config.gcc: Support --with-multilib-list for x86 Linux targets.
* configure.ac: Mention x86-64 for --with-multilib-list.
* configure: Regenerated.
......@@ -609,8 +609,7 @@
* config/i386/t-linux64: Support TM_MULTILIB_CONFIG.
* doc/install.texi: Document --with-multilib-list for
Linux/x86-64.
* doc/install.texi: Document --with-multilib-list for Linux/x86-64.
* doc/invoke.texi: Document -mx32.
......@@ -660,24 +659,18 @@
(TARGET_HAVE_NAMED_SECTIONS): Don't define.
* common/config/m32c/m32c-common.c: Remove.
* config.gcc (m32c*-*-*): Set target_has_targetm_common=no.
* config/alpha/osf5.h (TARGET_HAVE_NAMED_SECTIONS): Define to
false.
* config/i386/openbsd.h (TARGET_HAVE_NAMED_SECTIONS): Define to
false.
* config/m68k/openbsd.h (TARGET_HAVE_NAMED_SECTIONS): Define to
false.
* config/alpha/osf5.h (TARGET_HAVE_NAMED_SECTIONS): Define to false.
* config/i386/openbsd.h (TARGET_HAVE_NAMED_SECTIONS): Define to false.
* config/m68k/openbsd.h (TARGET_HAVE_NAMED_SECTIONS): Define to false.
* config/pa/som.h (TARGET_HAVE_NAMED_SECTIONS): Define to false.
* config/pdp11/pdp11.h (TARGET_HAVE_NAMED_SECTIONS): Define to
false.
* config/vax/openbsd.h (TARGET_HAVE_NAMED_SECTIONS): Define to
false.
* config/pdp11/pdp11.h (TARGET_HAVE_NAMED_SECTIONS): Define to false.
* config/vax/openbsd.h (TARGET_HAVE_NAMED_SECTIONS): Define to false.
2011-07-07 Jakub Jelinek <jakub@redhat.com>
PR middle-end/49640
* gimplify.c (gimplify_compound_lval): For last 2 ARRAY_*REF
operands and last COMPONENT_REF operand call gimplify_expr on it
if non-NULL.
* gimplify.c (gimplify_compound_lval): For last 2 ARRAY_*REF operands
and last COMPONENT_REF operand call gimplify_expr on it if non-NULL.
2011-07-07 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
......@@ -708,8 +701,7 @@
(ASM_SPEC): Redefine.
(DEFAULT_ARCH32_P): Define using TARGET_64BIT_DEFAULT.
* config/host-solaris.c [__x86_64__] (TRY_EMPTY_VM_SPACE): Reduce.
* doc/install.texi (Specific, amd64-*-solaris2.1[0-9]*):
Document.
* doc/install.texi (Specific, amd64-*-solaris2.1[0-9]*): Document.
(Specific, i?86-*-solaris2.10): Mention x86_64-*-solaris2.1[0-9]*
configuration.
(Specific, x86_64-*-solaris2.1[0-9]*): Document.
......@@ -724,7 +716,7 @@
* config/sparc/sol2.h (ASM_SPEC): Redefine.
2011-07-07 Georg-Johann Lay <avr@gjlay.de>
* config/avr/avr.md (*reload_insi): Change predicate #1 to
const_int_operand. Ditto for peep2 producing this insn.
Add argument to output_reload_insisf call.
......@@ -787,11 +779,10 @@
Revert:
* simplify-rtx.c (simplify_const_binary_operation): Use the
shift_truncation_mask hook instead of performing modulo by
width. Compare against mode precision, not bitsize.
shift_truncation_mask hook instead of performing modulo by width.
Compare against mode precision, not bitsize.
* combine.c (combine_simplify_rtx, simplify_shift_const_1):
Use shift_truncation_mask instead of constructing the value
manually.
Use shift_truncation_mask instead of constructing the value manually.
2011-07-06 Michael Meissner <meissner@linux.vnet.ibm.com>
......@@ -830,10 +821,8 @@
(AIX_FUNC_DESC_TOC_64BIT): Ditto.
(AIX_FUNC_DESC_SC_32BIT): Ditto.
(AIX_FUNC_DESC_SC_64BIT): Ditto.
(ptrload): New mode attribute for the appropriate load of a
pointer.
(call_indirect_aix32): Delete, rewrite AIX indirect function
calls.
(ptrload): New mode attribute for the appropriate load of a pointer.
(call_indirect_aix32): Delete, rewrite AIX indirect function calls.
(call_indirect_aix64): Ditto.
(call_value_indirect_aix32): Ditto.
(call_value_indirect_aix64): Ditto.
......@@ -866,8 +855,7 @@
2011-07-06 James Greenhalgh <james.greenhalgh@arm.com>
* config/arm/arm.h (TARGET_CPU_CPP_BUILTINS): Add
__ARM_FEATURE_DSP.
* config/arm/arm.h (TARGET_CPU_CPP_BUILTINS): Add __ARM_FEATURE_DSP.
2011-07-06 Basile Starynkevitch <basile@starynkevitch.net>
......@@ -906,16 +894,14 @@
* simplify-rtx.c (mode_signbit_p): Use GET_MODE_PRECISION.
(val_mode_signbit_p, val_mode_signbit_set_p): New functions.
(simplify_const_unary_operation, simplify_binary_operation_1,
simplify_const_binary_operation,
simplify_const_relational_operation): Use them. Use
GET_MODE_MASK for masking and sign-extensions.
simplify_const_binary_operation, simplify_const_relational_operation):
Use them. Use GET_MODE_MASK for masking and sign-extensions.
* combine.c (set_nonzero_bits_and_sign_copies, simplify_set,
combine_simplify_rtx, force_to_mode, reg_nonzero_bits_for_combine,
simplify_shift_const_1, simplify_comparison): Likewise.
* expr.c (convert_modes): Likewise.
* rtlanal.c (nonzero_bits1, canonicalize_condition): Likewise.
* expmed.c (emit_cstore, emit_store_flag_1, emit_store_flag):
Likewise.
* expmed.c (emit_cstore, emit_store_flag_1, emit_store_flag): Likewise.
* rtl.h (val_mode_signbit_p, val_mode_signbit_set_p): Declare.
* simplify-rtx.c (simplify_ternary_operation): Remove dead code.
......@@ -940,11 +926,10 @@
2011-07-06 Bernd Schmidt <bernds@codesourcery.com>
* simplify-rtx.c (simplify_const_binary_operation): Use the
shift_truncation_mask hook instead of performing modulo by
width. Compare against mode precision, not bitsize.
shift_truncation_mask hook instead of performing modulo by width.
Compare against mode precision, not bitsize.
* combine.c (combine_simplify_rtx, simplify_shift_const_1):
Use shift_truncation_mask instead of constructing the value
manually.
Use shift_truncation_mask instead of constructing the value manually.
2011-07-06 H.J. Lu <hongjiu.lu@intel.com>
......@@ -1082,10 +1067,10 @@
2011-07-05 Razya Ladelsky <razya@il.ibm.com>
PR tree-optimization/49580
* tree-cfg.c (gimple_duplicate_sese_tail): Remove handling of
* tree-cfg.c (gimple_duplicate_sese_tail): Remove handling of
the loop's number of iterations.
* tree-parloops.c (transform_to_exit_first_loop): Add the
handling of the loop's number of iterations before the call
* tree-parloops.c (transform_to_exit_first_loop): Add the
handling of the loop's number of iterations before the call
to gimple_duplicate_sese_tail.
Insert the stmt caclculating the new rhs of the loop's
condition stmt to the preheader instead of iters_bb.
......@@ -1117,9 +1102,8 @@
* simplify-rtx.c (simplify_unary_operation_1) <case NEG>: When
negating MULT, negate the second operand instead of first.
(simplify_binary_operation_1) <case MULT>: If one operand is
a NEG and the other is MULT, don't attempt to optimize by
negation of the MULT operand if it only moves the NEG operation
around.
a NEG and the other is MULT, don't attempt to optimize by negation
of the MULT operand if it only moves the NEG operation around.
PR debug/49602
* tree-into-ssa.c (rewrite_debug_stmt_uses): Disregard
......
gcc/config/i386/i386.c
......@@ -22683,54 +22683,14 @@ static void
ix86_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value)
{
rtx mem, fnaddr;
int opcode;
int offset = 0;
fnaddr = XEXP (DECL_RTL (fndecl), 0);
if (!TARGET_64BIT)
{
rtx disp, chain;
int opcode;
/* Depending on the static chain location, either load a register
with a constant, or push the constant to the stack. All of the
instructions are the same size. */
chain = ix86_static_chain (fndecl, true);
if (REG_P (chain))
{
if (REGNO (chain) == CX_REG)
opcode = 0xb9;
else if (REGNO (chain) == AX_REG)
opcode = 0xb8;
else
gcc_unreachable ();
}
else
opcode = 0x68;
mem = adjust_address (m_tramp, QImode, 0);
emit_move_insn (mem, gen_int_mode (opcode, QImode));
mem = adjust_address (m_tramp, SImode, 1);
emit_move_insn (mem, chain_value);
/* Compute offset from the end of the jmp to the target function.
In the case in which the trampoline stores the static chain on
the stack, we need to skip the first insn which pushes the
(call-saved) register static chain; this push is 1 byte. */
disp = expand_binop (SImode, sub_optab, fnaddr,
plus_constant (XEXP (m_tramp, 0),
MEM_P (chain) ? 9 : 10),
NULL_RTX, 1, OPTAB_DIRECT);
mem = adjust_address (m_tramp, QImode, 5);
emit_move_insn (mem, gen_int_mode (0xe9, QImode));
mem = adjust_address (m_tramp, SImode, 6);
emit_move_insn (mem, disp);
}
else
if (TARGET_64BIT)
{
int offset = 0, size;
int size;
/* Load the function address to r11. Try to load address using
the shorter movl instead of movabs. We may want to support
......@@ -22757,20 +22717,22 @@ ix86_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value)
offset += 10;
}
/* Load static chain using movabs to r10. */
mem = adjust_address (m_tramp, HImode, offset);
/* Use the shorter movl instead of movabs for x32. */
/* Load static chain using movabs to r10. Use the
shorter movl instead of movabs for x32. */
if (TARGET_X32)
{
opcode = 0xba41;
size = 6;
emit_move_insn (mem, gen_int_mode (0xba41, HImode));
}
else
{
opcode = 0xba49;
size = 10;
emit_move_insn (mem, gen_int_mode (0xba49, HImode));
}
mem = adjust_address (m_tramp, HImode, offset);
emit_move_insn (mem, gen_int_mode (opcode, HImode));
mem = adjust_address (m_tramp, ptr_mode, offset + 2);
emit_move_insn (mem, chain_value);
offset += size;
......@@ -22780,10 +22742,56 @@ ix86_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value)
mem = adjust_address (m_tramp, SImode, offset);
emit_move_insn (mem, gen_int_mode (0x90e3ff49, SImode));
offset += 4;
}
else
{
rtx disp, chain;
/* Depending on the static chain location, either load a register
with a constant, or push the constant to the stack. All of the
instructions are the same size. */
chain = ix86_static_chain (fndecl, true);
if (REG_P (chain))
{
switch (REGNO (chain))
{
case AX_REG:
opcode = 0xb8; break;
case CX_REG:
opcode = 0xb9; break;
default:
gcc_unreachable ();
}
}
else
opcode = 0x68;
mem = adjust_address (m_tramp, QImode, offset);
emit_move_insn (mem, gen_int_mode (opcode, QImode));
mem = adjust_address (m_tramp, SImode, offset + 1);
emit_move_insn (mem, chain_value);
offset += 5;
mem = adjust_address (m_tramp, QImode, offset);
emit_move_insn (mem, gen_int_mode (0xe9, QImode));
mem = adjust_address (m_tramp, SImode, offset + 1);
gcc_assert (offset <= TRAMPOLINE_SIZE);
/* Compute offset from the end of the jmp to the target function.
In the case in which the trampoline stores the static chain on
the stack, we need to skip the first insn which pushes the
(call-saved) register static chain; this push is 1 byte. */
offset += 5;
disp = expand_binop (SImode, sub_optab, fnaddr,
plus_constant (XEXP (m_tramp, 0),
offset - (MEM_P (chain) ? 1 : 0)),
NULL_RTX, 1, OPTAB_DIRECT);
emit_move_insn (mem, disp);
}
gcc_assert (offset <= TRAMPOLINE_SIZE);
#ifdef HAVE_ENABLE_EXECUTE_STACK
#ifdef CHECK_EXECUTE_STACK_ENABLED
if (CHECK_EXECUTE_STACK_ENABLED)
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