ia64.c (TARGET_VECTOR_MODE_SUPPORTED_P): New.

        * config/ia64/ia64.c (TARGET_VECTOR_MODE_SUPPORTED_P): New.
        (ia64_const_ok_for_letter_p): New.
        (ia64_const_double_ok_for_letter_p): New.
        (ia64_extra_constraint): New.
        (ia64_expand_vecint_compare): New.
        (ia64_expand_vcondu_v2si): New.
        (ia64_expand_vecint_cmov): New.
        (ia64_expand_vecint_minmax): New.
        (ia64_print_operand): Add 'v'.
        (ia64_preferred_reload_class): New.
        (ia64_vector_mode_supported_p): New.
        * config/ia64/ia64.h (UNITS_PER_SIMD_WORD): New.
        (PREFERRED_RELOAD_CLASS): Move to function.
        (CONST_OK_FOR_LETTER_P): Move to function.
        (CONST_DOUBLE_OK_FOR_LETTER_P): Move to function.
        (CONSTRAINT_OK_FOR_Q, CONSTRAINT_OK_FOR_R): Remove.
        (CONSTRAINT_OK_FOR_S, CONSTRAINT_OK_FOR_T): Remove.
        (EXTRA_CONSTRAINT): Move to function.
        * config/ia64/ia64.md: Include vect.md.
        (itanium_class): Add mmalua.
        (type): Handle it.
        * config/ia64/itanium1.md (1_mmalua): New.  Add it to bypasses.
        (1b_mmalua): New.
        * config/ia64/itanium2.md (2_mmalua, 2b_mmalua): Similarly.
        * config/ia64/predicates.md (gr_reg_or_0_operand): Accept any
        CONST0_RTX.
        (const_int_2bit_operand): New.
        (fr_reg_or_0_operand): New.
        * config/ia64/ia64-modes.def: Add vector modes.
        * config/ia64/ia64-protos.h: Update.
        * config/ia64/vect.md: New file.

        * gcc.dg/vect/vect.exp: Enable for ia64.
        * lib/target-supports.exp (check_effective_target_vect_int): Likewise.
        (check_effective_target_vect_float): Likewise.
        (check_effective_target_vect_no_align): Likewise.
        * gcc.dg/vect/vect-30.c: XFAIL for vect_no_align.
        * gcc.dg/vect/vect-8.c: Likewise.

From-SVN: r92862

gcc/ChangeLog

 2005-01-03  Richard Henderson  <rth@redhat.com>
 
+	* config/ia64/ia64.c (TARGET_VECTOR_MODE_SUPPORTED_P): New.
+	(ia64_const_ok_for_letter_p): New.
+	(ia64_const_double_ok_for_letter_p): New.
+	(ia64_extra_constraint): New.
+	(ia64_expand_vecint_compare): New.
+	(ia64_expand_vcondu_v2si): New.
+	(ia64_expand_vecint_cmov): New.
+	(ia64_expand_vecint_minmax): New.
+	(ia64_print_operand): Add 'v'.
+	(ia64_preferred_reload_class): New.
+	(ia64_vector_mode_supported_p): New.
+	* config/ia64/ia64.h (UNITS_PER_SIMD_WORD): New.
+	(PREFERRED_RELOAD_CLASS): Move to function.
+	(CONST_OK_FOR_LETTER_P): Move to function.
+	(CONST_DOUBLE_OK_FOR_LETTER_P): Move to function.
+	(CONSTRAINT_OK_FOR_Q, CONSTRAINT_OK_FOR_R): Remove.
+	(CONSTRAINT_OK_FOR_S, CONSTRAINT_OK_FOR_T): Remove.
+	(EXTRA_CONSTRAINT): Move to function.
+	* config/ia64/ia64.md: Include vect.md.
+	(itanium_class): Add mmalua.
+	(type): Handle it.
+	* config/ia64/itanium1.md (1_mmalua): New.  Add it to bypasses.
+	(1b_mmalua): New.
+	* config/ia64/itanium2.md (2_mmalua, 2b_mmalua): Similarly.
+	* config/ia64/predicates.md (gr_reg_or_0_operand): Accept any
+	CONST0_RTX.
+	(const_int_2bit_operand): New.
+	(fr_reg_or_0_operand): New.
+	* config/ia64/ia64-modes.def: Add vector modes.
+	* config/ia64/ia64-protos.h: Update.
+	* config/ia64/vect.md: New file.
+
+2005-01-03  Richard Henderson  <rth@redhat.com>
+
 	* simplify-rtx.c (simplify_binary_operation): Handle VEC_CONCAT.
 
 2005-01-03  Uros Bizjak  <uros@kss-loka.si>

gcc/config/ia64/ia64-modes.def

@@ -66,3 +66,11 @@ INT_MODE (OI, 32);
    so that flow doesn't do something stupid.  */
 
 CC_MODE (CCI);
+
+/* Vector modes.  */
+VECTOR_MODES (INT, 4);		/* V4QI V2HI */
+VECTOR_MODES (INT, 8);		/* V8QI V4HI V2SI */
+VECTOR_MODE (INT, QI, 16);
+VECTOR_MODE (INT, HI, 8);
+VECTOR_MODE (INT, SI, 4);
+VECTOR_MODE (FLOAT, SF, 2);

gcc/config/ia64/ia64-protos.h

@@ -34,6 +34,10 @@ extern int ia64_st_address_bypass_p (rtx, rtx);
 extern int ia64_ld_address_bypass_p (rtx, rtx);
 extern int ia64_produce_address_p (rtx);
 
+extern bool ia64_const_ok_for_letter_p (HOST_WIDE_INT, char);
+extern bool ia64_const_double_ok_for_letter_p (rtx, char);
+extern bool ia64_extra_constraint (rtx, char);
+
 extern rtx ia64_expand_move (rtx, rtx);
 extern int ia64_move_ok (rtx, rtx);
 extern int addp4_optimize_ok (rtx, rtx);
@@ -42,6 +46,8 @@ extern int ia64_depz_field_mask (rtx, rtx);
 extern void ia64_split_tmode_move (rtx[]);
 extern rtx spill_xfmode_operand (rtx, int);
 extern rtx ia64_expand_compare (enum rtx_code, enum machine_mode);
+extern void ia64_expand_vecint_cmov (rtx[]);
+extern bool ia64_expand_vecint_minmax (enum rtx_code, enum machine_mode, rtx[]);
 extern void ia64_expand_call (rtx, rtx, rtx, int);
 extern void ia64_split_call (rtx, rtx, rtx, rtx, rtx, int, int);
 extern void ia64_reload_gp (void);
@@ -57,6 +63,7 @@ extern int ia64_hard_regno_rename_ok (int, int);
 extern void ia64_initialize_trampoline (rtx, rtx, rtx);
 extern void ia64_print_operand_address (FILE *, rtx);
 extern void ia64_print_operand (FILE *, rtx, int);
+extern enum reg_class ia64_preferred_reload_class (rtx, enum reg_class);
 extern enum reg_class ia64_secondary_reload_class (enum reg_class,
 						   enum machine_mode, rtx);
 extern void ia64_output_dwarf_dtprel (FILE*, int, rtx);

gcc/config/ia64/ia64.h

@@ -338,6 +338,8 @@ extern const char *ia64_tune_string;
 
 #define UNITS_PER_WORD 8
 
+#define UNITS_PER_SIMD_WORD UNITS_PER_WORD
+
 #define POINTER_SIZE (TARGET_ILP32 ? 32 : 64)
 
 /* A C expression whose value is zero if pointers that need to be extended
@@ -1024,18 +1026,8 @@ enum reg_class
    The value is a register class; perhaps CLASS, or perhaps another, smaller
    class.  */
 
-/* Don't allow volatile mem reloads into floating point registers.  This
-   is defined to force reload to choose the r/m case instead of the f/f case
-   when reloading (set (reg fX) (mem/v)).
-
-   Do not reload expressions into AR regs.  */
-
 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
-  (CLASS == FR_REGS && GET_CODE (X) == MEM && MEM_VOLATILE_P (X) ? NO_REGS   \
-   : CLASS == FR_REGS && GET_CODE (X) == CONST_DOUBLE ? NO_REGS		     \
-   : !OBJECT_P (X)							     \
-     && (CLASS == AR_M_REGS || CLASS == AR_I_REGS) ? NO_REGS		     \
-   : CLASS)
+  ia64_preferred_reload_class (X, CLASS)
 
 /* You should define this macro to indicate to the reload phase that it may
    need to allocate at least one register for a reload in addition to the
@@ -1106,15 +1098,7 @@ enum reg_class
 #define CONST_OK_FOR_P(VALUE) ((VALUE) == 0 || (VALUE) == -1)
 
 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
-((C) == 'I' ? CONST_OK_FOR_I (VALUE)		\
- : (C) == 'J' ? CONST_OK_FOR_J (VALUE)		\
- : (C) == 'K' ? CONST_OK_FOR_K (VALUE)		\
- : (C) == 'L' ? CONST_OK_FOR_L (VALUE)		\
- : (C) == 'M' ? CONST_OK_FOR_M (VALUE)		\
- : (C) == 'N' ? CONST_OK_FOR_N (VALUE)		\
- : (C) == 'O' ? CONST_OK_FOR_O (VALUE)		\
- : (C) == 'P' ? CONST_OK_FOR_P (VALUE)		\
- : 0)
+  ia64_const_ok_for_letter_p (VALUE, C)
 
 /* A C expression that defines the machine-dependent operand constraint letters
    (`G', `H') that specify particular ranges of `const_double' values.  */
@@ -1125,33 +1109,14 @@ enum reg_class
    || (VALUE) == CONST1_RTX (GET_MODE (VALUE)))
 
 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
-  ((C) == 'G' ? CONST_DOUBLE_OK_FOR_G (VALUE) : 0)
+  ia64_const_double_ok_for_letter_p (VALUE, C)
 
 /* A C expression that defines the optional machine-dependent constraint
    letters (`Q', `R', `S', `T', `U') that can be used to segregate specific
    types of operands, usually memory references, for the target machine.  */
 
-/* Non-volatile memory for FP_REG loads/stores.  */
-#define CONSTRAINT_OK_FOR_Q(VALUE) \
-  (memory_operand((VALUE), VOIDmode) && ! MEM_VOLATILE_P (VALUE))
-/* 1..4 for shladd arguments.  */
-#define CONSTRAINT_OK_FOR_R(VALUE) \
-  (GET_CODE (VALUE) == CONST_INT && INTVAL (VALUE) >= 1 && INTVAL (VALUE) <= 4)
-/* Non-post-inc memory for asms and other unsavory creatures.  */
-#define CONSTRAINT_OK_FOR_S(VALUE)					\
-  (GET_CODE (VALUE) == MEM						\
-   && GET_RTX_CLASS (GET_CODE (XEXP ((VALUE), 0))) != RTX_AUTOINC	\
-   && (reload_in_progress || memory_operand ((VALUE), VOIDmode)))
-/* Symbol ref to small-address-area: */
-#define CONSTRAINT_OK_FOR_T(VALUE)						\
-	(GET_CODE (VALUE) == SYMBOL_REF && SYMBOL_REF_SMALL_ADDR_P (VALUE))
-
 #define EXTRA_CONSTRAINT(VALUE, C) \
-  ((C) == 'Q' ? CONSTRAINT_OK_FOR_Q (VALUE)	\
-   : (C) == 'R' ? CONSTRAINT_OK_FOR_R (VALUE)	\
-   : (C) == 'S' ? CONSTRAINT_OK_FOR_S (VALUE)	\
-   : (C) == 'T' ? CONSTRAINT_OK_FOR_T (VALUE)	\
-   : 0)
+  ia64_extra_constraint (VALUE, C)
 
 /* Basic Stack Layout */
 

gcc/config/ia64/ia64.md

@@ -121,9 +121,9 @@
 
 (define_attr "itanium_class" "unknown,ignore,stop_bit,br,fcmp,fcvtfx,fld,
 	fmac,fmisc,frar_i,frar_m,frbr,frfr,frpr,ialu,icmp,ilog,ishf,ld,
-	chk_s,long_i,mmmul,mmshf,mmshfi,rse_m,scall,sem,stf,st,syst_m0,
-	syst_m,tbit,toar_i,toar_m,tobr,tofr,topr,xmpy,xtd,nop,nop_b,nop_f,
-	nop_i,nop_m,nop_x,lfetch,pre_cycle"
+	chk_s,long_i,mmalua,mmmul,mmshf,mmshfi,rse_m,scall,sem,stf,
+        st,syst_m0, syst_m,tbit,toar_i,toar_m,tobr,tofr,topr,xmpy,xtd,nop,
+        nop_b,nop_f,nop_i,nop_m,nop_x,lfetch,pre_cycle"
   (const_string "unknown"))
 
 ;; chk_s has an I and an M form; use type A for convenience.
@@ -132,7 +132,8 @@
 	 (eq_attr "itanium_class" "rse_m,syst_m,syst_m0") (const_string "M")
 	 (eq_attr "itanium_class" "frar_m,toar_m,frfr,tofr") (const_string "M")
 	 (eq_attr "itanium_class" "lfetch") (const_string "M")
-	 (eq_attr "itanium_class" "chk_s,ialu,icmp,ilog") (const_string "A")
+	 (eq_attr "itanium_class" "chk_s,ialu,icmp,ilog,mmalua")
+	   (const_string "A")
 	 (eq_attr "itanium_class" "fmisc,fmac,fcmp,xmpy") (const_string "F")
 	 (eq_attr "itanium_class" "fcvtfx,nop_f") (const_string "F")
 	 (eq_attr "itanium_class" "frar_i,toar_i,frbr,tobr") (const_string "I")
@@ -6036,3 +6037,6 @@
   "addp4_optimize_ok (operands[1], operands[2])"
   "addp4 %0 = %1, %2"
   [(set_attr "itanium_class" "ialu")])
+
+;; Vector operations
+(include "vect.md")

gcc/config/ia64/itanium1.md

@@ -589,6 +589,11 @@
   (and (and (eq_attr "cpu" "itanium")
             (eq_attr "itanium_class" "ilog"))
        (eq (symbol_ref "bundling_p") (const_int 0))) "1_A")
+(define_insn_reservation "1_mmalua" 2
+    (and (and (eq_attr "cpu" "itanium")
+              (eq_attr "itanium_class" "mmalua"))
+         (eq (symbol_ref "bundling_p") (const_int 0)))
+    "1_A")
 (define_insn_reservation "1_ishf"    1
   (and (and (eq_attr "cpu" "itanium")
             (eq_attr "itanium_class" "ishf"))
@@ -920,7 +925,7 @@
 ;; There is only one insn `mov ar.pfs =' for toar_i.
 (define_bypass  0 "1_tobr,1_topr,1_toar_i" "1_br,1_scall")
 
-(define_bypass  3 "1_ialu,1_ialu_addr" "1_mmmul,1_mmshf")
+(define_bypass  3 "1_ialu,1_ialu_addr" "1_mmmul,1_mmshf,1_mmalua")
 ;; ??? howto describe ialu for I slot only.  We use ialu_addr for that
 ;;(define_bypass  2 "1_ialu" "1_ld"  "ia64_ld_address_bypass_p")
 ;; ??? howto describe ialu st/address for I slot only.  We use ialu_addr
@@ -940,7 +945,7 @@
 
 ;; Intel docs say only LD, ST, IALU, ILOG, ISHF consumers have latency 4,
 ;;      but HP engineers say any non-MM operation.
-(define_bypass  4 "1_mmmul,1_mmshf"
+(define_bypass  4 "1_mmmul,1_mmshf,1_mmalua"
      "1_br,1_fcmp,1_fcvtfx,1_fld,1_fmac,1_fmisc,1_frar_i,1_frar_m,\
       1_frbr,1_frfr,1_frpr,1_ialu,1_icmp,1_ilog,1_ishf,1_ld,1_chk_s,\
       1_long_i,1_rse_m,1_sem,1_stf,1_st,1_syst_m0,1_syst_m,\
@@ -958,13 +963,13 @@
 ;; We don't use here fcmp because scall may be predicated.
 (define_bypass  0 "1_fcvtfx,1_fld,1_fmac,1_fmisc,1_frar_i,1_frar_m,\
                    1_frbr,1_frfr,1_frpr,1_ialu,1_ialu_addr,1_ilog,1_ishf,\
-	           1_ld,1_long_i,1_mmmul,1_mmshf,1_mmshfi,1_toar_m,1_tofr,\
-                   1_xmpy,1_xtd" "1_scall")
+	           1_ld,1_long_i,2_mmalua,1_mmmul,1_mmshf,1_mmshfi,1_toar_m,\
+		   1_tofr,1_xmpy,1_xtd" "1_scall")
 
 (define_bypass  0 "1_unknown,1_ignore,1_stop_bit,1_br,1_fcmp,1_fcvtfx,\
                    1_fld,1_fmac,1_fmisc,1_frar_i,1_frar_m,1_frbr,1_frfr,\
                    1_frpr,1_ialu,1_ialu_addr,1_icmp,1_ilog,1_ishf,1_ld,\
-                   1_chk_s,1_long_i,1_mmmul,1_mmshf,1_mmshfi,1_nop,\
+                   1_chk_s,1_long_i,1_mmalua,1_mmmul,1_mmshf,1_mmshfi,1_nop,\
                    1_nop_b,1_nop_f,1_nop_i,1_nop_m,1_nop_x,1_rse_m,1_scall,\
                    1_sem,1_stf,1_st,1_syst_m0,1_syst_m,1_tbit,1_toar_i,\
                    1_toar_m,1_tobr,1_tofr,1_topr,1_xmpy,1_xtd,1_lfetch"
@@ -1458,6 +1463,10 @@
   (and (and (eq_attr "cpu" "itanium")
             (eq_attr "itanium_class" "ilog"))
        (ne (symbol_ref "bundling_p") (const_int 0))) "1b_A")
+(define_insn_reservation "1b_mmalua"  2
+  (and (and (eq_attr "cpu" "itanium")
+            (eq_attr "itanium_class" "mmalua"))
+       (ne (symbol_ref "bundling_p") (const_int 0))) "1b_A")
 (define_insn_reservation "1b_ishf"    1
   (and (and (eq_attr "cpu" "itanium")
             (eq_attr "itanium_class" "ishf"))

gcc/config/ia64/itanium2.md

@@ -786,6 +786,10 @@
   (and (and (eq_attr "cpu" "itanium2")
             (eq_attr "itanium_class" "ilog"))
        (eq (symbol_ref "bundling_p") (const_int 0))) "2_A")
+(define_insn_reservation "2_mmalua"  2
+  (and (and (eq_attr "cpu" "itanium2")
+            (eq_attr "itanium_class" "mmalua"))
+       (eq (symbol_ref "bundling_p") (const_int 0))) "2_A")
 ;; Latency time ???
 (define_insn_reservation "2_ishf"    1
   (and (and (eq_attr "cpu" "itanium2")
@@ -1016,23 +1020,24 @@
 (define_bypass  0 "2_tbit" "2_br,2_scall")
 (define_bypass  2 "2_ld" "2_ld"  "ia64_ld_address_bypass_p")
 (define_bypass  2 "2_ld" "2_st"  "ia64_st_address_bypass_p")
-(define_bypass  2 "2_ld" "2_mmmul,2_mmshf")
-(define_bypass  3 "2_ilog" "2_mmmul,2_mmshf")
-(define_bypass  3 "2_ialu" "2_mmmul,2_mmshf")
-(define_bypass  3 "2_mmmul,2_mmshf" "2_ialu,2_ilog,2_ishf,2_st,2_ld")
+(define_bypass  2 "2_ld" "2_mmalua,2_mmmul,2_mmshf")
+(define_bypass  3 "2_ilog" "2_mmalua,2_mmmul,2_mmshf")
+(define_bypass  3 "2_ialu" "2_mmalua,2_mmmul,2_mmshf")
+(define_bypass  3 "2_mmalua,2_mmmul,2_mmshf" "2_ialu,2_ilog,2_ishf,2_st,2_ld")
 (define_bypass  6 "2_tofr"  "2_frfr,2_stf")
 (define_bypass  7 "2_fmac"  "2_frfr,2_stf")
 
 ;; We don't use here fcmp because scall may be predicated.
 (define_bypass  0 "2_fcvtfx,2_fld,2_fmac,2_fmisc,2_frar_i,2_frar_m,\
                    2_frbr,2_frfr,2_frpr,2_ialu,2_ilog,2_ishf,2_ld,2_long_i,\
-                   2_mmmul,2_mmshf,2_mmshfi,2_toar_m,2_tofr,2_xmpy,2_xtd"
+                   2_mmalua,2_mmmul,2_mmshf,2_mmshfi,2_toar_m,2_tofr,\
+		   2_xmpy,2_xtd"
                   "2_scall")
 
 (define_bypass  0 "2_unknown,2_ignore,2_stop_bit,2_br,2_fcmp,2_fcvtfx,2_fld,\
                    2_fmac,2_fmisc,2_frar_i,2_frar_m,2_frbr,2_frfr,2_frpr,\
-                   2_ialu,2_icmp,2_ilog,2_ishf,2_ld,2_chk_s,\
-                   2_long_i,2_mmmul,2_mmshf,2_mmshfi,2_nop,2_nop_b,2_nop_f,\
+                   2_ialu,2_icmp,2_ilog,2_ishf,2_ld,2_chk_s,2_long_i,\
+		   2_mmalua,2_mmmul,2_mmshf,2_mmshfi,2_nop,2_nop_b,2_nop_f,\
                    2_nop_i,2_nop_m,2_nop_x,2_rse_m,2_scall,2_sem,2_stf,2_st,\
                    2_syst_m0,2_syst_m,2_tbit,2_toar_i,2_toar_m,2_tobr,2_tofr,\
                    2_topr,2_xmpy,2_xtd,2_lfetch" "2_ignore")
@@ -1586,6 +1591,10 @@
   (and (and (eq_attr "cpu" "itanium2")
             (eq_attr "itanium_class" "ilog"))
        (ne (symbol_ref "bundling_p") (const_int 0))) "2b_A")
+(define_insn_reservation "2b_mmalua"  2
+  (and (and (eq_attr "cpu" "itanium2")
+            (eq_attr "itanium_class" "mmalua"))
+       (ne (symbol_ref "bundling_p") (const_int 0))) "2b_A")
 ;; Latency time ???
 (define_insn_reservation "2b_ishf"    1
   (and (and (eq_attr "cpu" "itanium2")

gcc/config/ia64/predicates.md

@@ -236,8 +236,8 @@
 ;; True if OP is a GR register operand, or zero.
 (define_predicate "gr_reg_or_0_operand"
   (ior (match_operand 0 "gr_register_operand")
-       (and (match_code "const_int")
-	    (match_test "op == const0_rtx"))))
+       (and (match_code "const_int,const_double,const_vector")
+	    (match_test "op == CONST0_RTX (GET_MODE (op))"))))
 
 ;; True if OP is a GR register operand, or a 5 bit immediate operand.
 (define_predicate "gr_reg_or_5bit_operand"
@@ -320,6 +320,10 @@
                     INTVAL (op) == 1   || INTVAL (op) == 4  ||
                     INTVAL (op) == 8   || INTVAL (op) == 16")))
 
+;; True if OP is 0..3.
+(define_predicate "const_int_2bit_operand"
+  (and (match_code "const_int")
+        (match_test "INTVAL (op) >= 0 && INTVAL (op) <= 3")))
 
 ;; True if OP is a floating-point constant zero, one, or a register.
 (define_predicate "fr_reg_or_fp01_operand"
@@ -332,6 +336,12 @@
   (and (match_operand 0 "fr_reg_or_fp01_operand")
        (not (match_code "subreg"))))
 
+;; True if OP is a constant zero, or a register.
+(define_predicate "fr_reg_or_0_operand"
+  (ior (match_operand 0 "fr_register_operand")
+       (and (match_code "const_double,const_vector")
+	    (match_test "op == CONST0_RTX (GET_MODE (op))"))))
+
 ;; True if this is a comparison operator, which accepts a normal 8-bit
 ;; signed immediate operand.
 (define_predicate "normal_comparison_operator"

gcc/testsuite/ChangeLog

+2005-01-03  Richard Henderson  <rth@redhat.com>
+
+	* gcc.dg/vect/vect.exp: Enable for ia64.
+	* lib/target-supports.exp (check_effective_target_vect_int): Likewise.
+	(check_effective_target_vect_float): Likewise.
+	(check_effective_target_vect_no_align): Likewise.
+	* gcc.dg/vect/vect-30.c: XFAIL for vect_no_align.
+	* gcc.dg/vect/vect-8.c: Likewise.
+
 2005-01-03  Uros Bizjak <uros@kss-loka.si>
+
 	PR target/19235
 	* gcc.dg/pr19236-1.c: New test case.
 

gcc/testsuite/gcc.dg/vect/vect-30.c

@@ -59,4 +59,6 @@ int main (void)
   return 0;
 }
 
-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 2 "vect"  } } */
+/* Need misalignment support, or cgraph to delay emitting the arrays until
+   after vectorization can force-align them.  */
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 2 "vect" { xfail vect_no_align } } } */

gcc/testsuite/gcc.dg/vect/vect-8.c

@@ -34,4 +34,6 @@ int main (void)
   return main1 (N);
 }
 
-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect"  } } */
+/* Need misalignment support, or cgraph to delay emitting the arrays until
+   after vectorization can force-align them.  */
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { xfail vect_no_align } } } */

gcc/testsuite/gcc.dg/vect/vect.exp

@@ -65,6 +65,8 @@ if [istarget "powerpc*-*-*"] {
     } else {
 	set dg-do-what-default compile
     }
+} elseif [istarget "ia64-*-*"] {
+    set dg-do-what-default run
 } else {
     return
 }

gcc/testsuite/lib/target-supports.exp

@@ -455,7 +455,8 @@ proc check_effective_target_vect_int { } {
 	      || [istarget powerpc*-*-*]
 	      || [istarget x86_64-*-*]
 	      || [istarget sparc*-*-*]
-	      || [istarget alpha*-*-*] } {
+	      || [istarget alpha*-*-*]
+	      || [istarget ia64-*-*] } {
 	   set et_vect_int_saved 1
 	}
     }
@@ -496,7 +497,8 @@ proc check_effective_target_vect_float { } {
 	if { [istarget i?86-*-*]
 	      || [istarget powerpc*-*-*]
 	      || [istarget mipsisa64*-*-*]
-	      || [istarget x86_64-*-*] } {
+	      || [istarget x86_64-*-*]
+	      || [istarget ia64-*-*] } {
 	   set et_vect_float_saved 1
 	}
     }
@@ -583,7 +585,8 @@ proc check_effective_target_vect_no_align { } {
     } else {
 	set et_vect_no_align_saved 0
 	if { [istarget mipsisa64*-*-*]
-	     || [istarget sparc*-*-*] } {
+	     || [istarget sparc*-*-*]
+	     || [istarget ia64-*-*] } {
 	    set et_vect_no_align_saved 1
 	}
     }