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lvzhengyang
riscv-gcc-1
Commits
3198b947
Commit
3198b947
authored
Jan 03, 2005
by
Richard Henderson
Committed by
Richard Henderson
Jan 03, 2005
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* simplify-rtx.c (simplify_binary_operation): Handle VEC_CONCAT.
From-SVN: r92861
parent
cde7853d
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gcc/ChangeLog
+4
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gcc/simplify-rtx.c
+38
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gcc/ChangeLog
View file @
3198b947
2005-01-03 Richard Henderson <rth@redhat.com>
* simplify-rtx.c (simplify_binary_operation): Handle VEC_CONCAT.
2005-01-03 Uros Bizjak <uros@kss-loka.si>
2005-01-03 Uros Bizjak <uros@kss-loka.si>
PR target/19236
PR target/19236
...
@@ -5,7 +9,6 @@
...
@@ -5,7 +9,6 @@
to SFmode.
to SFmode.
(log1pdf2): Change mode of operands[0,1] to DFmode.
(log1pdf2): Change mode of operands[0,1] to DFmode.
2005-01-03 Eric Botcazou <ebotcazou@libertysurf.fr>
2005-01-03 Eric Botcazou <ebotcazou@libertysurf.fr>
* config/sparc/sparc.h (SPARC_RELAXED_ORDERING): Define to false.
* config/sparc/sparc.h (SPARC_RELAXED_ORDERING): Define to false.
...
...
gcc/simplify-rtx.c
View file @
3198b947
...
@@ -1190,14 +1190,11 @@ simplify_binary_operation (enum rtx_code code, enum machine_mode mode,
...
@@ -1190,14 +1190,11 @@ simplify_binary_operation (enum rtx_code code, enum machine_mode mode,
&&
GET_CODE
(
trueop0
)
==
CONST_VECTOR
&&
GET_CODE
(
trueop0
)
==
CONST_VECTOR
&&
GET_CODE
(
trueop1
)
==
CONST_VECTOR
)
&&
GET_CODE
(
trueop1
)
==
CONST_VECTOR
)
{
{
int
elt_size
=
GET_MODE_SIZE
(
GET_MODE_INNER
(
mode
));
unsigned
n_elts
=
GET_MODE_NUNITS
(
mode
);
unsigned
n_elts
=
(
GET_MODE_SIZE
(
mode
)
/
elt_size
);
enum
machine_mode
op0mode
=
GET_MODE
(
trueop0
);
enum
machine_mode
op0mode
=
GET_MODE
(
trueop0
);
int
op0_elt_size
=
GET_MODE_SIZE
(
GET_MODE_INNER
(
op0mode
));
unsigned
op0_n_elts
=
GET_MODE_NUNITS
(
op0mode
);
unsigned
op0_n_elts
=
(
GET_MODE_SIZE
(
op0mode
)
/
op0_elt_size
);
enum
machine_mode
op1mode
=
GET_MODE
(
trueop1
);
enum
machine_mode
op1mode
=
GET_MODE
(
trueop1
);
int
op1_elt_size
=
GET_MODE_SIZE
(
GET_MODE_INNER
(
op1mode
));
unsigned
op1_n_elts
=
GET_MODE_NUNITS
(
op1mode
);
unsigned
op1_n_elts
=
(
GET_MODE_SIZE
(
op1mode
)
/
op1_elt_size
);
rtvec
v
=
rtvec_alloc
(
n_elts
);
rtvec
v
=
rtvec_alloc
(
n_elts
);
unsigned
int
i
;
unsigned
int
i
;
...
@@ -1216,6 +1213,41 @@ simplify_binary_operation (enum rtx_code code, enum machine_mode mode,
...
@@ -1216,6 +1213,41 @@ simplify_binary_operation (enum rtx_code code, enum machine_mode mode,
return
gen_rtx_CONST_VECTOR
(
mode
,
v
);
return
gen_rtx_CONST_VECTOR
(
mode
,
v
);
}
}
if
(
VECTOR_MODE_P
(
mode
)
&&
code
==
VEC_CONCAT
&&
CONSTANT_P
(
trueop0
)
&&
CONSTANT_P
(
trueop1
))
{
unsigned
n_elts
=
GET_MODE_NUNITS
(
mode
);
rtvec
v
=
rtvec_alloc
(
n_elts
);
gcc_assert
(
n_elts
>=
2
);
if
(
n_elts
==
2
)
{
gcc_assert
(
GET_CODE
(
trueop0
)
!=
CONST_VECTOR
);
gcc_assert
(
GET_CODE
(
trueop1
)
!=
CONST_VECTOR
);
RTVEC_ELT
(
v
,
0
)
=
trueop0
;
RTVEC_ELT
(
v
,
1
)
=
trueop1
;
}
else
{
unsigned
op0_n_elts
=
GET_MODE_NUNITS
(
GET_MODE
(
trueop0
));
unsigned
op1_n_elts
=
GET_MODE_NUNITS
(
GET_MODE
(
trueop1
));
unsigned
i
;
gcc_assert
(
GET_CODE
(
trueop0
)
==
CONST_VECTOR
);
gcc_assert
(
GET_CODE
(
trueop1
)
==
CONST_VECTOR
);
gcc_assert
(
op0_n_elts
+
op1_n_elts
==
n_elts
);
for
(
i
=
0
;
i
<
op0_n_elts
;
++
i
)
RTVEC_ELT
(
v
,
i
)
=
XVECEXP
(
trueop0
,
0
,
i
);
for
(
i
=
0
;
i
<
op1_n_elts
;
++
i
)
RTVEC_ELT
(
v
,
op0_n_elts
+
i
)
=
XVECEXP
(
trueop1
,
0
,
i
);
}
return
gen_rtx_CONST_VECTOR
(
mode
,
v
);
}
if
(
GET_MODE_CLASS
(
mode
)
==
MODE_FLOAT
if
(
GET_MODE_CLASS
(
mode
)
==
MODE_FLOAT
&&
GET_CODE
(
trueop0
)
==
CONST_DOUBLE
&&
GET_CODE
(
trueop0
)
==
CONST_DOUBLE
&&
GET_CODE
(
trueop1
)
==
CONST_DOUBLE
&&
GET_CODE
(
trueop1
)
==
CONST_DOUBLE
...
...
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