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riscv-gcc-1
Commit ef57f7d6 by Palmer Dabbelt Committed by Palmer Dabbelt
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RISC-V Port: Regenerate gcc/configure 

From-SVN: r245225
parent 09cae750
Showing with 14 additions and 2 deletions
gcc/ChangeLog
...@@ -31,6 +31,7 @@ ...@@ -31,6 +31,7 @@
* doc/install.texi: Add RISC-V entries. * doc/install.texi: Add RISC-V entries.
* doc/invoke.texi: Add RISC-V options section. * doc/invoke.texi: Add RISC-V options section.
* doc/md.texi: Add RISC-V constraints section. * doc/md.texi: Add RISC-V constraints section.
* configure: Regenerated.
2017-02-06 Michael Meissner <meissner@linux.vnet.ibm.com> 2017-02-06 Michael Meissner <meissner@linux.vnet.ibm.com>
......
gcc/configure
...@@ -24156,6 +24156,17 @@ x3: .space 4 ...@@ -24156,6 +24156,17 @@ x3: .space 4
tls_first_minor=14 tls_first_minor=14
tls_as_opt="-a32 --fatal-warnings" tls_as_opt="-a32 --fatal-warnings"
;; ;;
riscv*-*-*)
conftest_s='
.section .tdata,"awT",@progbits
x: .word 2
.text
la.tls.gd a0,x
call __tls_get_addr'
tls_first_major=2
tls_first_minor=21
tls_as_opt='--fatal-warnings'
;;
s390-*-*) s390-*-*)
conftest_s=' conftest_s='
.section ".tdata","awT",@progbits .section ".tdata","awT",@progbits
...@@ -27516,8 +27527,8 @@ esac ...@@ -27516,8 +27527,8 @@ esac
# version to the per-target configury. # version to the per-target configury.
case "$cpu_type" in case "$cpu_type" in
aarch64 | alpha | arm | avr | bfin | cris | i386 | m32c | m68k | microblaze \ aarch64 | alpha | arm | avr | bfin | cris | i386 | m32c | m68k | microblaze \
| mips | nios2 | pa | rs6000 | score | sparc | spu | tilegx | tilepro \ | mips | nios2 | pa | riscv | rs6000 | score | sparc | spu | tilegx \
| visium | xstormy16 | xtensa) | tilepro | visium | xstormy16 | xtensa)
insn="nop" insn="nop"
;; ;;
ia64 | s390) ia64 | s390)
......
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