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Commit 09cae750 by Palmer Dabbelt Committed by Palmer Dabbelt
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RISC-V Port: gcc 

gcc/ChangeLog:

2017-02-06  Palmer Dabbelt  <palmer@dabbelt.com>

        * config/riscv/riscv.c: New file.
        * gcc/common/config/riscv/riscv-common.c: Likewise.
        * config.gcc: Likewise.
        * config/riscv/constraints.md: Likewise.
        * config/riscv/elf.h: Likewise.
        * config/riscv/generic.md: Likewise.
        * config/riscv/linux.h: Likewise.
        * config/riscv/multilib-generator: Likewise.
        * config/riscv/peephole.md: Likewise.
        * config/riscv/pic.md: Likewise.
        * config/riscv/predicates.md: Likewise.
        * config/riscv/riscv-builtins.c: Likewise.
        * config/riscv/riscv-c.c: Likewise.
        * config/riscv/riscv-ftypes.def: Likewise.
        * config/riscv/riscv-modes.def: Likewise.
        * config/riscv/riscv-opts.h: Likewise.
        * config/riscv/riscv-protos.h: Likewise.
        * config/riscv/riscv.h: Likewise.
        * config/riscv/riscv.md: Likewise.
        * config/riscv/riscv.opt: Likewise.
        * config/riscv/sync.md: Likewise.
        * config/riscv/t-elf-multilib: Likewise.
        * config/riscv/t-linux: Likewise.
        * config/riscv/t-linux-multilib: Likewise.
        * config/riscv/t-riscv: Likewise.
        * configure.ac: Likewise.
        * doc/contrib.texi: Add Kito Cheng, Palmer Dabbelt, and Andrew
        Waterman as RISC-V maintainers.
        * doc/install.texi: Add RISC-V entries.
        * doc/invoke.texi: Add RISC-V options section.
        * doc/md.texi: Add RISC-V constraints section.

From-SVN: r245224
parent 44a6da7b
Showing with 1968 additions and 2 deletions
gcc/ChangeLog
2017-02-06 Palmer Dabbelt <palmer@dabbelt.com>
* config/riscv/riscv.c: New file.
* gcc/common/config/riscv/riscv-common.c: Likewise.
* config.gcc: Likewise.
* config/riscv/constraints.md: Likewise.
* config/riscv/elf.h: Likewise.
* config/riscv/generic.md: Likewise.
* config/riscv/linux.h: Likewise.
* config/riscv/multilib-generator: Likewise.
* config/riscv/peephole.md: Likewise.
* config/riscv/pic.md: Likewise.
* config/riscv/predicates.md: Likewise.
* config/riscv/riscv-builtins.c: Likewise.
* config/riscv/riscv-c.c: Likewise.
* config/riscv/riscv-ftypes.def: Likewise.
* config/riscv/riscv-modes.def: Likewise.
* config/riscv/riscv-opts.h: Likewise.
* config/riscv/riscv-protos.h: Likewise.
* config/riscv/riscv.h: Likewise.
* config/riscv/riscv.md: Likewise.
* config/riscv/riscv.opt: Likewise.
* config/riscv/sync.md: Likewise.
* config/riscv/t-elf-multilib: Likewise.
* config/riscv/t-linux: Likewise.
* config/riscv/t-linux-multilib: Likewise.
* config/riscv/t-riscv: Likewise.
* configure.ac: Likewise.
* doc/contrib.texi: Add Kito Cheng, Palmer Dabbelt, and Andrew
Waterman as RISC-V maintainers.
* doc/install.texi: Add RISC-V entries.
* doc/invoke.texi: Add RISC-V options section.
* doc/md.texi: Add RISC-V constraints section.
2017-02-06 Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/66144
......
gcc/common/config/riscv/riscv-common.c 0 → 100644
/* Common hooks for RISC-V.
Copyright (C) 2016 Free Software Foundation, Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
GCC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
#include "config.h"
#include "system.h"
#include "coretypes.h"
#include "tm.h"
#include "common/common-target.h"
#include "common/common-target-def.h"
#include "opts.h"
#include "flags.h"
#include "diagnostic-core.h"
/* Parse a RISC-V ISA string into an option mask. */
static void
riscv_parse_arch_string (const char *isa, int *flags, location_t loc)
{
const char *p = isa;
if (strncmp (p, "rv32", 4) == 0)
*flags &= ~MASK_64BIT, p += 4;
else if (strncmp (p, "rv64", 4) == 0)
*flags |= MASK_64BIT, p += 4;
else
{
error_at (loc, "-march=%s: ISA string must begin with rv32 or rv64", isa);
return;
}
if (*p == 'g')
{
p++;
*flags |= MASK_MUL;
*flags |= MASK_ATOMIC;
*flags |= MASK_HARD_FLOAT;
*flags |= MASK_DOUBLE_FLOAT;
}
else if (*p == 'i')
{
p++;
*flags &= ~MASK_MUL;
if (*p == 'm')
*flags |= MASK_MUL, p++;
*flags &= ~MASK_ATOMIC;
if (*p == 'a')
*flags |= MASK_ATOMIC, p++;
*flags &= ~(MASK_HARD_FLOAT | MASK_DOUBLE_FLOAT);
if (*p == 'f')
{
*flags |= MASK_HARD_FLOAT, p++;
if (*p == 'd')
{
*flags |= MASK_DOUBLE_FLOAT;
p++;
}
}
}
else
{
error_at (loc, "-march=%s: invalid ISA string", isa);
return;
}
*flags &= ~MASK_RVC;
if (*p == 'c')
*flags |= MASK_RVC, p++;
if (*p)
{
error_at (loc, "-march=%s: unsupported ISA substring %qs", isa, p);
return;
}
}
/* Implement TARGET_HANDLE_OPTION. */
static bool
riscv_handle_option (struct gcc_options *opts,
struct gcc_options *opts_set ATTRIBUTE_UNUSED,
const struct cl_decoded_option *decoded,
location_t loc)
{
switch (decoded->opt_index)
{
case OPT_march_:
riscv_parse_arch_string (decoded->arg, &opts->x_target_flags, loc);
return true;
default:
return true;
}
}
/* Implement TARGET_OPTION_OPTIMIZATION_TABLE. */
static const struct default_options riscv_option_optimization_table[] =
{
{ OPT_LEVELS_1_PLUS, OPT_fsection_anchors, NULL, 1 },
{ OPT_LEVELS_1_PLUS, OPT_fomit_frame_pointer, NULL, 1 },
{ OPT_LEVELS_2_PLUS, OPT_free, NULL, 1 },
{ OPT_LEVELS_NONE, 0, NULL, 0 }
};
#undef TARGET_OPTION_OPTIMIZATION_TABLE
#define TARGET_OPTION_OPTIMIZATION_TABLE riscv_option_optimization_table
#undef TARGET_HANDLE_OPTION
#define TARGET_HANDLE_OPTION riscv_handle_option
struct gcc_targetm_common targetm_common = TARGETM_COMMON_INITIALIZER;
gcc/config.gcc
......@@ -451,6 +451,10 @@ powerpc*-*-*)
esac
extra_options="${extra_options} g.opt fused-madd.opt rs6000/rs6000-tables.opt"
;;
riscv*)
cpu_type=riscv
extra_objs="riscv-builtins.o riscv-c.o"
;;
rs6000*-*-*)
extra_options="${extra_options} g.opt fused-madd.opt rs6000/rs6000-tables.opt"
;;
......@@ -2016,6 +2020,34 @@ microblaze*-*-elf)
cxx_target_objs="${cxx_target_objs} microblaze-c.o"
tmake_file="${tmake_file} microblaze/t-microblaze"
;;
riscv*-*-linux*)
tm_file="elfos.h gnu-user.h linux.h glibc-stdint.h ${tm_file} riscv/linux.h"
case "x${enable_multilib}" in
xno) ;;
xyes) tmake_file="${tmake_file} riscv/t-linux-multilib" ;;
*) echo "Unknown value for enable_multilib"; exit 1
esac
tmake_file="${tmake_file} riscv/t-riscv riscv/t-linux"
gnu_ld=yes
gas=yes
# Force .init_array support. The configure script cannot always
# automatically detect that GAS supports it, yet we require it.
gcc_cv_initfini_array=yes
;;
riscv*-*-elf*)
tm_file="elfos.h newlib-stdint.h ${tm_file} riscv/elf.h"
case "x${enable_multilib}" in
xno) ;;
xyes) tmake_file="${tmake_file} riscv/t-elf-multilib" ;;
*) echo "Unknown value for enable_multilib"; exit 1
esac
tmake_file="${tmake_file} riscv/t-riscv"
gnu_ld=yes
gas=yes
# Force .init_array support. The configure script cannot always
# automatically detect that GAS supports it, yet we require it.
gcc_cv_initfini_array=yes
;;
mips*-*-netbsd*) # NetBSD/mips, either endian.
target_cpu_default="MASK_ABICALLS"
tm_file="elfos.h ${tm_file} mips/elf.h netbsd.h netbsd-elf.h mips/netbsd.h"
......@@ -3939,6 +3971,70 @@ case "${target}" in
done
;;
riscv*-*-*)
supported_defaults="abi arch tune"
case "${target}" in
riscv32*) xlen=32 ;;
riscv64*) xlen=64 ;;
*) echo "Unsupported RISC-V target ${target}" 1>&2; exit 1 ;;
esac
# Infer arch from --with-arch, --target, and --with-abi.
case "${with_arch}" in
rv32i* | rv32g* | rv64i* | rv64g*)
# OK.
;;
"")
# Infer XLEN, but otherwise assume GC.
case "${with_abi}" in
ilp32 | ilp32f | ilp32d) with_arch="rv32gc" ;;
lp64 | lp64f | lp64d) with_arch="rv64gc" ;;
*) with_arch="rv${xlen}gc" ;;
esac
;;
*)
echo "--with-arch=${with_arch} is not supported. The argument must begin with rv32i, rv32g, rv64i, or rv64g." 1>&2
exit 1
;;
esac
# Make sure --with-abi is valid. If it was not specified,
# pick a default based on the ISA, preferring soft-float
# unless the D extension is present.
case "${with_abi}" in
ilp32 | ilp32f | ilp32d | lp64 | lp64f | lp64d)
;;
"")
case "${with_arch}" in
rv32*d* | rv32g*) with_abi=ilp32d ;;
rv32*) with_abi=ilp32 ;;
rv64*d* | rv64g*) with_abi=lp64d ;;
rv64*) with_abi=lp64 ;;
esac
;;
*)
echo "--with-abi=${with_abi} is not supported" 1>&2
exit 1
;;
esac
# Make sure ABI and ISA are compatible.
case "${with_abi},${with_arch}" in
ilp32,rv32* \
| ilp32f,rv32*f* | ilp32f,rv32g* \
| ilp32d,rv32*d* | ilp32d,rv32g* \
| lp64,rv64* \
| lp64f,rv64*f* | lp64f,rv64g* \
| lp64d,rv64*d* | lp64d,rv64g*)
;;
*)
echo "--with-abi=${with_abi} is not supported for ISA ${with_arch}" 1>&2
exit 1
;;
esac
;;
mips*-*-*)
supported_defaults="abi arch arch_32 arch_64 float fpu nan fp_32 odd_spreg_32 tune tune_32 tune_64 divide llsc mips-plt synci lxc1-sxc1 madd4"
......
gcc/config/riscv/constraints.md 0 → 100644
;; Constraint definitions for RISC-V target.
;; Copyright (C) 2011-2017 Free Software Foundation, Inc.
;; Contributed by Andrew Waterman (andrew@sifive.com).
;; Based on MIPS target for GNU compiler.
;;
;; This file is part of GCC.
;;
;; GCC is free software; you can redistribute it and/or modify
;; it under the terms of the GNU General Public License as published by
;; the Free Software Foundation; either version 3, or (at your option)
;; any later version.
;;
;; GCC is distributed in the hope that it will be useful,
;; but WITHOUT ANY WARRANTY; without even the implied warranty of
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
;; GNU General Public License for more details.
;;
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.
;; Register constraints
(define_register_constraint "f" "TARGET_HARD_FLOAT ? FP_REGS : NO_REGS"
"A floating-point register (if available).")
(define_register_constraint "j" "SIBCALL_REGS"
"@internal")
;; Avoid using register t0 for JALR's argument, because for some
;; microarchitectures that is a return-address stack hint.
(define_register_constraint "l" "JALR_REGS"
"@internal")
;; General constraints
(define_constraint "I"
"An I-type 12-bit signed immediate."
(and (match_code "const_int")
(match_test "SMALL_OPERAND (ival)")))
(define_constraint "J"
"Integer zero."
(and (match_code "const_int")
(match_test "ival == 0")))
(define_constraint "K"
"A 5-bit unsigned immediate for CSR access instructions."
(and (match_code "const_int")
(match_test "IN_RANGE (ival, 0, 31)")))
;; Floating-point constant +0.0, used for FCVT-based moves when FMV is
;; not available in RV32.
(define_constraint "G"
"@internal"
(and (match_code "const_double")
(match_test "op == CONST0_RTX (mode)")))
(define_memory_constraint "A"
"An address that is held in a general-purpose register."
(and (match_code "mem")
(match_test "GET_CODE(XEXP(op,0)) == REG")))
(define_constraint "S"
"@internal
A constant call address."
(match_operand 0 "absolute_symbolic_operand"))
(define_constraint "U"
"@internal
A PLT-indirect call address."
(match_operand 0 "plt_symbolic_operand"))
(define_constraint "T"
"@internal
A constant @code{move_operand}."
(and (match_operand 0 "move_operand")
(match_test "CONSTANT_P (op)")))
gcc/config/riscv/elf.h 0 → 100644
/* Target macros for riscv*-elf targets.
Copyright (C) 1994-2017 Free Software Foundation, Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
GCC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
#define LINK_SPEC "\
-melf" XLEN_SPEC "lriscv \
%{shared}"
/* Link against Newlib libraries, because the ELF backend assumes Newlib.
Handle the circular dependence between libc and libgloss. */
#undef LIB_SPEC
#define LIB_SPEC "--start-group -lc -lgloss --end-group"
#undef STARTFILE_SPEC
#define STARTFILE_SPEC "crt0%O%s crtbegin%O%s"
#undef ENDFILE_SPEC
#define ENDFILE_SPEC "crtend%O%s"
#define NO_IMPLICIT_EXTERN_C 1
gcc/config/riscv/generic.md 0 → 100644
;; Generic DFA-based pipeline description for RISC-V targets.
;; Copyright (C) 2011-2017 Free Software Foundation, Inc.
;; Contributed by Andrew Waterman (andrew@sifive.com).
;; Based on MIPS target for GNU compiler.
;; This file is part of GCC.
;; GCC is free software; you can redistribute it and/or modify it
;; under the terms of the GNU General Public License as published
;; by the Free Software Foundation; either version 3, or (at your
;; option) any later version.
;; GCC is distributed in the hope that it will be useful, but WITHOUT
;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
;; License for more details.
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.
(define_automaton "pipe0")
(define_cpu_unit "alu" "pipe0")
(define_cpu_unit "imuldiv" "pipe0")
(define_cpu_unit "fdivsqrt" "pipe0")
(define_insn_reservation "generic_alu" 1
(eq_attr "type" "unknown,const,arith,shift,slt,multi,nop,logical,move")
"alu")
(define_insn_reservation "generic_load" 3
(eq_attr "type" "load,fpload")
"alu")
(define_insn_reservation "generic_store" 1
(eq_attr "type" "store,fpstore")
"alu")
(define_insn_reservation "generic_xfer" 3
(eq_attr "type" "mfc,mtc,fcvt,fmove,fcmp")
"alu")
(define_insn_reservation "generic_branch" 1
(eq_attr "type" "branch,jump,call")
"alu")
(define_insn_reservation "generic_imul" 10
(eq_attr "type" "imul")
"imuldiv*10")
(define_insn_reservation "generic_idivsi" 34
(and (eq_attr "type" "idiv")
(eq_attr "mode" "SI"))
"imuldiv*34")
(define_insn_reservation "generic_idivdi" 66
(and (eq_attr "type" "idiv")
(eq_attr "mode" "DI"))
"imuldiv*66")
(define_insn_reservation "generic_fmul_single" 5
(and (eq_attr "type" "fadd,fmul,fmadd")
(eq_attr "mode" "SF"))
"alu")
(define_insn_reservation "generic_fmul_double" 7
(and (eq_attr "type" "fadd,fmul,fmadd")
(eq_attr "mode" "DF"))
"alu")
(define_insn_reservation "generic_fdiv" 20
(eq_attr "type" "fdiv")
"fdivsqrt*20")
(define_insn_reservation "generic_fsqrt" 25
(eq_attr "type" "fsqrt")
"fdivsqrt*25")
gcc/config/riscv/linux.h 0 → 100644
/* Definitions for RISC-V GNU/Linux systems with ELF format.
Copyright (C) 1998-2017 Free Software Foundation, Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
GCC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
#define TARGET_OS_CPP_BUILTINS() \
do { \
GNU_USER_TARGET_OS_CPP_BUILTINS(); \
} while (0)
#define GLIBC_DYNAMIC_LINKER "/lib/ld-linux-riscv" XLEN_SPEC "-" ABI_SPEC ".so.1"
/* Because RISC-V only has word-sized atomics, it requries libatomic where
others do not. So link libatomic by default, as needed. */
#undef LIB_SPEC
#ifdef LD_AS_NEEDED_OPTION
#define LIB_SPEC GNU_USER_TARGET_LIB_SPEC \
" %{pthread:" LD_AS_NEEDED_OPTION " -latomic " LD_NO_AS_NEEDED_OPTION "}"
#else
#define LIB_SPEC GNU_USER_TARGET_LIB_SPEC " -latomic "
#endif
#define LINK_SPEC "\
-melf" XLEN_SPEC "lriscv \
%{shared} \
%{!shared: \
%{!static: \
%{rdynamic:-export-dynamic} \
-dynamic-linker " GNU_USER_DYNAMIC_LINKER "} \
%{static:-static}}"
gcc/config/riscv/multilib-generator 0 → 100755
#!/usr/bin/env python
# RISC-V multilib list generator.
# Copyright (C) 2011-2017 Free Software Foundation, Inc.
# Contributed by Andrew Waterman (andrew@sifive.com).
#
# This file is part of GCC.
#
# GCC is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 3, or (at your option)
# any later version.
#
# GCC is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with GCC; see the file COPYING3. If not see
# <http://www.gnu.org/licenses/>.
# Each argument to this script is of the form
# <primary arch>-<abi>-<additional arches>-<extensions>
# For example,
# rv32imafd-ilp32d-rv32g-c,v
# means that, in addition to rv32imafd, these configurations can also use the
# rv32imafd-ilp32d libraries: rv32imafdc, rv32imafdv, rv32g, rv32gc, rv32gv
from __future__ import print_function
import sys
import collections
arches = collections.OrderedDict()
abis = collections.OrderedDict()
required = []
reuse = []
for cfg in sys.argv[1:]:
(arch, abi, extra, ext) = cfg.split('-')
arches[arch] = 1
abis[abi] = 1
extra = list(filter(None, extra.split(',')))
ext = list(filter(None, ext.split(',')))
alts = sum([[x] + [x + y for y in ext] for x in [arch] + extra], [])
alts = alts + [x.replace('imafd', 'g') for x in alts if 'imafd' in x]
for alt in alts[1:]:
arches[alt] = 1
reuse.append('march.%s/mabi.%s=march.%s/mabi.%s' % (arch, abi, alt, abi))
required.append('march=%s/mabi=%s' % (arch, abi))
arch_options = '/'.join(['march=%s' % x for x in arches.keys()])
arch_dirnames = ' \\\n'.join(arches.keys())
abi_options = '/'.join(['mabi=%s' % x for x in abis.keys()])
abi_dirnames = ' \\\n'.join(abis.keys())
prog = sys.argv[0].split('/')[-1]
print('# This file was generated by %s with the command:' % prog)
print('# %s' % ' '.join(sys.argv))
print('MULTILIB_OPTIONS = %s %s' % (arch_options, abi_options))
print('MULTILIB_DIRNAMES = %s %s' % (arch_dirnames, abi_dirnames))
print('MULTILIB_REQUIRED = %s' % ' \\\n'.join(required))
print('MULTILIB_REUSE = %s' % ' \\\n'.join(reuse))
gcc/config/riscv/peephole.md 0 → 100644
;; Peephole optimizations for RISC-V for GNU compiler.
;; Copyright (C) 2011-2017 Free Software Foundation, Inc.
;; Contributed by Andrew Waterman (andrew@sifive.com).
;; This file is part of GCC.
;; GCC is free software; you can redistribute it and/or modify
;; it under the terms of the GNU General Public License as published by
;; the Free Software Foundation; either version 3, or (at your option)
;; any later version.
;; GCC is distributed in the hope that it will be useful,
;; but WITHOUT ANY WARRANTY; without even the implied warranty of
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
;; GNU General Public License for more details.
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.
;; Simplify (unsigned long)(unsigned int)a << const
(define_peephole2
[(set (match_operand:DI 0 "register_operand")
(ashift:DI (match_operand:DI 1 "register_operand")
(match_operand 2 "const_int_operand")))
(set (match_operand:DI 3 "register_operand")
(lshiftrt:DI (match_dup 0) (match_dup 2)))
(set (match_operand:DI 4 "register_operand")
(ashift:DI (match_dup 3) (match_operand 5 "const_int_operand")))]
"TARGET_64BIT
&& INTVAL (operands[5]) < INTVAL (operands[2])
&& (REGNO (operands[3]) == REGNO (operands[4])
|| peep2_reg_dead_p (3, operands[3]))"
[(set (match_dup 0)
(ashift:DI (match_dup 1) (match_dup 2)))
(set (match_dup 4)
(lshiftrt:DI (match_dup 0) (match_operand 5)))]
{
operands[5] = GEN_INT (INTVAL (operands[2]) - INTVAL (operands[5]));
})
gcc/config/riscv/pic.md 0 → 100644
;; PIC codegen for RISC-V for GNU compiler.
;; Copyright (C) 2011-2017 Free Software Foundation, Inc.
;; Contributed by Andrew Waterman (andrew@sifive.com).
;; This file is part of GCC.
;; GCC is free software; you can redistribute it and/or modify
;; it under the terms of the GNU General Public License as published by
;; the Free Software Foundation; either version 3, or (at your option)
;; any later version.
;; GCC is distributed in the hope that it will be useful,
;; but WITHOUT ANY WARRANTY; without even the implied warranty of
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
;; GNU General Public License for more details.
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.
;; Simplify PIC loads to static variables.
;; These should go away once we figure out how to emit auipc discretely.
(define_insn "*local_pic_load<mode>"
[(set (match_operand:ANYI 0 "register_operand" "=r")
(mem:ANYI (match_operand 1 "absolute_symbolic_operand" "")))]
"USE_LOAD_ADDRESS_MACRO (operands[1])"
"<load>\t%0,%1"
[(set (attr "length") (const_int 8))])
(define_insn "*local_pic_load<mode>"
[(set (match_operand:ANYF 0 "register_operand" "=f")
(mem:ANYF (match_operand 1 "absolute_symbolic_operand" "")))
(clobber (match_scratch:DI 2 "=r"))]
"TARGET_HARD_FLOAT && TARGET_64BIT && USE_LOAD_ADDRESS_MACRO (operands[1])"
"<load>\t%0,%1,%2"
[(set (attr "length") (const_int 8))])
(define_insn "*local_pic_load<mode>"
[(set (match_operand:ANYF 0 "register_operand" "=f")
(mem:ANYF (match_operand 1 "absolute_symbolic_operand" "")))
(clobber (match_scratch:SI 2 "=r"))]
"TARGET_HARD_FLOAT && !TARGET_64BIT && USE_LOAD_ADDRESS_MACRO (operands[1])"
"<load>\t%0,%1,%2"
[(set (attr "length") (const_int 8))])
(define_insn "*local_pic_loadu<mode>"
[(set (match_operand:SUPERQI 0 "register_operand" "=r")
(zero_extend:SUPERQI (mem:SUBX (match_operand 1 "absolute_symbolic_operand" ""))))]
"USE_LOAD_ADDRESS_MACRO (operands[1])"
"<load>u\t%0,%1"
[(set (attr "length") (const_int 8))])
(define_insn "*local_pic_storedi<mode>"
[(set (mem:ANYI (match_operand 0 "absolute_symbolic_operand" ""))
(match_operand:ANYI 1 "reg_or_0_operand" "rJ"))
(clobber (match_scratch:DI 2 "=&r"))]
"TARGET_64BIT && USE_LOAD_ADDRESS_MACRO (operands[0])"
"<store>\t%z1,%0,%2"
[(set (attr "length") (const_int 8))])
(define_insn "*local_pic_storesi<mode>"
[(set (mem:ANYI (match_operand 0 "absolute_symbolic_operand" ""))
(match_operand:ANYI 1 "reg_or_0_operand" "rJ"))
(clobber (match_scratch:SI 2 "=&r"))]
"!TARGET_64BIT && USE_LOAD_ADDRESS_MACRO (operands[0])"
"<store>\t%z1,%0,%2"
[(set (attr "length") (const_int 8))])
(define_insn "*local_pic_storedi<mode>"
[(set (mem:ANYF (match_operand 0 "absolute_symbolic_operand" ""))
(match_operand:ANYF 1 "register_operand" "f"))
(clobber (match_scratch:DI 2 "=r"))]
"TARGET_HARD_FLOAT && TARGET_64BIT && USE_LOAD_ADDRESS_MACRO (operands[0])"
"<store>\t%1,%0,%2"
[(set (attr "length") (const_int 8))])
(define_insn "*local_pic_storesi<mode>"
[(set (mem:ANYF (match_operand 0 "absolute_symbolic_operand" ""))
(match_operand:ANYF 1 "register_operand" "f"))
(clobber (match_scratch:SI 2 "=r"))]
"TARGET_HARD_FLOAT && !TARGET_64BIT && USE_LOAD_ADDRESS_MACRO (operands[0])"
"<store>\t%1,%0,%2"
[(set (attr "length") (const_int 8))])
gcc/config/riscv/predicates.md 0 → 100644
;; Predicate description for RISC-V target.
;; Copyright (C) 2011-2017 Free Software Foundation, Inc.
;; Contributed by Andrew Waterman (andrew@sifive.com).
;; Based on MIPS target for GNU compiler.
;;
;; This file is part of GCC.
;;
;; GCC is free software; you can redistribute it and/or modify
;; it under the terms of the GNU General Public License as published by
;; the Free Software Foundation; either version 3, or (at your option)
;; any later version.
;;
;; GCC is distributed in the hope that it will be useful,
;; but WITHOUT ANY WARRANTY; without even the implied warranty of
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
;; GNU General Public License for more details.
;;
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.
(define_predicate "const_arith_operand"
(and (match_code "const_int")
(match_test "SMALL_OPERAND (INTVAL (op))")))
(define_predicate "arith_operand"
(ior (match_operand 0 "const_arith_operand")
(match_operand 0 "register_operand")))
(define_predicate "const_csr_operand"
(and (match_code "const_int")
(match_test "IN_RANGE (INTVAL (op), 0, 31)")))
(define_predicate "csr_operand"
(ior (match_operand 0 "const_csr_operand")
(match_operand 0 "register_operand")))
(define_predicate "sle_operand"
(and (match_code "const_int")
(match_test "SMALL_OPERAND (INTVAL (op) + 1)")))
(define_predicate "sleu_operand"
(and (match_operand 0 "sle_operand")
(match_test "INTVAL (op) + 1 != 0")))
(define_predicate "const_0_operand"
(and (match_code "const_int,const_wide_int,const_double,const_vector")
(match_test "op == CONST0_RTX (GET_MODE (op))")))
(define_predicate "reg_or_0_operand"
(ior (match_operand 0 "const_0_operand")
(match_operand 0 "register_operand")))
;; Only use branch-on-bit sequences when the mask is not an ANDI immediate.
(define_predicate "branch_on_bit_operand"
(and (match_code "const_int")
(match_test "INTVAL (op) >= IMM_BITS - 1")))
;; A legitimate CONST_INT operand that takes more than one instruction
;; to load.
(define_predicate "splittable_const_int_operand"
(match_code "const_int")
{
/* Don't handle multi-word moves this way; we don't want to introduce
the individual word-mode moves until after reload. */
if (GET_MODE_SIZE (mode) > UNITS_PER_WORD)
return false;
/* Otherwise check whether the constant can be loaded in a single
instruction. */
return !LUI_OPERAND (INTVAL (op)) && !SMALL_OPERAND (INTVAL (op));
})
(define_predicate "move_operand"
(match_operand 0 "general_operand")
{
enum riscv_symbol_type symbol_type;
/* The thinking here is as follows:
(1) The move expanders should split complex load sequences into
individual instructions. Those individual instructions can
then be optimized by all rtl passes.
(2) The target of pre-reload load sequences should not be used
to store temporary results. If the target register is only
assigned one value, reload can rematerialize that value
on demand, rather than spill it to the stack.
(3) If we allowed pre-reload passes like combine and cse to recreate
complex load sequences, we would want to be able to split the
sequences before reload as well, so that the pre-reload scheduler
can see the individual instructions. This falls foul of (2);
the splitter would be forced to reuse the target register for
intermediate results.
(4) We want to define complex load splitters for combine. These
splitters can request a temporary scratch register, which avoids
the problem in (2). They allow things like:
(set (reg T1) (high SYM))
(set (reg T2) (low (reg T1) SYM))
(set (reg X) (plus (reg T2) (const_int OFFSET)))
to be combined into:
(set (reg T3) (high SYM+OFFSET))
(set (reg X) (lo_sum (reg T3) SYM+OFFSET))
if T2 is only used this once. */
switch (GET_CODE (op))
{
case CONST_INT:
return !splittable_const_int_operand (op, mode);
case CONST:
case SYMBOL_REF:
case LABEL_REF:
return riscv_symbolic_constant_p (op, &symbol_type)
&& !riscv_split_symbol_type (symbol_type);
case HIGH:
op = XEXP (op, 0);
return riscv_symbolic_constant_p (op, &symbol_type)
&& riscv_split_symbol_type (symbol_type)
&& symbol_type != SYMBOL_PCREL;
default:
return true;
}
})
(define_predicate "symbolic_operand"
(match_code "const,symbol_ref,label_ref")
{
enum riscv_symbol_type type;
return riscv_symbolic_constant_p (op, &type);
})
(define_predicate "absolute_symbolic_operand"
(match_code "const,symbol_ref,label_ref")
{
enum riscv_symbol_type type;
return (riscv_symbolic_constant_p (op, &type)
&& (type == SYMBOL_ABSOLUTE || type == SYMBOL_PCREL));
})
(define_predicate "plt_symbolic_operand"
(match_code "const,symbol_ref,label_ref")
{
enum riscv_symbol_type type;
return (riscv_symbolic_constant_p (op, &type)
&& type == SYMBOL_GOT_DISP && !SYMBOL_REF_WEAK (op) && TARGET_PLT);
})
(define_predicate "call_insn_operand"
(ior (match_operand 0 "absolute_symbolic_operand")
(match_operand 0 "plt_symbolic_operand")
(match_operand 0 "register_operand")))
(define_predicate "modular_operator"
(match_code "plus,minus,mult,ashift"))
(define_predicate "equality_operator"
(match_code "eq,ne"))
(define_predicate "order_operator"
(match_code "eq,ne,lt,ltu,le,leu,ge,geu,gt,gtu"))
(define_predicate "signed_order_operator"
(match_code "eq,ne,lt,le,ge,gt"))
(define_predicate "fp_native_comparison"
(match_code "eq,lt,le,gt,ge"))
(define_predicate "fp_scc_comparison"
(match_code "unordered,ordered,unlt,unge,unle,ungt,ltgt,ne,eq,lt,le,gt,ge"))
(define_predicate "fp_branch_comparison"
(match_code "unordered,ordered,unlt,unge,unle,ungt,uneq,ltgt,ne,eq,lt,le,gt,ge"))
gcc/config/riscv/riscv-builtins.c 0 → 100644
/* Subroutines used for expanding RISC-V builtins.
Copyright (C) 2011-2017 Free Software Foundation, Inc.
Contributed by Andrew Waterman (andrew@sifive.com).
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
GCC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
#include "config.h"
#include "system.h"
#include "coretypes.h"
#include "tm.h"
#include "rtl.h"
#include "tree.h"
#include "gimple-expr.h"
#include "memmodel.h"
#include "expmed.h"
#include "optabs.h"
#include "recog.h"
#include "diagnostic-core.h"
#include "stor-layout.h"
#include "expr.h"
#include "langhooks.h"
/* Macros to create an enumeration identifier for a function prototype. */
#define RISCV_FTYPE_NAME1(A, B) RISCV_##A##_FTYPE_##B
/* Classifies the prototype of a built-in function. */
enum riscv_function_type {
#define DEF_RISCV_FTYPE(NARGS, LIST) RISCV_FTYPE_NAME##NARGS LIST,
#include "config/riscv/riscv-ftypes.def"
#undef DEF_RISCV_FTYPE
RISCV_MAX_FTYPE_MAX
};
/* Specifies how a built-in function should be converted into rtl. */
enum riscv_builtin_type {
/* The function corresponds directly to an .md pattern. */
RISCV_BUILTIN_DIRECT,
/* Likewise, but with return type VOID. */
RISCV_BUILTIN_DIRECT_NO_TARGET
};
/* Declare an availability predicate for built-in functions. */
#define AVAIL(NAME, COND) \
static unsigned int \
riscv_builtin_avail_##NAME (void) \
{ \
return (COND); \
}
/* This structure describes a single built-in function. */
struct riscv_builtin_description {
/* The code of the main .md file instruction. See riscv_builtin_type
for more information. */
enum insn_code icode;
/* The name of the built-in function. */
const char *name;
/* Specifies how the function should be expanded. */
enum riscv_builtin_type builtin_type;
/* The function's prototype. */
enum riscv_function_type prototype;
/* Whether the function is available. */
unsigned int (*avail) (void);
};
AVAIL (hard_float, TARGET_HARD_FLOAT)
/* Construct a riscv_builtin_description from the given arguments.
INSN is the name of the associated instruction pattern, without the
leading CODE_FOR_riscv_.
NAME is the name of the function itself, without the leading
"__builtin_riscv_".
BUILTIN_TYPE and FUNCTION_TYPE are riscv_builtin_description fields.
AVAIL is the name of the availability predicate, without the leading
riscv_builtin_avail_. */
#define RISCV_BUILTIN(INSN, NAME, BUILTIN_TYPE, FUNCTION_TYPE, AVAIL) \
{ CODE_FOR_riscv_ ## INSN, "__builtin_riscv_" NAME, \
BUILTIN_TYPE, FUNCTION_TYPE, riscv_builtin_avail_ ## AVAIL }
/* Define __builtin_riscv_<INSN>, which is a RISCV_BUILTIN_DIRECT function
mapped to instruction CODE_FOR_riscv_<INSN>, FUNCTION_TYPE and AVAIL
are as for RISCV_BUILTIN. */
#define DIRECT_BUILTIN(INSN, FUNCTION_TYPE, AVAIL) \
RISCV_BUILTIN (INSN, #INSN, RISCV_BUILTIN_DIRECT, FUNCTION_TYPE, AVAIL)
/* Define __builtin_riscv_<INSN>, which is a RISCV_BUILTIN_DIRECT_NO_TARGET
function mapped to instruction CODE_FOR_riscv_<INSN>, FUNCTION_TYPE
and AVAIL are as for RISCV_BUILTIN. */
#define DIRECT_NO_TARGET_BUILTIN(INSN, FUNCTION_TYPE, AVAIL) \
RISCV_BUILTIN (INSN, #INSN, RISCV_BUILTIN_DIRECT_NO_TARGET, \
FUNCTION_TYPE, AVAIL)
/* Argument types. */
#define RISCV_ATYPE_VOID void_type_node
#define RISCV_ATYPE_USI unsigned_intSI_type_node
/* RISCV_FTYPE_ATYPESN takes N RISCV_FTYPES-like type codes and lists
their associated RISCV_ATYPEs. */
#define RISCV_FTYPE_ATYPES1(A, B) \
RISCV_ATYPE_##A, RISCV_ATYPE_##B
static const struct riscv_builtin_description riscv_builtins[] = {
DIRECT_BUILTIN (frflags, RISCV_USI_FTYPE_VOID, hard_float),
DIRECT_NO_TARGET_BUILTIN (fsflags, RISCV_VOID_FTYPE_USI, hard_float)
};
/* Index I is the function declaration for riscv_builtins[I], or null if the
function isn't defined on this target. */
static GTY(()) tree riscv_builtin_decls[ARRAY_SIZE (riscv_builtins)];
/* Get the index I of the function declaration for riscv_builtin_decls[I]
using the instruction code or return null if not defined for the target. */
static GTY(()) int riscv_builtin_decl_index[NUM_INSN_CODES];
#define GET_BUILTIN_DECL(CODE) \
riscv_builtin_decls[riscv_builtin_decl_index[(CODE)]]
/* Return the function type associated with function prototype TYPE. */
static tree
riscv_build_function_type (enum riscv_function_type type)
{
static tree types[(int) RISCV_MAX_FTYPE_MAX];
if (types[(int) type] == NULL_TREE)
switch (type)
{
#define DEF_RISCV_FTYPE(NUM, ARGS) \
case RISCV_FTYPE_NAME##NUM ARGS: \
types[(int) type] \
= build_function_type_list (RISCV_FTYPE_ATYPES##NUM ARGS, \
NULL_TREE); \
break;
#include "config/riscv/riscv-ftypes.def"
#undef DEF_RISCV_FTYPE
default:
gcc_unreachable ();
}
return types[(int) type];
}
/* Implement TARGET_INIT_BUILTINS. */
void
riscv_init_builtins (void)
{
for (size_t i = 0; i < ARRAY_SIZE (riscv_builtins); i++)
{
const struct riscv_builtin_description *d = &riscv_builtins[i];
if (d->avail ())
{
tree type = riscv_build_function_type (d->prototype);
riscv_builtin_decls[i]
= add_builtin_function (d->name, type, i, BUILT_IN_MD, NULL, NULL);
riscv_builtin_decl_index[d->icode] = i;
}
}
}
/* Implement TARGET_BUILTIN_DECL. */
tree
riscv_builtin_decl (unsigned int code, bool initialize_p ATTRIBUTE_UNUSED)
{
if (code >= ARRAY_SIZE (riscv_builtins))
return error_mark_node;
return riscv_builtin_decls[code];
}
/* Take argument ARGNO from EXP's argument list and convert it into
an expand operand. Store the operand in *OP. */
static void
riscv_prepare_builtin_arg (struct expand_operand *op, tree exp, unsigned argno)
{
tree arg = CALL_EXPR_ARG (exp, argno);
create_input_operand (op, expand_normal (arg), TYPE_MODE (TREE_TYPE (arg)));
}
/* Expand instruction ICODE as part of a built-in function sequence.
Use the first NOPS elements of OPS as the instruction's operands.
HAS_TARGET_P is true if operand 0 is a target; it is false if the
instruction has no target.
Return the target rtx if HAS_TARGET_P, otherwise return const0_rtx. */
static rtx
riscv_expand_builtin_insn (enum insn_code icode, unsigned int n_ops,
struct expand_operand *ops, bool has_target_p)
{
if (!maybe_expand_insn (icode, n_ops, ops))
{
error ("invalid argument to built-in function");
return has_target_p ? gen_reg_rtx (ops[0].mode) : const0_rtx;
}
return has_target_p ? ops[0].value : const0_rtx;
}
/* Expand a RISCV_BUILTIN_DIRECT or RISCV_BUILTIN_DIRECT_NO_TARGET function;
HAS_TARGET_P says which. EXP is the CALL_EXPR that calls the function
and ICODE is the code of the associated .md pattern. TARGET, if nonnull,
suggests a good place to put the result. */
static rtx
riscv_expand_builtin_direct (enum insn_code icode, rtx target, tree exp,
bool has_target_p)
{
struct expand_operand ops[MAX_RECOG_OPERANDS];
/* Map any target to operand 0. */
int opno = 0;
if (has_target_p)
create_output_operand (&ops[opno++], target, TYPE_MODE (TREE_TYPE (exp)));
/* Map the arguments to the other operands. */
gcc_assert (opno + call_expr_nargs (exp)
== insn_data[icode].n_generator_args);
for (int argno = 0; argno < call_expr_nargs (exp); argno++)
riscv_prepare_builtin_arg (&ops[opno++], exp, argno);
return riscv_expand_builtin_insn (icode, opno, ops, has_target_p);
}
/* Implement TARGET_EXPAND_BUILTIN. */
rtx
riscv_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
machine_mode mode ATTRIBUTE_UNUSED,
int ignore ATTRIBUTE_UNUSED)
{
tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
const struct riscv_builtin_description *d = &riscv_builtins[fcode];
switch (d->builtin_type)
{
case RISCV_BUILTIN_DIRECT:
return riscv_expand_builtin_direct (d->icode, target, exp, true);
case RISCV_BUILTIN_DIRECT_NO_TARGET:
return riscv_expand_builtin_direct (d->icode, target, exp, false);
}
gcc_unreachable ();
}
/* Implement TARGET_ATOMIC_ASSIGN_EXPAND_FENV. */
void
riscv_atomic_assign_expand_fenv (tree *hold, tree *clear, tree *update)
{
if (!TARGET_HARD_FLOAT)
return;
tree frflags = GET_BUILTIN_DECL (CODE_FOR_riscv_frflags);
tree fsflags = GET_BUILTIN_DECL (CODE_FOR_riscv_fsflags);
tree old_flags = create_tmp_var_raw (RISCV_ATYPE_USI);
*hold = build2 (MODIFY_EXPR, RISCV_ATYPE_USI, old_flags,
build_call_expr (frflags, 0));
*clear = build_call_expr (fsflags, 1, old_flags);
*update = NULL_TREE;
}
gcc/config/riscv/riscv-c.c 0 → 100644
/* RISC-V-specific code for C family languages.
Copyright (C) 2011-2017 Free Software Foundation, Inc.
Contributed by Andrew Waterman (andrew@sifive.com).
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
GCC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
#include "config.h"
#include "system.h"
#include "coretypes.h"
#include "tm.h"
#include "c-family/c-common.h"
#include "cpplib.h"
#define builtin_define(TXT) cpp_define (pfile, TXT)
/* Implement TARGET_CPU_CPP_BUILTINS. */
void
riscv_cpu_cpp_builtins (cpp_reader *pfile)
{
builtin_define ("__riscv");
if (TARGET_RVC)
builtin_define ("__riscv_compressed");
if (TARGET_ATOMIC)
builtin_define ("__riscv_atomic");
if (TARGET_MUL)
builtin_define ("__riscv_mul");
if (TARGET_DIV)
builtin_define ("__riscv_div");
if (TARGET_DIV && TARGET_MUL)
builtin_define ("__riscv_muldiv");
builtin_define_with_int_value ("__riscv_xlen", UNITS_PER_WORD * 8);
if (TARGET_HARD_FLOAT)
builtin_define_with_int_value ("__riscv_flen", UNITS_PER_FP_REG * 8);
if (TARGET_HARD_FLOAT && TARGET_FDIV)
{
builtin_define ("__riscv_fdiv");
builtin_define ("__riscv_fsqrt");
}
switch (riscv_abi)
{
case ABI_ILP32:
case ABI_LP64:
builtin_define ("__riscv_float_abi_soft");
break;
case ABI_ILP32F:
case ABI_LP64F:
builtin_define ("__riscv_float_abi_single");
break;
case ABI_ILP32D:
case ABI_LP64D:
builtin_define ("__riscv_float_abi_double");
break;
}
switch (riscv_cmodel)
{
case CM_MEDLOW:
builtin_define ("__riscv_cmodel_medlow");
break;
case CM_MEDANY:
builtin_define ("__riscv_cmodel_medany");
break;
case CM_PIC:
builtin_define ("__riscv_cmodel_pic");
break;
}
}
gcc/config/riscv/riscv-ftypes.def 0 → 100644
/* Definitions of prototypes for RISC-V built-in functions. -*- C -*-
Copyright (C) 2011-2017 Free Software Foundation, Inc.
Contributed by Andrew Waterman (andrew@sifive.com).
Based on MIPS target for GNU compiler.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
GCC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
/* Invoke DEF_RISCV_FTYPE (NARGS, LIST) for each prototype used by
RISCV built-in functions, where:
NARGS is the number of arguments.
LIST contains the return-type code followed by the codes for each
argument type. */
DEF_RISCV_FTYPE (1, (USI, VOID))
DEF_RISCV_FTYPE (1, (VOID, USI))
gcc/config/riscv/riscv-modes.def 0 → 100644
/* Extra machine modes for RISC-V target.
Copyright (C) 2011-2017 Free Software Foundation, Inc.
Contributed by Andrew Waterman (andrew@sifive.com).
Based on MIPS target for GNU compiler.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
GCC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
FLOAT_MODE (TF, 16, ieee_quad_format);
gcc/config/riscv/riscv-opts.h 0 → 100644
/* Definition of RISC-V target for GNU compiler.
Copyright (C) 2016-2017 Free Software Foundation, Inc.
Contributed by Andrew Waterman (andrew@sifive.com).
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
GCC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
#ifndef GCC_RISCV_OPTS_H
#define GCC_RISCV_OPTS_H
enum riscv_abi_type {
ABI_ILP32,
ABI_ILP32F,
ABI_ILP32D,
ABI_LP64,
ABI_LP64F,
ABI_LP64D
};
extern enum riscv_abi_type riscv_abi;
enum riscv_code_model {
CM_MEDLOW,
CM_MEDANY,
CM_PIC
};
extern enum riscv_code_model riscv_cmodel;
#endif /* ! GCC_RISCV_OPTS_H */
gcc/config/riscv/riscv-protos.h 0 → 100644
/* Definition of RISC-V target for GNU compiler.
Copyright (C) 2011-2017 Free Software Foundation, Inc.
Contributed by Andrew Waterman (andrew@sifive.com).
Based on MIPS target for GNU compiler.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
GCC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
#ifndef GCC_RISCV_PROTOS_H
#define GCC_RISCV_PROTOS_H
/* Symbol types we understand. The order of this list must match that of
the unspec enum in riscv.md, subsequent to UNSPEC_ADDRESS_FIRST. */
enum riscv_symbol_type {
SYMBOL_ABSOLUTE,
SYMBOL_PCREL,
SYMBOL_GOT_DISP,
SYMBOL_TLS,
SYMBOL_TLS_LE,
SYMBOL_TLS_IE,
SYMBOL_TLS_GD
};
#define NUM_SYMBOL_TYPES (SYMBOL_TLS_GD + 1)
/* Routines implemented in riscv.c. */
extern enum riscv_symbol_type riscv_classify_symbolic_expression (rtx);
extern bool riscv_symbolic_constant_p (rtx, enum riscv_symbol_type *);
extern int riscv_regno_mode_ok_for_base_p (int, enum machine_mode, bool);
extern bool riscv_hard_regno_mode_ok_p (unsigned int, enum machine_mode);
extern int riscv_address_insns (rtx, enum machine_mode, bool);
extern int riscv_const_insns (rtx);
extern int riscv_split_const_insns (rtx);
extern int riscv_load_store_insns (rtx, rtx_insn *);
extern rtx riscv_emit_move (rtx, rtx);
extern bool riscv_split_symbol (rtx, rtx, enum machine_mode, rtx *);
extern bool riscv_split_symbol_type (enum riscv_symbol_type);
extern rtx riscv_unspec_address (rtx, enum riscv_symbol_type);
extern void riscv_move_integer (rtx, rtx, HOST_WIDE_INT);
extern bool riscv_legitimize_move (enum machine_mode, rtx, rtx);
extern rtx riscv_subword (rtx, bool);
extern bool riscv_split_64bit_move_p (rtx, rtx);
extern void riscv_split_doubleword_move (rtx, rtx);
extern const char *riscv_output_move (rtx, rtx);
extern const char *riscv_output_gpr_save (unsigned);
#ifdef RTX_CODE
extern void riscv_expand_int_scc (rtx, enum rtx_code, rtx, rtx);
extern void riscv_expand_float_scc (rtx, enum rtx_code, rtx, rtx);
extern void riscv_expand_conditional_branch (rtx, enum rtx_code, rtx, rtx);
#endif
extern rtx riscv_legitimize_call_address (rtx);
extern void riscv_set_return_address (rtx, rtx);
extern bool riscv_expand_block_move (rtx, rtx, rtx);
extern rtx riscv_return_addr (int, rtx);
extern HOST_WIDE_INT riscv_initial_elimination_offset (int, int);
extern void riscv_expand_prologue (void);
extern void riscv_expand_epilogue (bool);
extern bool riscv_can_use_return_insn (void);
extern rtx riscv_function_value (const_tree, const_tree, enum machine_mode);
extern unsigned int riscv_hard_regno_nregs (int, enum machine_mode);
/* Routines implemented in riscv-c.c. */
void riscv_cpu_cpp_builtins (cpp_reader *);
/* Routines implemented in riscv-builtins.c. */
extern void riscv_atomic_assign_expand_fenv (tree *, tree *, tree *);
extern rtx riscv_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
extern tree riscv_builtin_decl (unsigned int, bool);
extern void riscv_init_builtins (void);
#endif /* ! GCC_RISCV_PROTOS_H */
gcc/config/riscv/riscv.c 0 → 100644
This source diff could not be displayed because it is too large. You can view the blob instead.
gcc/config/riscv/riscv.opt 0 → 100644
; Options for the RISC-V port of the compiler
;
; Copyright (C) 2011-2017 Free Software Foundation, Inc.
;
; This file is part of GCC.
;
; GCC is free software; you can redistribute it and/or modify it under
; the terms of the GNU General Public License as published by the Free
; Software Foundation; either version 3, or (at your option) any later
; version.
;
; GCC is distributed in the hope that it will be useful, but WITHOUT
; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
; License for more details.
;
; You should have received a copy of the GNU General Public License
; along with GCC; see the file COPYING3. If not see
; <http://www.gnu.org/licenses/>.
HeaderInclude
config/riscv/riscv-opts.h
mbranch-cost=
Target RejectNegative Joined UInteger Var(riscv_branch_cost)
-mbranch-cost=N Set the cost of branches to roughly N instructions.
mplt
Target Report Var(TARGET_PLT) Init(1)
When generating -fpic code, allow the use of PLTs. Ignored for fno-pic.
mabi=
Target Report RejectNegative Joined Enum(abi_type) Var(riscv_abi) Init(ABI_ILP32)
Specify integer and floating-point calling convention.
Enum
Name(abi_type) Type(enum riscv_abi_type)
Supported ABIs (for use with the -mabi= option):
EnumValue
Enum(abi_type) String(ilp32) Value(ABI_ILP32)
EnumValue
Enum(abi_type) String(ilp32f) Value(ABI_ILP32F)
EnumValue
Enum(abi_type) String(ilp32d) Value(ABI_ILP32D)
EnumValue
Enum(abi_type) String(lp64) Value(ABI_LP64)
EnumValue
Enum(abi_type) String(lp64f) Value(ABI_LP64F)
EnumValue
Enum(abi_type) String(lp64d) Value(ABI_LP64D)
mfdiv
Target Report Mask(FDIV)
Use hardware floating-point divide and square root instructions.
mdiv
Target Report Mask(DIV)
Use hardware instructions for integer division.
march=
Target Report RejectNegative Joined
-march= Generate code for given RISC-V ISA (e.g. RV64IM). ISA strings must be
lower-case.
mtune=
Target RejectNegative Joined Var(riscv_tune_string)
-mtune=PROCESSOR Optimize the output for PROCESSOR.
msmall-data-limit=
Target Joined Separate UInteger Var(g_switch_value) Init(8)
-msmall-data-limit=N Put global and static data smaller than <number> bytes into a special section (on some targets).
msave-restore
Target Report Mask(SAVE_RESTORE)
Use smaller but slower prologue and epilogue code.
mcmodel=
Target Report RejectNegative Joined Enum(code_model) Var(riscv_cmodel) Init(TARGET_DEFAULT_CMODEL)
Specify the code model.
Enum
Name(code_model) Type(enum riscv_code_model)
Known code models (for use with the -mcmodel= option):
EnumValue
Enum(code_model) String(medlow) Value(CM_MEDLOW)
EnumValue
Enum(code_model) String(medany) Value(CM_MEDANY)
mexplicit-relocs
Target Report Mask(EXPLICIT_RELOCS)
Use %reloc() operators, rather than assembly macros, to load addresses.
Mask(64BIT)
Mask(MUL)
Mask(ATOMIC)
Mask(HARD_FLOAT)
Mask(DOUBLE_FLOAT)
Mask(RVC)
gcc/config/riscv/sync.md 0 → 100644
;; Machine description for RISC-V atomic operations.
;; Copyright (C) 2011-2017 Free Software Foundation, Inc.
;; Contributed by Andrew Waterman (andrew@sifive.com).
;; Based on MIPS target for GNU compiler.
;; This file is part of GCC.
;; GCC is free software; you can redistribute it and/or modify
;; it under the terms of the GNU General Public License as published by
;; the Free Software Foundation; either version 3, or (at your option)
;; any later version.
;; GCC is distributed in the hope that it will be useful,
;; but WITHOUT ANY WARRANTY; without even the implied warranty of
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
;; GNU General Public License for more details.
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.
(define_c_enum "unspec" [
UNSPEC_COMPARE_AND_SWAP
UNSPEC_SYNC_OLD_OP
UNSPEC_SYNC_EXCHANGE
UNSPEC_ATOMIC_STORE
UNSPEC_MEMORY_BARRIER
])
(define_code_iterator any_atomic [plus ior xor and])
(define_code_attr atomic_optab
[(plus "add") (ior "or") (xor "xor") (and "and")])
;; Memory barriers.
(define_expand "mem_thread_fence"
[(match_operand:SI 0 "const_int_operand" "")] ;; model
""
{
if (INTVAL (operands[0]) != MEMMODEL_RELAXED)
{
rtx mem = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
MEM_VOLATILE_P (mem) = 1;
emit_insn (gen_mem_thread_fence_1 (mem, operands[0]));
}
DONE;
})
;; Until the RISC-V memory model (hence its mapping from C++) is finalized,
;; conservatively emit a full FENCE.
(define_insn "mem_thread_fence_1"
[(set (match_operand:BLK 0 "" "")
(unspec:BLK [(match_dup 0)] UNSPEC_MEMORY_BARRIER))
(match_operand:SI 1 "const_int_operand" "")] ;; model
""
"fence\trw,rw")
;; Atomic memory operations.
;; Implement atomic stores with amoswap. Fall back to fences for atomic loads.
(define_insn "atomic_store<mode>"
[(set (match_operand:GPR 0 "memory_operand" "=A")
(unspec_volatile:GPR
[(match_operand:GPR 1 "reg_or_0_operand" "rJ")
(match_operand:SI 2 "const_int_operand")] ;; model
UNSPEC_ATOMIC_STORE))]
"TARGET_ATOMIC"
"%F2amoswap.<amo>%A2 zero,%z1,%0"
[(set (attr "length") (const_int 8))])
(define_insn "atomic_<atomic_optab><mode>"
[(set (match_operand:GPR 0 "memory_operand" "+A")
(unspec_volatile:GPR
[(any_atomic:GPR (match_dup 0)
(match_operand:GPR 1 "reg_or_0_operand" "rJ"))
(match_operand:SI 2 "const_int_operand")] ;; model
UNSPEC_SYNC_OLD_OP))]
"TARGET_ATOMIC"
"%F2amo<insn>.<amo>%A2 zero,%z1,%0"
[(set (attr "length") (const_int 8))])
(define_insn "atomic_fetch_<atomic_optab><mode>"
[(set (match_operand:GPR 0 "register_operand" "=&r")
(match_operand:GPR 1 "memory_operand" "+A"))
(set (match_dup 1)
(unspec_volatile:GPR
[(any_atomic:GPR (match_dup 1)
(match_operand:GPR 2 "reg_or_0_operand" "rJ"))
(match_operand:SI 3 "const_int_operand")] ;; model
UNSPEC_SYNC_OLD_OP))]
"TARGET_ATOMIC"
"%F3amo<insn>.<amo>%A3 %0,%z2,%1"
[(set (attr "length") (const_int 8))])
(define_insn "atomic_exchange<mode>"
[(set (match_operand:GPR 0 "register_operand" "=&r")
(unspec_volatile:GPR
[(match_operand:GPR 1 "memory_operand" "+A")
(match_operand:SI 3 "const_int_operand")] ;; model
UNSPEC_SYNC_EXCHANGE))
(set (match_dup 1)
(match_operand:GPR 2 "register_operand" "0"))]
"TARGET_ATOMIC"
"%F3amoswap.<amo>%A3 %0,%z2,%1"
[(set (attr "length") (const_int 8))])
(define_insn "atomic_cas_value_strong<mode>"
[(set (match_operand:GPR 0 "register_operand" "=&r")
(match_operand:GPR 1 "memory_operand" "+A"))
(set (match_dup 1)
(unspec_volatile:GPR [(match_operand:GPR 2 "reg_or_0_operand" "rJ")
(match_operand:GPR 3 "reg_or_0_operand" "rJ")
(match_operand:SI 4 "const_int_operand") ;; mod_s
(match_operand:SI 5 "const_int_operand")] ;; mod_f
UNSPEC_COMPARE_AND_SWAP))
(clobber (match_scratch:GPR 6 "=&r"))]
"TARGET_ATOMIC"
"%F5 1: lr.<amo>%A5 %0,%1; bne %0,%z2,1f; sc.<amo>%A4 %6,%z3,%1; bnez %6,1b; 1:"
[(set (attr "length") (const_int 20))])
(define_expand "atomic_compare_and_swap<mode>"
[(match_operand:SI 0 "register_operand" "") ;; bool output
(match_operand:GPR 1 "register_operand" "") ;; val output
(match_operand:GPR 2 "memory_operand" "") ;; memory
(match_operand:GPR 3 "reg_or_0_operand" "") ;; expected value
(match_operand:GPR 4 "reg_or_0_operand" "") ;; desired value
(match_operand:SI 5 "const_int_operand" "") ;; is_weak
(match_operand:SI 6 "const_int_operand" "") ;; mod_s
(match_operand:SI 7 "const_int_operand" "")] ;; mod_f
"TARGET_ATOMIC"
{
emit_insn (gen_atomic_cas_value_strong<mode> (operands[1], operands[2],
operands[3], operands[4],
operands[6], operands[7]));
rtx compare = operands[1];
if (operands[3] != const0_rtx)
{
rtx difference = gen_rtx_MINUS (<MODE>mode, operands[1], operands[3]);
compare = gen_reg_rtx (<MODE>mode);
emit_insn (gen_rtx_SET (compare, difference));
}
if (word_mode != <MODE>mode)
{
rtx reg = gen_reg_rtx (word_mode);
emit_insn (gen_rtx_SET (reg, gen_rtx_SIGN_EXTEND (word_mode, compare)));
compare = reg;
}
emit_insn (gen_rtx_SET (operands[0], gen_rtx_EQ (SImode, compare, const0_rtx)));
DONE;
})
(define_expand "atomic_test_and_set"
[(match_operand:QI 0 "register_operand" "") ;; bool output
(match_operand:QI 1 "memory_operand" "+A") ;; memory
(match_operand:SI 2 "const_int_operand" "")] ;; model
"TARGET_ATOMIC"
{
/* We have no QImode atomics, so use the address LSBs to form a mask,
then use an aligned SImode atomic. */
rtx result = operands[0];
rtx mem = operands[1];
rtx model = operands[2];
rtx addr = force_reg (Pmode, XEXP (mem, 0));
rtx aligned_addr = gen_reg_rtx (Pmode);
emit_move_insn (aligned_addr, gen_rtx_AND (Pmode, addr, GEN_INT (-4)));
rtx aligned_mem = change_address (mem, SImode, aligned_addr);
set_mem_alias_set (aligned_mem, 0);
rtx offset = gen_reg_rtx (SImode);
emit_move_insn (offset, gen_rtx_AND (SImode, gen_lowpart (SImode, addr),
GEN_INT (3)));
rtx tmp = gen_reg_rtx (SImode);
emit_move_insn (tmp, GEN_INT (1));
rtx shmt = gen_reg_rtx (SImode);
emit_move_insn (shmt, gen_rtx_ASHIFT (SImode, offset, GEN_INT (3)));
rtx word = gen_reg_rtx (SImode);
emit_move_insn (word, gen_rtx_ASHIFT (SImode, tmp, shmt));
tmp = gen_reg_rtx (SImode);
emit_insn (gen_atomic_fetch_orsi (tmp, aligned_mem, word, model));
emit_move_insn (gen_lowpart (SImode, result),
gen_rtx_LSHIFTRT (SImode, tmp,
gen_lowpart (SImode, shmt)));
DONE;
})
gcc/config/riscv/t-elf-multilib 0 → 100644
# This file was generated by multilib-generator with the command:
# ./multilib-generator rv32i-ilp32--c rv32im-ilp32--c rv32iac-ilp32-- rv32imac-ilp32-- rv32imafc-ilp32f-rv32imafdc- rv64imac-lp64-- rv64imafdc-lp64d--
MULTILIB_OPTIONS = march=rv32i/march=rv32ic/march=rv32im/march=rv32imc/march=rv32iac/march=rv32imac/march=rv32imafc/march=rv32imafdc/march=rv32gc/march=rv64imac/march=rv64imafdc/march=rv64gc mabi=ilp32/mabi=ilp32f/mabi=lp64/mabi=lp64d
MULTILIB_DIRNAMES = rv32i \
rv32ic \
rv32im \
rv32imc \
rv32iac \
rv32imac \
rv32imafc \
rv32imafdc \
rv32gc \
rv64imac \
rv64imafdc \
rv64gc ilp32 \
ilp32f \
lp64 \
lp64d
MULTILIB_REQUIRED = march=rv32i/mabi=ilp32 \
march=rv32im/mabi=ilp32 \
march=rv32iac/mabi=ilp32 \
march=rv32imac/mabi=ilp32 \
march=rv32imafc/mabi=ilp32f \
march=rv64imac/mabi=lp64 \
march=rv64imafdc/mabi=lp64d
MULTILIB_REUSE = march.rv32i/mabi.ilp32=march.rv32ic/mabi.ilp32 \
march.rv32im/mabi.ilp32=march.rv32imc/mabi.ilp32 \
march.rv32imafc/mabi.ilp32f=march.rv32imafdc/mabi.ilp32f \
march.rv32imafc/mabi.ilp32f=march.rv32gc/mabi.ilp32f \
march.rv64imafdc/mabi.lp64d=march.rv64gc/mabi.lp64d
gcc/config/riscv/t-linux 0 → 100644
# Only XLEN and ABI affect Linux multilib dir names, e.g. /lib32/ilp32d/
MULTILIB_DIRNAMES := $(patsubst rv32%,lib32,$(patsubst rv64%,lib64,$(MULTILIB_DIRNAMES)))
MULTILIB_OSDIRNAMES := $(patsubst lib%,../lib%,$(MULTILIB_DIRNAMES))
gcc/config/riscv/t-linux-multilib 0 → 100644
# This file was generated by multilib-generator with the command:
# ./multilib-generator rv32imac-ilp32-rv32ima,rv32imaf,rv32imafd,rv32imafc,rv32imafdc- rv32imafdc-ilp32d-rv32imafd- rv64imac-lp64-rv64ima,rv64imaf,rv64imafd,rv64imafc,rv64imafdc- rv64imafdc-lp64d-rv64imafd-
MULTILIB_OPTIONS = march=rv32imac/march=rv32ima/march=rv32imaf/march=rv32imafd/march=rv32imafc/march=rv32imafdc/march=rv32g/march=rv32gc/march=rv64imac/march=rv64ima/march=rv64imaf/march=rv64imafd/march=rv64imafc/march=rv64imafdc/march=rv64g/march=rv64gc mabi=ilp32/mabi=ilp32d/mabi=lp64/mabi=lp64d
MULTILIB_DIRNAMES = rv32imac \
rv32ima \
rv32imaf \
rv32imafd \
rv32imafc \
rv32imafdc \
rv32g \
rv32gc \
rv64imac \
rv64ima \
rv64imaf \
rv64imafd \
rv64imafc \
rv64imafdc \
rv64g \
rv64gc ilp32 \
ilp32d \
lp64 \
lp64d
MULTILIB_REQUIRED = march=rv32imac/mabi=ilp32 \
march=rv32imafdc/mabi=ilp32d \
march=rv64imac/mabi=lp64 \
march=rv64imafdc/mabi=lp64d
MULTILIB_REUSE = march.rv32imac/mabi.ilp32=march.rv32ima/mabi.ilp32 \
march.rv32imac/mabi.ilp32=march.rv32imaf/mabi.ilp32 \
march.rv32imac/mabi.ilp32=march.rv32imafd/mabi.ilp32 \
march.rv32imac/mabi.ilp32=march.rv32imafc/mabi.ilp32 \
march.rv32imac/mabi.ilp32=march.rv32imafdc/mabi.ilp32 \
march.rv32imac/mabi.ilp32=march.rv32g/mabi.ilp32 \
march.rv32imac/mabi.ilp32=march.rv32gc/mabi.ilp32 \
march.rv32imafdc/mabi.ilp32d=march.rv32imafd/mabi.ilp32d \
march.rv32imafdc/mabi.ilp32d=march.rv32gc/mabi.ilp32d \
march.rv32imafdc/mabi.ilp32d=march.rv32g/mabi.ilp32d \
march.rv64imac/mabi.lp64=march.rv64ima/mabi.lp64 \
march.rv64imac/mabi.lp64=march.rv64imaf/mabi.lp64 \
march.rv64imac/mabi.lp64=march.rv64imafd/mabi.lp64 \
march.rv64imac/mabi.lp64=march.rv64imafc/mabi.lp64 \
march.rv64imac/mabi.lp64=march.rv64imafdc/mabi.lp64 \
march.rv64imac/mabi.lp64=march.rv64g/mabi.lp64 \
march.rv64imac/mabi.lp64=march.rv64gc/mabi.lp64 \
march.rv64imafdc/mabi.lp64d=march.rv64imafd/mabi.lp64d \
march.rv64imafdc/mabi.lp64d=march.rv64gc/mabi.lp64d \
march.rv64imafdc/mabi.lp64d=march.rv64g/mabi.lp64d
gcc/config/riscv/t-riscv 0 → 100644
riscv-builtins.o: $(srcdir)/config/riscv/riscv-builtins.c $(CONFIG_H) \
$(SYSTEM_H) coretypes.h $(TM_H) $(RTL_H) $(TREE_H) $(RECOG_H) langhooks.h \
$(DIAGNOSTIC_CORE_H) $(OPTABS_H) $(srcdir)/config/riscv/riscv-ftypes.def \
$(srcdir)/config/riscv/riscv-modes.def
$(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) \
$(srcdir)/config/riscv/riscv-builtins.c
riscv-c.o: $(srcdir)/config/riscv/riscv-c.c $(CONFIG_H) $(SYSTEM_H) \
coretypes.h $(TM_H) $(TREE_H) output.h $(C_COMMON_H) $(TARGET_H)
$(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) \
$(srcdir)/config/riscv/riscv-c.c
gcc/configure.ac
......@@ -3393,6 +3393,17 @@ x3: .space 4
tls_first_minor=14
tls_as_opt="-a32 --fatal-warnings"
;;
riscv*-*-*)
conftest_s='
.section .tdata,"awT",@progbits
x: .word 2
.text
la.tls.gd a0,x
call __tls_get_addr'
tls_first_major=2
tls_first_minor=21
tls_as_opt='--fatal-warnings'
;;
s390-*-*)
conftest_s='
.section ".tdata","awT",@progbits
......@@ -4744,8 +4755,8 @@ esac
# version to the per-target configury.
case "$cpu_type" in
aarch64 | alpha | arm | avr | bfin | cris | i386 | m32c | m68k | microblaze \
| mips | nios2 | pa | rs6000 | score | sparc | spu | tilegx | tilepro \
| visium | xstormy16 | xtensa)
| mips | nios2 | pa | riscv | rs6000 | score | sparc | spu | tilegx \
| tilepro | visium | xstormy16 | xtensa)
insn="nop"
;;
ia64 | s390)
......
gcc/doc/contrib.texi
......@@ -173,6 +173,10 @@ Denis Chertykov for contributing and maintaining the AVR port, the first GCC por
for an 8-bit architecture.
@item
Kito Cheng for his work on the RISC-V port, including bringing up the test
suite and maintenance.
@item
Scott Christley for his Objective-C contributions.
@item
......@@ -217,6 +221,9 @@ Paul Dale for his work to add uClinux platform support to the
m68k backend.
@item
Palmer Dabbelt for his work maintaining the RISC-V port.
@item
Dario Dariol contributed the four varieties of sample programs
that print a copy of their source.
......@@ -1035,6 +1042,9 @@ associated configure steps.
Todd Vierling for contributions for NetBSD ports.
@item
Andrew Waterman for contributing the RISC-V port, as well as maintaining it.
@item
Jonathan Wakely for contributing libstdc++ Doxygen notes and XHTML
guidance.
......
gcc/doc/install.texi
......@@ -4297,6 +4297,36 @@ This configuration is intended for embedded systems.
@html
<hr />
@end html
@anchor{riscv32-x-elf}
@heading riscv32-*-elf
The RISC-V RV32 instruction set.
This configuration is intended for embedded systems.
@html
<hr />
@end html
@anchor{riscv64-x-elf}
@heading riscv64-*-elf
The RISC-V RV64 instruction set.
This configuration is intended for embedded systems.
@html
<hr />
@end html
@anchor{riscv32-x-linux}
@heading riscv32-*-linux
The RISC-V RV32 instruction set running GNU/Linux.
@html
<hr />
@end html
@anchor{riscv64-x-linux}
@heading riscv64-*-linux
The RISC-V RV64 instruction set running GNU/Linux.
@html
<hr />
@end html
@anchor{rx-x-elf}
@heading rx-*-elf
The Renesas RX processor. See
......
gcc/doc/invoke.texi
......@@ -1026,6 +1026,20 @@ See RS/6000 and PowerPC Options.
-mstack-protector-guard-offset=@var{offset} @gol
-mlra -mno-lra}
@emph{RISC-V Options}
@gccoptlist{-mbranch-cost=@var{N-instruction} @gol
-mmemcpy -mno-memcpy @gol
-mplt -mno-plt @gol
-mabi=@var{ABI-string} @gol
-mfdiv -mno-fdiv @gol
-mdiv -mno-div @gol
-march=@var{ISA-string} @gol
-mtune=@var{processor-string} @gol
-msmall-data-limit=@var{N-bytes} @gol
-msave-restore -mno-save-restore @gol
-mcmodel=@var{code-model} @gol
-mexplicit-relocs -mno-explicit-relocs @gol}
@emph{RX Options}
@gccoptlist{-m64bit-doubles -m32bit-doubles -fpu -nofpu@gol
-mcpu=@gol
......@@ -13744,6 +13758,7 @@ platform.
* PowerPC Options::
* RL78 Options::
* RS/6000 and PowerPC Options::
* RISC-V Options::
* RX Options::
* S/390 and zSeries Options::
* Score Options::
......@@ -22137,6 +22152,70 @@ offset from that base register. The default for those is as specified in the
relevant ABI.
@end table
@node RISC-V Options
@subsection RISC-V Options
@cindex RISC-V Options
These command-line options are defined for RISC-V targets:
@table @gcctabopt
@item -mbranch-cost=@var{n}
@opindex mbranch-cost
Set the cost of branches to roughly @var{n} instructions.
@item -mmemcpy
@itemx -mno-memcpy
@opindex mmemcpy
Don't optimize block moves.
@item -mplt
@itemx -mno-plt
@opindex plt
When generating PIC code, allow the use of PLTs. Ignored for non-PIC.
@item -mabi=@var{ABI-string}
@opindex mabi
Specify integer and floating-point calling convention. This defaults to the
natural calling convention: e.g.@ LP64 for RV64I, ILP32 for RV32I, LP64D for
RV64G.
@item -mfdiv
@itemx -mno-fdiv
@opindex mfdiv
Use hardware floating-point divide and square root instructions. This requires
the F or D extensions for floating-point registers.
@item -mdiv
@itemx -mno-div
@opindex mdiv
Use hardware instructions for integer division. This requires the M extension.
@item -march=@var{ISA-string}
@opindex march
Generate code for given RISC-V ISA (e.g.@ @samp{rv64im}). ISA strings must be
lower-case. Examples include @samp{rv64i}, @samp{rv32g}, and @samp{rv32imaf}.
@item -mtune=@var{processor-string}
@opindex mtune
Optimize the output for the given processor, specified by microarchitecture
name.
@item -msmall-data-limit=@var{n}
@opindex msmall-data-limit
Put global and static data smaller than @var{n} bytes into a special section
(on some targets).
@item -msave-restore
@itemx -mno-save-restore
@opindex msave-restore
Use smaller but slower prologue and epilogue code.
@item -mcmodel=@var{code-model}
@opindex mcmodel
Specify the code model.
@end table
@node RX Options
@subsection RX Options
@cindex RX Options
......
gcc/doc/md.texi
......@@ -3362,6 +3362,26 @@ The @code{X} register.
@end table
@item RISC-V---@file{config/riscv/constraints.md}
@table @code
@item f
A floating-point register (if availiable).
@item I
An I-type 12-bit signed immediate.
@item J
Integer zero.
@item K
A 5-bit unsigned immediate for CSR access instructions.
@item A
An address that is held in a general-purpose register.
@end table
@item RX---@file{config/rx/constraints.md}
@table @code
@item Q
......
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