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riscv-gcc-1
Commit e87afe54 by Richard Earnshaw Committed by Richard Earnshaw
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[arm] Add default FPUs for CPUs. 


This patch adds the default CPUs for each cpu and provides options for
changing the FPU variant when appropriate.

It turns out to be easier to describe removal options using general
mask operations that disable a concept rather than specific bits.
Sometimes the helper definitions for enabling a feature are not excat
duals when it comes to disabling them - for example, +simd forcibly
turns on double-precision capabilities in the FPU, but disabling just
simd (+nosimd) should not forcibly disable that.

	* config/arm/arm-isa.h (ISA_ALL_FPU_INTERNAL): Renamed from ISA_ALL_FPU.
	(ISA_ALL_CRYPTO): New macro.
	(ISA_ALL_SIMD): New macro
	(ISA_ALL_FP): New macro.
	* config/arm/arm.c (fpu_bitlist): Update initializer.
	* config/arm/arm-cpus.in: Use new ISA_ALL macros to disable crypto,
	simd or fp.
	(arm9e): Add fpu.  Add option for nofp
	(arm946e-s, arm966e-s, arm968e-s, arm10e, arm1020e, arm1022e): Likewise.
	(arm926ej-s, arm1026ej-s): Likewise.
	(generic-armv7-a): Add fpu.  Add options for simd, vfpv3, vfpv3-d16,
	vfpv3-fp16, vfpv3-d16-fp16, vfpv4, vfpv4-d16, neon, neon-vfp3,
	neon-fp16, neon-vfpv4, nofp and nosimd.
	(cortex-a5, cortex-a7): Add fpu.  Add options for nosimd and nofp.
	(cortex-a8): Add fpu.  Add option for nofp.
	(cortex-a9): Add fpu.  Add options for nosimd and nofp.
	(cortex-a12, cortex-a15, cortex-a17): Add fpu.  Add option for nofp.
	(cortex-r4f): Add fpu.
	(cortex-r5): Add fpu.  Add options for nofp.dp and nofp.
	(cortex-r7): Use idiv option from architecture.  Add fpu.  Add option
	for nofp.
	(cortex-r8): Likewise.
	(cortex-m4): Add fpu.  Add option for nofp.
	(cortex-a15.cortex-a7): Add fpu.  Add option for nofp.
	(cortex-a17.cortex-a7): Likewise.
	(cortex-a32): Add fpu.  Add options for crypto and nofp.
	(cortex-a35, cortex-a53): Likewise.
	(cortex-a57): Add fpu.  Add option for crypto.
	(cortex-a72, cortex-a73): Likewise.
	(exynos-m1): Likewise.
	(cortex-a57.cortex-a53, cortex-a72.cortex-a53): Likewise.
	(cortex-a73.cortex-a35, cortex-a73.cortex-a53): Likewise.
	(cortex-m33): Add fpu.  Add option for nofp.
	* config/arm/arm-cpu-cdata.h: Regenerated
	* config/arm/arm-cpu-data.h: Regenerated.

From-SVN: r249284
parent 76d7d533
Showing with 94 additions and 8 deletions
gcc/ChangeLog
2017-06-16 Richard Earnshaw <rearnsha@arm.com>
* config/arm/arm-isa.h (ISA_ALL_FPU_INTERNAL): Renamed from ISA_ALL_FPU.
(ISA_ALL_CRYPTO): New macro.
(ISA_ALL_SIMD): New macro
(ISA_ALL_FP): New macro.
* config/arm/arm.c (fpu_bitlist): Update initializer.
* config/arm/arm-cpus.in: Use new ISA_ALL macros to disable crypto,
simd or fp.
(arm9e): Add fpu. Add option for nofp
(arm946e-s, arm966e-s, arm968e-s, arm10e, arm1020e, arm1022e): Likewise.
(arm926ej-s, arm1026ej-s): Likewise.
(generic-armv7-a): Add fpu. Add options for simd, vfpv3, vfpv3-d16,
vfpv3-fp16, vfpv3-d16-fp16, vfpv4, vfpv4-d16, neon, neon-vfp3,
neon-fp16, neon-vfpv4, nofp and nosimd.
(cortex-a5, cortex-a7): Add fpu. Add options for nosimd and nofp.
(cortex-a8): Add fpu. Add option for nofp.
(cortex-a9): Add fpu. Add options for nosimd and nofp.
(cortex-a12, cortex-a15, cortex-a17): Add fpu. Add option for nofp.
(cortex-r4f): Add fpu.
(cortex-r5): Add fpu. Add options for nofp.dp and nofp.
(cortex-r7): Use idiv option from architecture. Add fpu. Add option
for nofp.
(cortex-r8): Likewise.
(cortex-m4): Add fpu. Add option for nofp.
(cortex-a15.cortex-a7): Add fpu. Add option for nofp.
(cortex-a17.cortex-a7): Likewise.
(cortex-a32): Add fpu. Add options for crypto and nofp.
(cortex-a35, cortex-a53): Likewise.
(cortex-a57): Add fpu. Add option for crypto.
(cortex-a72, cortex-a73): Likewise.
(exynos-m1): Likewise.
(cortex-a57.cortex-a53, cortex-a72.cortex-a53): Likewise.
(cortex-a73.cortex-a35, cortex-a73.cortex-a53): Likewise.
(cortex-m33): Add fpu. Add option for nofp.
* config/arm/arm-cpu-cdata.h: Regenerated
* config/arm/arm-cpu-data.h: Regenerated.
2017-06-16 Richard Earnshaw <rearnsha@arm.com>
* arm-cpus.in (armv5e): Add options fp, vfpv2 and nofp.
(armv5te, armv5tej): Likewise.
(armv6, armv6j, armv6k, armv6z, armv6kz, armv6zk, armv6t2): Likewise.
......
gcc/config/arm/arm-cpu-cdata.h
......@@ -341,6 +341,7 @@ static const struct arm_arch_core_flag arm_arch_core_flags[] =
"arm9e",
{
ISA_ARMv5te,
ISA_VFPv2,ISA_FP_DBL,
isa_nobit
},
},
......@@ -348,6 +349,7 @@ static const struct arm_arch_core_flag arm_arch_core_flags[] =
"arm946e-s",
{
ISA_ARMv5te,
ISA_VFPv2,ISA_FP_DBL,
isa_nobit
},
},
......@@ -355,6 +357,7 @@ static const struct arm_arch_core_flag arm_arch_core_flags[] =
"arm966e-s",
{
ISA_ARMv5te,
ISA_VFPv2,ISA_FP_DBL,
isa_nobit
},
},
......@@ -362,6 +365,7 @@ static const struct arm_arch_core_flag arm_arch_core_flags[] =
"arm968e-s",
{
ISA_ARMv5te,
ISA_VFPv2,ISA_FP_DBL,
isa_nobit
},
},
......@@ -369,6 +373,7 @@ static const struct arm_arch_core_flag arm_arch_core_flags[] =
"arm10e",
{
ISA_ARMv5te,
ISA_VFPv2,ISA_FP_DBL,
isa_nobit
},
},
......@@ -376,6 +381,7 @@ static const struct arm_arch_core_flag arm_arch_core_flags[] =
"arm1020e",
{
ISA_ARMv5te,
ISA_VFPv2,ISA_FP_DBL,
isa_nobit
},
},
......@@ -383,6 +389,7 @@ static const struct arm_arch_core_flag arm_arch_core_flags[] =
"arm1022e",
{
ISA_ARMv5te,
ISA_VFPv2,ISA_FP_DBL,
isa_nobit
},
},
......@@ -440,6 +447,7 @@ static const struct arm_arch_core_flag arm_arch_core_flags[] =
"arm926ej-s",
{
ISA_ARMv5tej,
ISA_VFPv2,ISA_FP_DBL,
isa_nobit
},
},
......@@ -447,6 +455,7 @@ static const struct arm_arch_core_flag arm_arch_core_flags[] =
"arm1026ej-s",
{
ISA_ARMv5tej,
ISA_VFPv2,ISA_FP_DBL,
isa_nobit
},
},
......@@ -556,6 +565,7 @@ static const struct arm_arch_core_flag arm_arch_core_flags[] =
"generic-armv7-a",
{
ISA_ARMv7a,
ISA_VFPv3,ISA_FP_DBL,
isa_nobit
},
},
......@@ -563,6 +573,7 @@ static const struct arm_arch_core_flag arm_arch_core_flags[] =
"cortex-a5",
{
ISA_ARMv7a,
ISA_VFPv3,ISA_NEON,isa_bit_fp16conv,
isa_nobit
},
},
......@@ -570,6 +581,7 @@ static const struct arm_arch_core_flag arm_arch_core_flags[] =
"cortex-a7",
{
ISA_ARMv7ve,
ISA_VFPv4,ISA_NEON,
isa_nobit
},
},
......@@ -585,7 +597,7 @@ static const struct arm_arch_core_flag arm_arch_core_flags[] =
"cortex-a9",
{
ISA_ARMv7a,
ISA_VFPv3,ISA_NEON,
ISA_VFPv3,ISA_NEON,isa_bit_fp16conv,
isa_nobit
},
},
......@@ -593,6 +605,7 @@ static const struct arm_arch_core_flag arm_arch_core_flags[] =
"cortex-a12",
{
ISA_ARMv7ve,
ISA_VFPv4,ISA_NEON,
isa_nobit
},
},
......@@ -600,6 +613,7 @@ static const struct arm_arch_core_flag arm_arch_core_flags[] =
"cortex-a15",
{
ISA_ARMv7ve,
ISA_VFPv4,ISA_NEON,
isa_nobit
},
},
......@@ -607,6 +621,7 @@ static const struct arm_arch_core_flag arm_arch_core_flags[] =
"cortex-a17",
{
ISA_ARMv7ve,
ISA_VFPv4,ISA_NEON,
isa_nobit
},
},
......@@ -621,6 +636,7 @@ static const struct arm_arch_core_flag arm_arch_core_flags[] =
"cortex-r4f",
{
ISA_ARMv7r,
ISA_VFPv3,ISA_FP_DBL,
isa_nobit
},
},
......@@ -628,7 +644,7 @@ static const struct arm_arch_core_flag arm_arch_core_flags[] =
"cortex-r5",
{
ISA_ARMv7r,
isa_bit_adiv,
ISA_VFPv3,ISA_FP_DBL,
isa_nobit
},
},
......@@ -636,7 +652,7 @@ static const struct arm_arch_core_flag arm_arch_core_flags[] =
"cortex-r7",
{
ISA_ARMv7r,
isa_bit_adiv,
ISA_VFPv3,ISA_FP_DBL,
isa_nobit
},
},
......@@ -644,7 +660,7 @@ static const struct arm_arch_core_flag arm_arch_core_flags[] =
"cortex-r8",
{
ISA_ARMv7r,
isa_bit_adiv,
ISA_VFPv3,ISA_FP_DBL,
isa_nobit
},
},
......@@ -652,6 +668,7 @@ static const struct arm_arch_core_flag arm_arch_core_flags[] =
"cortex-m7",
{
ISA_ARMv7em,
ISA_FPv5,ISA_FP_DBL,
isa_quirk_no_volatile_ce,
isa_nobit
},
......@@ -660,6 +677,7 @@ static const struct arm_arch_core_flag arm_arch_core_flags[] =
"cortex-m4",
{
ISA_ARMv7em,
ISA_VFPv4,
isa_nobit
},
},
......@@ -682,6 +700,7 @@ static const struct arm_arch_core_flag arm_arch_core_flags[] =
"cortex-a15.cortex-a7",
{
ISA_ARMv7ve,
ISA_VFPv4,ISA_NEON,
isa_nobit
},
},
......@@ -689,6 +708,7 @@ static const struct arm_arch_core_flag arm_arch_core_flags[] =
"cortex-a17.cortex-a7",
{
ISA_ARMv7ve,
ISA_VFPv4,ISA_NEON,
isa_nobit
},
},
......@@ -696,6 +716,7 @@ static const struct arm_arch_core_flag arm_arch_core_flags[] =
"cortex-a32",
{
ISA_ARMv8a,
ISA_FP_ARMv8,ISA_NEON,
isa_nobit
},
},
......@@ -703,6 +724,7 @@ static const struct arm_arch_core_flag arm_arch_core_flags[] =
"cortex-a35",
{
ISA_ARMv8a,
ISA_FP_ARMv8,ISA_NEON,
isa_nobit
},
},
......@@ -710,6 +732,7 @@ static const struct arm_arch_core_flag arm_arch_core_flags[] =
"cortex-a53",
{
ISA_ARMv8a,
ISA_FP_ARMv8,ISA_NEON,
isa_nobit
},
},
......@@ -717,6 +740,7 @@ static const struct arm_arch_core_flag arm_arch_core_flags[] =
"cortex-a57",
{
ISA_ARMv8a,
ISA_FP_ARMv8,ISA_NEON,
isa_nobit
},
},
......@@ -724,6 +748,7 @@ static const struct arm_arch_core_flag arm_arch_core_flags[] =
"cortex-a72",
{
ISA_ARMv8a,
ISA_FP_ARMv8,ISA_NEON,
isa_nobit
},
},
......@@ -731,6 +756,7 @@ static const struct arm_arch_core_flag arm_arch_core_flags[] =
"cortex-a73",
{
ISA_ARMv8a,
ISA_FP_ARMv8,ISA_NEON,
isa_nobit
},
},
......@@ -738,6 +764,7 @@ static const struct arm_arch_core_flag arm_arch_core_flags[] =
"exynos-m1",
{
ISA_ARMv8a,
ISA_FP_ARMv8,ISA_NEON,
isa_nobit
},
},
......@@ -745,6 +772,7 @@ static const struct arm_arch_core_flag arm_arch_core_flags[] =
"xgene1",
{
ISA_ARMv8a,
ISA_FP_ARMv8,ISA_NEON,
isa_nobit
},
},
......@@ -752,6 +780,7 @@ static const struct arm_arch_core_flag arm_arch_core_flags[] =
"cortex-a57.cortex-a53",
{
ISA_ARMv8a,
ISA_FP_ARMv8,ISA_NEON,
isa_nobit
},
},
......@@ -759,6 +788,7 @@ static const struct arm_arch_core_flag arm_arch_core_flags[] =
"cortex-a72.cortex-a53",
{
ISA_ARMv8a,
ISA_FP_ARMv8,ISA_NEON,
isa_nobit
},
},
......@@ -766,6 +796,7 @@ static const struct arm_arch_core_flag arm_arch_core_flags[] =
"cortex-a73.cortex-a35",
{
ISA_ARMv8a,
ISA_FP_ARMv8,ISA_NEON,
isa_nobit
},
},
......@@ -773,6 +804,7 @@ static const struct arm_arch_core_flag arm_arch_core_flags[] =
"cortex-a73.cortex-a53",
{
ISA_ARMv8a,
ISA_FP_ARMv8,ISA_NEON,
isa_nobit
},
},
......@@ -787,6 +819,7 @@ static const struct arm_arch_core_flag arm_arch_core_flags[] =
"cortex-m33",
{
ISA_ARMv8m_main,
ISA_FPv5,
isa_nobit
},
},
......
gcc/config/arm/arm-isa.h
......@@ -127,11 +127,25 @@ enum isa_feature
#define ISA_ARMv8m_base ISA_ARMv6m, isa_bit_ARMv8, isa_bit_cmse, isa_bit_tdiv
#define ISA_ARMv8m_main ISA_ARMv7m, isa_bit_ARMv8, isa_bit_cmse
/* List of all cryptographic extensions to stripout if crypto is
disabled. Currently, that's trivial, but we define it anyway for
consistency with the SIMD and FP disable lists. */
#define ISA_ALL_CRYPTO isa_bit_crypto
/* List of all SIMD bits to strip out if SIMD is disabled. This does
strip off 32 D-registers, but does not remove support for
double-precision FP. */
#define ISA_ALL_SIMD isa_bit_fp_d32, isa_bit_neon, ISA_ALL_CRYPTO
/* List of all FPU bits to strip out if -mfpu is used to override the
default. isa_bit_fp16 is deliberately missing from this list. */
#define ISA_ALL_FPU isa_bit_VFPv2, isa_bit_VFPv3, isa_bit_VFPv4, \
isa_bit_FPv5, isa_bit_FP_ARMv8, isa_bit_neon, isa_bit_fp16conv, \
isa_bit_fp_dbl, isa_bit_fp_d32, isa_bit_crypto
#define ISA_ALL_FPU_INTERNAL \
isa_bit_VFPv2, isa_bit_VFPv3, isa_bit_VFPv4, isa_bit_FPv5, \
isa_bit_FP_ARMv8, isa_bit_fp16conv, isa_bit_fp_dbl, ISA_ALL_SIMD
/* Similarly, but including fp16 and other extensions that aren't part of
-mfpu support. */
#define ISA_ALL_FP isa_bit_fp16, ISA_ALL_FPU_INTERNAL
/* Useful combinations. */
#define ISA_VFPv2 isa_bit_VFPv2
......
gcc/config/arm/arm.c
......@@ -3418,7 +3418,8 @@ arm_configure_build_target (struct arm_build_target *target,
static void
arm_option_override (void)
{
static const enum isa_feature fpu_bitlist[] = { ISA_ALL_FPU, isa_nobit };
static const enum isa_feature fpu_bitlist[]
= { ISA_ALL_FPU_INTERNAL, isa_nobit };
static const enum isa_feature quirk_bitlist[] = { ISA_ALL_QUIRKS, isa_nobit};
cl_target_option opts;
......
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